ON NCP1500DMR2 Dual mode pwm/linear buck converter Datasheet

NCP1500
Dual Mode PWM/Linear
BUCK Converter
The NCP1500 is a dual mode converter that operates as either a
pulse width modulated (PWM) buck converter or as a linear regulator.
The converter automatically transitions between the two modes. The
converter operates as a PWM when a synchronization signal is present
at the sync input. The converter operates as a linear regulator in the
absence of a synchronization signal. The PWM mode offers excellent
performance at normal to heavy loads at the sacrifice of output ripple
voltage. The linear mode offers excellent noise rejection at the
sacrifice of system efficiency. The user is able to select which mode
will give the best performance for a given operating condition.
Internal protection features include thermal shutdown with hysteresis
and cycle−by−cycle current limit in the PWM mode. Additionally, the
converter transitions into PFM mode at very light loads if a
synchronization signal is present and an output overvoltage condition
is detected.
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MARKING
DIAGRAM
8
Micro8
(MSOP−8)
DM SUFFIX
CASE 846A
8
1
1500
AYW
1
A = Assembly Location
Y = Year
W = Work Week
PWM Features
• Current Mode Control with Cycle−by−Cycle Current Limit
• Nominal Synchronization Frequency of 270 to 630 kHz
• Built−in Slope Compensation
PIN CONNECTIONS
Linear Regulator Features
• Low Output Noise
SHD
1
8
CB0
Overall Features
SYN
2
7
CB1
VO
3
6
GND
LX
4
5
VIN
• Thermal Shutdown with Hysteresis
• Digitally Programmable Output Voltage Between 4 Voltages:
•
•
•
•
•
1.0, 1.3, 1.5, and 1.8
Fast Transient Response
Input Voltage Range From 2.7 V to 5.4 V
Space Saving Micro8 Package
Low Shutdown Current of 0.18 A Typical
Pb−Free Package is Available
(Top View)
ORDERING INFORMATION
Device
NCP1500DMR2
Typical Applications
• Baseband Supplies for Portable Handsets
• PDAs
• Supplies for DSP Circuitry
L
1 SHD
CB0
8
2 SYN
CB1
7
3 VO
GND
6
4 LX
VIN
5
MBRM120
COUT
NCP1500DMR2G
Package
Shipping†
Micro8
4000 Tape/Reel
Micro8
(Pb−Free)
4000 Tape/Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
CIN
VIN
L = 15 H
CIN = 10 F
COUT = 10 F
Figure 1. Typical Operating Circuit
 Semiconductor Components Industries, LLC, 2004
February, 2004 − Rev. 4
1
Publication Order Number:
NCP1500/D
NCP1500
PIN FUNCTION DESCRIPTIONS
Pin #
Symbol
Pin Description
1
SHD
Device is placed in shutdown when SHD is driven low. In shutdown mode, the internal MOSFET and output
are turned off. Driven to high for normal operation. This pin is floating internally and needs to be tied to a
fixed source externally.
2
SYN
External Synchronization Clock Signal Input. If a clock signal is present at this pin, the device will go into
PWM mode. If SYN is driven low, the device operates in linear mode.
3
VO
Connected to internal voltage divider for feedback.
4
LX
Pin for the connection between the drain of the internal P−MOSFET and the external inductor.
5
VIN
Voltage Supply Input. Bypass with 10 F capacitor.
6
GND
Ground.
7
CB1
Control Bit 1 Input for output voltage level selection. Internally pulled low.
8
CB0
Control Bit 0 Input for output voltage level selection. Internally pulled low.
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Power Supply (Pin 5)
Rating
VIN
−0.3 to 6.0
V
Input/Output Pins
Pin 1−4 & Pin 7−8
VIO
−0.3 to 6.0
V
Thermal Characteristics
Micro8 Plastic Package
Thermal Resistance Junction to Air
RJA
240
°C/W
Operating Junction Temperature Range
TJ
−40 to +140
°C
Operating Ambient Temperature Range
TA
− 40 to +85
°C
Storage Temperature Range
Tstg
− 55 to +150
°C
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22−A114.
Machine Model (MM) 200 V per JEDEC standard: JESD22−A115.
2. Latch−up Current Maximum Rating: 150 mA per JEDEC standard: JESD78.
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2
NCP1500
ELECTRICAL CHARACTERISTICS (VIN = 3.6 V, VO = 1.5 V, TA = 25°C, Fsyn = 600 kHz 50% Duty Cycle sinewave with VH = 2.0 V
and VL = 0 V for PWM mode; TA = −40 to 85°C for Min/Max values, unless otherwise noted.)
Characteristic
Input Voltage Range
Symbol
Min
Typ
Max
Unit
VIN
2.7
−
5.4
V
ILEAK
−
−
0.06
−
0.3
10
A
SYN “H” Input Voltage
VSYNH
1.3
−
−
V
SYN “L” Input Voltage
VSYNL
−
−
1.1
V
SYN “H” Input Current
ISYNH
−
0
0.5
A
SYN “L” Input Current
ISYNL
−0.5
0
−
A
External Synchronization Frequency
FSYNC
270
−
630
kHz
CB “H” Input Voltage Threshold
VCBH
0.90
−
−
V
CB “L” Input Voltage Threshold
VCBL
−
−
0.63
V
CB “H” Input Current
ICBH
−
0.1
−
A
CB “L” Input Current
ICBL
−
0
−
A
SHD “H” Input Voltage Threshold
VSHDH
0.59
−
−
V
SHD “L” Input Voltage Threshold
VSHDL
−
−
0.26
V
SHD “H” Input Current
ISHDH
−
0.1
−
A
SHD “L” Input Current
ISHDL
−
0
−
A
0.941
1.235
1.425
1.710
0.99
1.30
1.50
1.80
1.050
1.365
1.575
1.890
−
−
1.0
2.0
−
−
−
−
1.0
13
−
−
Main FET Leakage Current (Pins 5 to 4) TA = 25°C
Main FET Leakage Current (Pins 5 to 4) TA = −40°C to 85°C
Mode Selection Pin
Output Level Selection Pins
Shutdown Pin
PWM Mode
Output Voltage (IOUT = 35 mA, TA = 25°C)
CB0, CB1 = (H, H)
CB0, CB1 = (H, L)
CB0, CB1 = (L, L)
CB0, CB1 = (L, H)
VOUT0
Line Regulation, Iout = 100 mA
3.0 to 3.6 V
3.0 to 4.2 V
Vout0
Load Regulation
50 to 120 mA
20 to 200 mA
Vout0
Minimum On−Time
Internal PFET ON−Resistance (ILX = 400 mA, VIN = 2.0 V)
Main Output Switch Current Limit
V
mV
mV
TONMIN
−
210
−
nsec
RDS(ON)_P
−
0.65
1.2
ILIM
−
800
−
mA
0.941
1.235
1.425
1.710
0.99
1.30
1.50
1.80
1.050
1.365
1.575
1.890
ISTARTLIN
80
−
−
mA
VOPFM
−
+5.0
+10
%
−
−
−
0.18
−
96
0.5
10
150
−
30
70
Linear Regulator Mode (Lx shorted to Vo)
Output Voltage (Iout = 0 mA, TA = 25°C)
CB0, CB1 = (H, H)
CB0, CB1 = (H, L)
CB0, CB1 = (L, L)
CB0, CB1 = (L, H)
Vout0
Startup Current Load in Linear Mode
V
Overvoltage Protection
Output Overvoltage Threshold in PWM Mode
Total Device
Power Supply Current
Standby (SHD tied low, VIN = 3.6 V, SYN tied low) TA = 25°C
TA = −40°C to 85°C
PWM Mode (SHD tied high, VIN = 3.6 V, Vout = 1.6 V, VCB0 = VCB1 = 0 V,
SYN @ 600 kHz/50% duty cycle, Iout = 0 mA)
Linear Mode (SHD tied high, VIN = 3.6 V, Vout = 1.5 V, SYN tied low,
Iout = 0 mA)
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3
A
ICC
NCP1500
SHD
Input
Voltage
VCC
Reference
Out +
−
C1
ILimit
PWM
SYN
Sync
Detection
and
Timing
Block
S
Mode Select
Q
+
Slope
Compression
−
SoftStart
−
+
Out
R
LX
PWM
Comparator
MBRM120
Thermal
Shutdown
−
Out
VO
+
−
CVP
Comparator
Out
Vref
CB0
Output
Voltage
Program
MUX
CB1
Ground
C1, C2
L
Value
Manufacturer
10 F, 6.3 V
15 H
Output
Voltage
C2
Vref + 5%
+
−
Error
Amplifier
Component
L
Linear
Control
Block
TDK, C3216X5R0J106M
TDK, RLF5018T−150MR76 (Iout = 300 mA)
Coilcraft, D01606T−153 (Iout = 300 mA)
TDK, NLC252018T−150 (Iout = 100 mA)
Figure 2. Typical Circuit with the Internal Schematic
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NCP1500
DETAILED OPERATING DESCRIPTION
Introduction
The NCP1500 is a dual mode regulator intended for use
in baseband supplies for portable equipment. Its unique
features provide power to the baseband circuitry while, at
the same time save valuable battery energy. When the
handset is idle, the user can activate the linear regulator
function. In this mode, the regulator provides a regulated
low current, low noise output voltage keeping the baseband
circuit biased. When the handset is in its normal operating
mode, the regulator synchronizes to the baseband clock and
turns into a switching regulator. This allows the regulator to
provide efficient power to the baseband circuit.
Figure 3 shows the waveform when the SYNC signal is
applied. After several cycles, the MODE select changes and
PWM operation is activated with the internal clock signal.
Reference/Shutdown
The NCP1500 uses an internal reference, typically at
0.8 V. An external shutdown pin is provided. When this pin
is pulled low, the reference and other circuitry are disabled,
placing the part into a low quiescent current standby mode.
In this mode, the pass device is off and the output voltage
will be zero. The typical standby current is 0.18 A.
Error Amplifier/Output Voltage Program
A fully compensated error amplifier is provided inside the
NCP1500. No external circuitry is required to stabilize the
operation of the NCP1500. The error amplifier provides an
error signal to both the PWM circuit and the linear regulator
circuit. The output of the error amplifier is directly
connected to the linear regulator control circuit. However,
the output of the error amplifier is connected first to a
subtraction circuit before going to the input of the PWM
comparator. The subtraction circuit is activated only during
an over current condition. During this condition, a signal
proportional to the amount of over current is subtracted from
the error amplifier signal. This subtraction results in a lower
signal applied to the PWM comparator, thus lowering the
output duty cycle.
The output voltage is digitally programmable up to four
voltages. Two program pins are provided to accomplish this
task. The program pins control a mux, which switch a bank
of resistors. The appropriate resistor bank is switched to the
error amplifier input, depending on the program input. The
following truth table can be used to program the output
voltage:
Operating Description
Synchronization Protocol and Mode Selection
The NCP1500 has a SYNC input. The device operates at
a fixed switch frequency determined by the frequency of the
synchronization signal applied. The part automatically
operates in PWM mode after synchronization pulses are
present for several cycles. The NCP1500 will output 2
pulses when a sync signal is present. The first is a PWM
pulse. This pulse ‘sets’ a latch that initiates output switch
conduction. The width of this pulse controls the minimum
on time in PWM mode. The second signal is a slope
compensation ramp. A ramp signal is generated. This signal
is summed with the current information before being fed
into the PWM comparator. The purpose of this circuit is to
provide stable operation at output switch duty cycles in
excess of 50%. The device automatically switches to linear
mode when the SYNC signal is removed for approximately
6.0 sec. It is recommended that the sync signal be
externally pulled low to enable the linear mode. Pulling
the pin high or open may cause portions of the circuit to
remain active, increasing the total current consumption of
the IC. The threshold level of the SYNC signal is typically
1.3 V. The duty cycle of the sync signal must be within 20
to 80%.
CB0
CB1
Output Voltage
0
0
1.5
0
1
1.8
1
0
1.3
1
1
1.0
Internal CLK Signal
VIN
Both program pins are internally pulled low. Thus, if the
input pins are left open, the output voltage will be 1.5 V.
0
External SYNC Signal
3.0
0
0
TIME ()
10
Figure 3. Timing Diagram of the SYNC Signal
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NCP1500
PWM Section
The PWM section consists of a PWM comparator, set
dominant latch, slope compensation circuit, current sense
circuit, and current limit circuit.
The NCP1500 operates as a current mode regulator in
PWM mode. In this mode, a PWM pulse from the
synchronization section initiates the output switch
conduction. Output switch conduction is terminated when the
peak inductor current reaches a threshold level established by
the error amplifier. The output switch conduction duty cycle
is allowed to go to 100% to increase transient load response
when going from light load to heavy load.
A reset dominant latch is provided in the NCP1500. A 3
input OR gate controls the reset pin. Any one of the 3 inputs
will terminate output switch conduction. Once terminated,
output switch conduction cannot begin again until the next
PWM pulse. The only state the NCP1500 does not switch
every cycle is if the 5% overvoltage comparator trips. When
the comparator trips, the switching regulator will remain off
until the voltage drops below the nominal voltage. This state
3.6040
is similar to a PFM mode of operation. Output switch
conduction can begin at the next PWM cycle after the OVP
input is reset.
Current mode controllers can exhibit an instability at duty
cycles over 50%. A slope compensation circuit is provided
inside the NCP1500 to overcome the potential instability.
Slope compensation consists of a ramp signal generated by
the synchronization block and adding this to the current
signal. The summed signal is then applied to the PWM
comparator.
A current limit feature is provided in the PWM mode only.
The current limit is set to allow peak switch current in excess
of 800 mA. It is implemented as a cycle−by−cycle current
limit. Each on−cycle is treated as a separate situation.
Current limiting is implemented by monitoring the output
switch transistor current buildup during conduction. An
error signal is generated upon sensing an over−current
condition. This signal is subtracted from the error amplifier
output. This in turn reduces the PWM comparison threshold
voltage, thus limiting the output duty cycle.
VIN
3.6000
3.5960
400 m
IFET
200 m
0.00
400 m
IL
300 m
200 m
400 m
Idiode
100 m
−200 m
1.01
VO
1.00
990 m
3.70
VLX
1.35
−1.00
198.0
201.0
204.0
207.0
TIME ()
Figure 4. PWM Waveforms During Normal Operation
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210.0
213.0
NCP1500
IOUT (mA)
Linear Mode Operation
The NCP1500 operates as a linear regulator if the
synchronization signal is absent. The part is designed to
provide up to 50 mA nominally in this mode. Transients of
up to 100 mA can be accommodated if the thermal impact
is low. The main output is in series with an external inductor.
This can cause a lag in the transient response of the device
when going from light load to heavy load. A bypass
transistor is incorporated to release the energy stored in the
inductor in order to avoid oscillation within the operation
range. (Patent Pending).
The following figure shows the transient step load
response of the NCP1500 in this mode of operation.
10
VOUT (mV)
1.0
0
500
1000
1500
0
500
1000
1500
20
0
−20
Time (s)
Figure 5. Load Transient Response in Linear Mode
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VIN = 3.6 V
VOUT = 1.8 V
CIN = 10 F
COUT = 10 F
NCP1500
Over Voltage Protection
NCP1500 has an overvoltage protection circuit that
protects the output during the PWM mode. Normally, in
PWM mode, the output switch will conduct at the onset of
every synchronization pulse. The minimum output duty
cycle is 3%. The output voltage will rise at minimum duty
cycle and a light load or no load condition is present at the
output. If the output rises more than 5% of the programmed
voltage, an overvoltage comparator will trip. This signal will
reset the PWM latch and hold it in a reset condition until the
output voltage decays below its threshold. The output will
then be allowed to switch at the next synchronization pulse.
This type of operation is usually referred to as PFM or skip
mode operation.
The following figure is a simulation of the regulator
during this condition:
Note: PP − Patent Pending
VIN
3.6040
3.6000
3.5960
Main FET Current
250.0 m
124.5 m
−1.000 m
20 m
Inductor Current (Fsync = 300 kHz)
10 m
0.0
−10 m
150 m
Diode Current
25.0 m
−100 m
4.00
VLX
1.75
−500 m
1.05150
VO (Set to 1 V)
1.05080
1.05010
Gate Voltage for Switching FET
4.0
2.0
0.0
175.00000
181.33333
187.66667
194.00000
200.33333
TIME ()
Figure 6. Waveforms of PFM Mode Operation During Over Voltage
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206.66667
213.00000
NCP1500
Thermal Shutdown
Internal Thermal Shutdown circuitry is provided to
protect the integrated circuit in the event at the maximum
junction temperature is exceeded. When activated, typically
at 150°C, the PWM latch is reset and the linear regulator
control circuitry is disabled. The thermal shutdown circuit
is designed with 25°C of hysteresis. This means that the
PWM latch and the regulator control circuitry cannot be
re−enabled until the die temperature drops by this amount.
This feature is provided to prevent catastrophic failures from
accidental device overheating. It is not intended as a
substitute for proper heatsinking. The NCP1500 is
contained in the Micro8 package.
VIN
SHD
1.8 V
1.5 V
1.3 V
1.0 V
VO
CB0
CB1
Figure 7. Power−Up and Power−Down Sequence
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NCP1500
APPLICATIONS INFORMATION
80
1.77
70
1.76
VO = 1.8 V
1.75
EFFICIENCY (%)
60
CB0 = Low
CB1 = High
VIN = 3.6 V
1.74
VOUT (V)
50
40
30
VO = 1.5 V
20
VO = 1.3 V
VO = 1.0 V
1.73
1.72
1.71
1.70
10
1.69
0
2.5
2.7
2.9
3.1
3.3
1.68
3.5
0
100
200
300
400
VIN, INPUT VOLTAGE (V)
IOUT, (mA)
Figure 8. Efficiency in Linear Mode Operation
vs. Input Voltage (IOUT = 10 mA)
Figure 9. Output Voltage vs. Output Current in
LDO Mode
90
85
80
EFFICIENCY (%)
1.8
VOUT (V)
VIN = 3.6 V
CIN = 10 F
COUT = 10 F
L = 15 H
PW Load = 8 msec, 3%
1.7
VOUT = 1.8 V
75
65
60
VIN = 3.6 V
CIN = 10 H
COUT = 10 H
L = 15 H
55
50
45
500
0
1000
40
1500
VOUT = 1.5 V
70
0
50
100
IOUT, (mA)
150
200
250
300
IOUT, (mA)
Figure 10. Output Voltage vs. Output Current
in PWM Mode
Figure 11. PWM Efficiency
Table 1. Efficiency Measurement in PWM Mode
VOUT
(V)
15
1.5
18
1.8
NOTE:
IOUT (mA)
VIN
(V)
1
5
10
20
30
40
60
80
100
200
300
2.5
44%
75%
82%
86%
87%
88%
88%
88%
90%
84%
80%
3.0
44%
68%
76%
82%
84%
85%
86%
86%
86%
83%
80%
3.6
49%
62%
71%
79%
80%
83%
83%
84%
84%
82%
80%
4.2
51%
64%
66%
75%
77%
80%
81%
82%
82%
82%
79%
2.5
48%
79%
86%
90%
90%
91%
91%
91%
91%
87%
84%
3.0
41%
73%
80%
85%
88%
88%
89%
89%
89%
86%
84%
3.6
45%
64%
76%
83%
84%
86%
86%
87%
87%
85%
84%
4.2
52%
63%
71%
78%
81%
83%
84%
85%
85%
85%
83%
See figure 1 for circuit configuration.
Cin = Cout = C3216X5R106M
L = D01606T−153
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NCP1500
PACKAGE DIMENSIONS
Micro8
(MSOP−8)
DM SUFFIX
CASE 846A−02
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. 846A−01 OBSOLETE, NEW STANDARD 846A−02.
−A−
−B−
K
PIN 1 ID
G
D 8 PL
0.08 (0.003)
M
T B
A
S
DIM
A
B
C
D
G
H
J
K
L
S
SEATING
−T− PLANE
0.038 (0.0015)
C
L
J
H
SOLDERING FOOTPRINT*
1.04
8X
0.041
0.38
0.015
3.20
0.126
6X
8X
4.24
0.167
0.65
0.0256
5.28
0.208
SCALE 8:1
mm inches
Micro8
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
−−−
1.10
0.25
0.40
0.65 BSC
0.05
0.15
0.13
0.23
4.75
5.05
0.40
0.70
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
−−−
0.043
0.010
0.016
0.026 BSC
0.002
0.006
0.005
0.009
0.187
0.199
0.016
0.028
NCP1500
Micro8 is a trademark of International Rectifier.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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For additional information, please contact your
local Sales Representative.
NCP1500/D
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