MITSUBISHI LSIs 1998.6.18 Ver.A M5M564R16DJ,TP-10,-12,-15 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM DESCRIPTION The M5M564R16D is a family of 65536-word by 16-bit PIN CONFIGURATION (TOP VIEW) static RAMs, fabricated with the high performance CMOS process and designed for high speed application. These devices operate on a single 3.3V supply, and are directly TTL compatible. ADDRESS INPUTS They include a power down feature as well. In write and read cycles, the lower and upper bytes are able to be controled either togethe or separately by LB and UB. DATA INPUTS/ OUTPUTS FEATURES •Fast access time M5M564R16DJ,TP-10 ... 10ns(max) M5M564R16DJ,TP-12 ... 12ns(max) M5M564R16DJ,TP-15 ... 15ns(max) •Low power dissipation Active .................. 363mW(typ) •Single +3.3V power supply •Fully static operation : No clocks, No refresh •Common data I/O •Easy memory expansion by S •Three-state outputs : OR-tie capability •OE prevents data contention in the I/O bus •Directly TTL compatible : All inputs and outputs •Separate control of lower and upper bytes by LB and UB APPLICATION (3.3V) VCC (0V) GND DATA INPUTS/ OUTPUTS WRITE CONTROL INPUT ADDRESS INPUTS DQ5 DQ6 DQ7 DQ8 W A5 A6 A7 A8 N.C 34 A15 A14 ADDRESS INPUTS A13 OUTPUT OE INPUT ENABLE UB BYTE CONTROL LB INPUTS DQ16 DQ15 DATA INPUTS/ DQ14 OUTPUTS DQ13 GND (0V) 33 VCC (3.3V) 32 DQ12 DQ11 DQ10 DQ9 N.C A12 A11 A10 A9 N.C 1 44 2 43 3 42 4 41 5 40 6 39 7 8 9 10 11 12 13 14 15 16 M5M564R16DJ,TP CHIP SELECT INPUTS A0 A1 A2 A3 A4 S DQ1 DQ2 DQ3 DQ4 38 37 36 35 31 30 29 17 28 18 27 19 26 20 25 21 24 22 23 DATA INPUTS/ OUTPUTS ADDRESS INPUTS Outline 44P0K(J) 44P3W-H(TP) PACKAGE High-speed memory system M5M564R16DJ M5M564R16DTP : 44pin 400mil SOJ : 44pin 400mil TSOP(II) FUNCTION The operation mode of the M5M564R16D is determined by a combination of the device control inputs S, W, OE, LB, and UB. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with low level LB and/or low level UB and low level S. The address must be set-up before write cycle and must be stable during the entire cycle. The data is latched into a cell on the traling edge of W, LB, UB or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while LB and/or UB and S are in an active state. (LB and/or UB=L, S=L) When setting LB at a high level and other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enable, and lower-Byte are in a non-selectable mode. And when setting UB at a high level and other pins are in an active state, lower-Byte are in a selectable mode in which both reading and writing are enable, and upperByte are in a non-selectable mode. When setting LB and UB at a high level or S at high level, the chip is in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by LB, UB and S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time. MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs M5M564R16DJ,TP-10,-12,-15 1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM FUNCTION TABLE Read cycle All Bytes DQ1~8 D OUT Read cycle Upper Bytes High-impedance Mode S L L W H H OE L L LB L H UB L L L H L L H L L X L L Read cycle Lower Bytes Write cycle All Bytes L L X H L Write cycle Upper Bytes L L X L H Write cycle Lower Bytes L H H X X L X X H H H X X X X D DQ9~16 D OUT D OUT Icc Active Active Active D IN High-impedance D IN High-impedance D IN Active D IN High-impedance Active Output disable High-impedance High-impedance Active Non selection High-impedance High-impedance Stand by OUT Active 18 19 20 21 18 OUTPUT BUFFERS 3 4 5 MEMORY ARRAY 512 ROWS 2048 COLUMNS 512 7 8 9 10 13 14 15 16 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 29 30 31 32 35 36 37 38 DQ 9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 11 33 VCC DATA INPUTS/ OUTPUTS DATA INPUT BUFFERS 1 2 ROW ADDRESS DECODERS ADDRESS INPUTS A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW INPUT BUFFERS BLOCK DIAGRAM S 6 WRITE CONTROL INPUT W 17 OUTPUT ENABLE INPUT OE 41 UPPER BYTE CONTROL INPUTS UB 40 LOWER BYTE CONTROL INPUTS LB 39 COLUMN I/O CIRCUITS COLUMN ADDRESS DECODERS 14 OUTPUT BUFFERS 2048 CHIP SELECT INPUTS DATA INPUTS/ OUTPUTS DATA INPUT BUFFERS COLUMN INPUT BUFFERS 24 25 26 27 42 43 12 34 (3.3V) GND (0V) 44 A9 A10 A11 A12 A13 A14 A15 ADDRESS INPUTS MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs M5M564R16DJ,TP-10,-12,-15 1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS V cc Parameter Supply voltage VI Input voltage Symbol Conditions Ratings With respect to GND - 2.0*~ 4.6 - 2.0*~ Vcc+0.5 - 2.0*~ Vcc VO Output voltage Power dissipation Pd Operating temperature T opr Tstg(bias) Storage temperature(bias) Tstg 1000 Ta=25°C V V mW - 10 ~ 85 °C °C - 65 ~ 150 °C 0 ~ 70 Storage temperature Unit V *Pulse width ≤5ns, In case of DC: - 0.5V DC ELECTRICAL CHARACTERISTICS Symbol Parameter VIH VIL VOH VOL II High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current IOZ Output current in off-state I CC1 (Ta=0~70°C, Vcc=3.3V Active supply current (TTL level) +10% -5% ,unless otherwise noted) Condition Min 2.0 IOH = - 4mA IOL= 8mA V I = 0 ~ Vcc VI (S)= VIH VO= 0 ~ Vcc Limits Typ Max Vcc+0.3 0.8 0.4 2 V V V V uA 2 uA 2.4 AC(10ns cycle) AC(12ns cycle) AC(15ns cycle) DC AC(10ns cycle) AC(12ns cycle) AC(15ns cycle) DC VI (S)= VIL other inputs V IH or VIL Output-open(duty 100%) I CC2 Stand-by supply current (TTL level) VI (S)= VIH I CC3 Stand-by current (MOS level) VI (S)= Vcc - 0.2V other inputs V I≤0.2V or VI≥Vcc - 0.2V 110 Unit 200 195 190 140 70 65 60 40 mA mA 10 mA Max 6 8 Unit Note 1: Direction for current flowing into an IC is positive (no mark). CAPACITANCE Symbol CI CO (Ta=0~70°C , Vcc=3.3V +10% -5% ,unless Parameter Input capacitance Output capacitance otherwise noted) Test Condition Min Limit Typ VI =GND,V i =25mVrms,f=1MHz Vo =GND,V o =25mVrms,f=1MHz pF pF Note 2: C I,CO are periodically sampled and are not 100% tested. AC ELECTRICAL CHARACTERISTICS (Ta= 0~70 °C ,VCC =3.3V +10% -5% ,unless otherwise noted) (1) MEASUREMENT CONDITION Input pulse levels ................................... VIH=3.0V,VIL=0.0V OUTPUT 5.0V Z0=50Ω 480Ω Input rise and fall time ................................................... 3ns DQ Input timing reference levels ...................... VIH=1.5V,V IL=1.5V Output timing reference levels ................ VOH=1.5V, V OL=1.5V Output loads ....................................................... Fig1 ,Fig2 RL=50Ω VL=1.5V Fig.1 Output load MITSUBISHI ELECTRIC DQ 255Ω ( 5pF Including scope and JIG ) Fig.2 Output load for t en, t dis 3 MITSUBISHI LSIs M5M564R16DJ,TP-10,-12,-15 1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM READ CYCLE Limits Symbol Parameter M5M564R16D-10 Max Min tCR ta(A) ta(S) ta(OE) ta(B) Read cycle time 10 M5M564R16D-12 Max Min 12 M5M564R16D-15 Min Max 15 ns Address access time 10 12 15 Chip select access time 10 5 12 6 15 7 Output enable access time LB,UB access time tdis(S) tdis(OE) Output disable time after S high tdis(B) ten(S) ten(OE) ten(B) tv(A) Output disable time after LB,UB high tPU tPD Power-up time after chip selection Output disable time after OE high Output enable time after S low Output enable time after OE low Output enable time after LB,UB low Data valid time after address change 0 0 0 4 3 3 4 0 5 5 5 5 6 6 6 6 0 0 0 4 3 3 4 0 10 Power down time after chip selection 0 0 0 4 3 3 4 0 12 Unit 7 7 7 7 ns ns ns ns ns ns ns ns ns ns ns ns 15 ns Write cycle Limits Symbol Parameter M5M564R16D-10 Min tCW Write cycle time tw(W) tsu(B) tsu(A)1 tsu(A)2 Write pulse width LB,UB setup time Address setup time(W) Address setup time(S) 10 9 9 0 0 9 5 tsu(S) tsu(D) th(D) trec(W) Chip select setup time tdis(W) tdis(OE) ten(W) ten(OE) ten(B) tsu(A-WH) Output disable time after W low tsu(A-SH) tsu(A-BH) Address to S High 0 0 0 0 9 9 Address to LB,UB High 9 Data setup time Data hold time Write recovery time Output disable time after OE high Output enable time after W high Output enable time after OE low Output enable time after LB,UB low Address to W High Max 0 0 0 5 5 M5M564R16D-12 Min 12 10 10 0 0 10 6 0 0 0 0 0 0 0 10 10 10 Max M5M564R16D-15 Min Max ns ns 15 12 12 0 6 6 0 12 7 0 0 0 0 0 0 0 12 12 12 Unit ns ns ns ns ns ns 7 7 ns ns ns ns ns ns ns ns ns MITSUBISHI ELECTRIC 4 MITSUBISHI LSIs M5M564R16DJ,TP-10,-12,-15 1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle 1 A 0~15 t CR VIH VIL ta(A) tv(A) tv(A) DQ1~16 VOH PREVIOUS DATA VALID VOL W=H LB=L S=L UB=L UNKNOWN DATA VALID OE=L Read cycle 2 (Note 3) t CR VIH S VIL tdis(S) ta(S) (Note 4) ten(S) DQ1~16 (Note 4) VOH UNKNOWN DATA VALID VOL tPU ICC1 Icc tPD 50% ICC2 W=H 50% UB=L OE=L LB=L Note 3. Addresses valid prior to or coincident with S transition low. 4. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2. Read cycle 3 (Note 5) t CR VIH OE VIL ta(OE) (Note 4) DQ1~16 VOH tdis(OE) (Note 4) ten(OE) UNKNOWN DATA VALID VOL W=H UB=L S=L LB=L Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE)) MITSUBISHI ELECTRIC 5 MITSUBISHI LSIs M5M564R16DJ,TP-10,-12,-15 1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM Read cycle 4 (Note 6) UB,LB t CR VIH VIL tdis(B) ta(B) (Note 4) DQ1~16 (Note 4) ten(B) VOH UNKNOWN DATA VALID VOL W=H OE=L S=L Note 6. Addresses , S and OE valid prior to LB,UB transition low by (ta(A)-ta(B)), (ta(S)-ta(B)), (ta(OE)-ta(B)). Write cycle (W control mode) t CW A 0~15 VIH VIL S VIH VIL tsu(S) (Note 7) (Note 7) tsu(A-WH) OE VIH VIL tsu (A) W tw(W) trec (W) VIH VIL tsu(B) LB,UB VIH VIL (Note 7) (Note 7) tsu (D) th(D) DQ1~16 (Input Data) VIH VIL DATA STABLE tdis(W) (Note 4) tdis(OE) DQ1~16 (Output Data) VOH VOL ten(OE) (Note 4) ten(W) Hi-Z Note 7: Hatching indicates the state is don't care. 8: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance. 9: t en,tdis are periodically sampled and are not 100% tested. MITSUBISHI ELECTRIC 6 MITSUBISHI LSIs M5M564R16DJ,TP-10,-12,-15 1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM Write cycle(S control) t CW A 0~15 VIH VIL tsu(A) S VIH VIL W VIH VIL tsu (A-SH) tsu (S) trec(W) tw(W) (Note 6) (Note 6) tsu(B) LB,UB VIH VIL (Note 6) (Note 6) tsu (D) DQ1~16 (Input Data) VIH VIL DATA STABLE tdis(W) (Note 4) DQ1~16 (Output Data) VOH VOL th(D) (Note 4) ten(B) ten(S) Hi-Z (Note 8) Write cycle(LB,UB control) t CW A 0~15 VIH VIL tsu(S) S VIH VIL (Note 6) (Note 6) tw(W) W VIH VIL (Note 6) tsu(A) LB,UB tsu(A-BH) tsu (B) (Note 6) trec(W) VIH VIL tsu (D) DQ1~16 (Input Data) VIH VIL DATA STABLE tdis(W) (Note 4) DQ1~16 (Output Data) VOH VOL th(D) ten(B) (Note 4) ten(S) Hi-Z (Note 8) MITSUBISHI ELECTRIC 7