ON MC74LCX652 Low.voltage cmos octal transceiver/ registered transceiver with dual enable Datasheet

SEMICONDUCTOR TECHNICAL DATA
&-&$*! *$
(%) #, ( !#)* ( (%) #, ( #*" +$ %$
#*" &$ (%* %'+*) % +*'+*)
** &%%, (*#%!
The MC74LCX652 is a high performance, non–inverting octal
transceiver/registered transceiver operating from a 2.7 to 3.6V supply.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5V allows
MC74LCX652 inputs to be safely driven from 5V devices. The
MC74LCX652 is suitable for memory address driving and all TTL level
bus oriented transceiver applications.
LOW–VOLTAGE CMOS
OCTAL TRANSCEIVER/
REGISTERED TRANSCEIVER
WITH DUAL ENABLE
Data on the A or B bus will be clocked into the registers as the
appropriate clock pin goes from a LOW–to–HIGH logic level. Two Output
Enable pins (OEBA, OEAB) are provided to control the transceiver
outputs. In the transceiver mode, data present at the high impedance port
may be stored in either the A or the B register or in both. The select
controls (SBA, SAB) can multiplex stored and real–time (transparent
mode) data. In the isolation mode (both outputs disabled), A data may be
stored in the B register or B data may be stored in the A register. When in
the real–time mode, it is possible to store data without using the internal
registers by simultaneously enabling OEAB and OEBA. In this
configuration, each output reinforces its input (data retention is not
guaranteed in this mode).
•
•
•
•
•
•
•
•
DW SUFFIX
24–LEAD PLASTIC SOIC PACKAGE
CASE 751E–04
SD SUFFIX
24–LEAD PLASTIC SSOP PACKAGE
CASE 940D–03
Designed for 2.7 to 3.6V VCC Operation
5V Tolerant — Interface Capability With 5V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0V
LVTTL Compatible
LVCMOS Compatible
DT SUFFIX
24–LEAD PLASTIC TSSOP PACKAGE
CASE 948H–01
24mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10µA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500mA
• ESD Performance: Human Body Model >2000V; Machine Model >200V
VCC CBA SBA OEBA B0
24
23
22
21
20
1
2
3
B1
B2
B3
B4
B5
B6
B7
19
18
17
16
15
14
13
8
A4
9
10
A6
11
A5
A7
12
GND
4
5
6
7
CAB SAB OEAB A0
A1
A2
A3
PIN NAMES
Pins
Function
A0–A7
B0–B7
CAB, CBA
SAB, SBA
OEBA, OEAB
Side A Inputs/Outputs
Side B Inputs/Outputs
Clock Pulse Inputs
Select Control Inputs
Output Enable Inputs
Figure 1. 24–Lead Pinout (Top View)
3/97
 Motorola, Inc. 1997
1
REV 1
MC74LCX652
1
CBA
3
OEAB
OEBA
SBA
21
Figure 2. Logic Diagram
22
2
SAB
CAB
23
C
Q
A0
D
C
Q
B0
D
1 of 8 Channels
To 7 Other Channels
FUNCTION TABLE
Inputs
Data Ports
Operating Mode
OEAB
OEBA
L
H
H
CAB
SBA
An
Bn
Input
Input
↑
X
X
X
X
Isolation, Hold Storage
↑
↑
X
X
l
h
l
h
Store A and/or B Data
Input
Output
H
↑
X*
X*
L
X
L
H
L
H
H
X
X
QA
L
X
l
h
L
H
H
X
L
H
QA
QA
Output
Input
L
X*
X*
H
SAB
↑
↑
L
CBA
↑
↑
↑
Stored A Data to B Bus
Real Time A Data to B Bus; Store A Data
Clock A Data to B Bus; Store A Data
X
L
L
H
L
H
Real Time B Data to A Bus
X
H
QB
X
Stored B Data to A Bus
X
L
L
H
l
h
Real Time B Data to A Bus; Store B Data
X
H
QB
QB
L
H
Clock B Data to A Bus; Store B Data
Output
Output
QB
QA
L
↑
Real Time A Data to B Bus
H
H
Stored A Data to B Bus,
Stored B Data to A Bus
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Low–to–High Clock Transition; L = Low Voltage Level; l = Low Voltage Level One Setup
Time Prior to the Low–to–High Clock Transition; X = Don’t Care; ↑ = Low–to–High Clock Transition; ↑ = NOT Low–to–High Clock Transition; QA = A input storage register;
QB = B input storage register; * = The clocks are not internally gated with either the Output Enables or the Source Inputs. Therefore, data at the A or B ports may be
clocked into the storage registers, at any time. For ICC reasons, Do Not Float Inputs.
MOTOROLA
2
LCX DATA
BR1339 — REV 3
MC74LCX652
L
CAB
X
CBA
X
SAB
OEAB
OEBA
CAB
CBA
SAB
SBA
L
H
H
X
X
L
X
X
Transfer A Stored Data to Bus B
or B Stored Data to Bus A or
Both at the Same Time
BUS A
BUS B
Store Data from Bus A, Bus B or
Bus A and Bus B
BUS A
BUS B
SBA
BUS B
L
OEBA
BUS A
BUS A
OEAB
Real Time Transfer – Bus A to
Bus B
BUS B
Real Time Transfer – Bus B to
Bus A
OEAB
OEBA
CAB
CBA
SAB
SBA
OEAB
OEBA
CAB
CBA
SAB
SBA
X
L
L
H
X
H
↑
X
↑
X
↑
↑
X
X
X
X
X
X
H
L
H
H
L
L
H or L
X
H or L
X
H or L
H or L
H
X
H
X
H
H
BUS A
BUS A
BUS B
Isolation
BUS B
Store Bus A in Both Registers or
Store Bus B in Both Registers
OEAB
OEBA
CAB
CBA
SAB
SBA
OEAB
OEBA
CAB
CBA
SAB
SBA
H
L
H
L
↑
↑
↑
↑
L
X
X
L
L
H
H or L
H or L
X
X
Figure 3. Bus Applications
LCX DATA
BR1339 — REV 3
3
MOTOROLA
MC74LCX652
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
VCC
DC Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
Value
Condition
Unit
–0.5 to +7.0
V
–0.5 ≤ VI ≤ +7.0
V
–0.5 ≤ VO ≤ +7.0
Output in 3–State
V
–0.5 ≤ VO ≤ VCC + 0.5
Note 1.
V
IIK
DC Input Diode Current
–50
VI < GND
mA
IOK
DC Output Diode Current
–50
VO < GND
mA
+50
VO > VCC
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
–65 to +150
°C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
1. Output in HIGH or LOW State. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
2.0
1.5
3.3
3.3
3.6
3.6
V
0
5.5
V
0
0
VCC
5.5
V
HIGH Level Output Current, VCC = 3.0V – 3.6V
–24
mA
IOL
LOW Level Output Current, VCC = 3.0V – 3.6V
24
mA
IOH
HIGH Level Output Current, VCC = 2.7V – 3.0V
–12
mA
IOL
LOW Level Output Current, VCC = 2.7V – 3.0V
TA
Operating Free–Air Temperature
∆t/∆V
Input Transition Rise or Fall Rate, VIN from 0.8V to 2.0V,
VCC = 3.0V
VCC
Supply Voltage
VI
Input Voltage
VO
Output Voltage
IOH
Operating
Data Retention Only
(HIGH or LOW State)
(3–State)
12
mA
–40
+85
°C
0
10
ns/V
DC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C
Symbol
Characteristic
VIH
HIGH Level Input Voltage (Note 2.)
VIL
LOW Level Input Voltage (Note 2.)
VOH
HIGH Level Output Voltage
VOL
LOW Level Output Voltage
Condition
Min
2.7V ≤ VCC ≤ 3.6V
2.0
2.7V ≤ VCC ≤ 3.6V
Max
V
0.8
2.7V ≤ VCC ≤ 3.6V; IOH = –100µA
VCC – 0.2
VCC = 2.7V; IOH = –12mA
2.2
VCC = 3.0V; IOH = –18mA
2.4
VCC = 3.0V; IOH = –24mA
2.2
Unit
V
V
2.7V ≤ VCC ≤ 3.6V; IOL = 100µA
0.2
VCC = 2.7V; IOL= 12mA
0.4
VCC = 3.0V; IOL = 16mA
0.4
VCC = 3.0V; IOL = 24mA
0.55
V
2. These values of VI are used to test DC electrical characteristics only.
MOTOROLA
4
LCX DATA
BR1339 — REV 3
MC74LCX652
DC ELECTRICAL CHARACTERISTICS (continued)
TA = –40°C to +85°C
Symbol
Characteristic
Condition
Min
Max
Unit
II
Input Leakage Current
2.7V ≤ VCC ≤ 3.6V; 0V ≤ VI ≤ 5.5V
±5.0
µA
IOZ
3–State Output Current
2.7 ≤ VCC ≤ 3.6V; 0V ≤ VO ≤ 5.5V;
VI = VIH or V IL
±5.0
µA
IOFF
Power–Off Leakage Current
VCC = 0V; VI or VO = 5.5V
10
µA
ICC
Quiescent Supply Current
2.7 ≤ VCC ≤ 3.6V; VI = GND or VCC
10
µA
2.7 ≤ VCC ≤ 3.6V; 3.6 ≤ VI or VO ≤ 5.5V
±10
µA
2.7 ≤ VCC ≤ 3.6V; VIH = VCC – 0.6V
500
µA
∆ICC
Increase in ICC per Input
AC CHARACTERISTICS (tR = tF = 2.5ns; CL = 50pF; RL = 500Ω)
Limits
TA = –40°C to +85°C
VCC = 3.0V to 3.6V
Symbol
Parameter
Waveform
Min
VCC = 2.7V
Max
Min
Max
Unit
fmax
Clock Pulse Frequency
3
150
tPLH
tPHL
Propagation Delay
Input to Output
1
1.5
1.5
7.0
7.0
1.5
1.5
8.0
8.0
MHz
ns
tPLH
tPHL
Propagation Delay
Clock to Output
3
1.5
1.5
8.5
8.5
1.5
1.5
9.5
9.5
ns
tPLH
tPHL
Propagation Delay
Select to Output
1
1.5
1.5
8.5
8.5
1.5
1.5
9.5
9.5
ns
tPZH
tPZL
Output Enable Time to
High and Low Level
2
1.5
1.5
8.5
8.5
1.5
1.5
9.5
9.5
ns
tPHZ
tPLZ
Output Disable Time From
High and Low Level
2
1.5
1.5
8.5
8.5
1.5
1.5
9.5
9.5
ns
ts
Setup Time, HIGH or LOW Data to Clock
3
2.5
2.5
ns
th
Hold Time, HIGH or LOW Data to Clock
3
1.5
1.5
ns
tw
Clock Pulse Width, HIGH or LOW
3
3.3
3.3
ns
tOSHL
tOSLH
Output–to–Output Skew
(Note 3.)
1.0
1.0
ns
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter
guaranteed by design.
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol
Characteristic
Condition
VOLP
Dynamic LOW Peak Voltage (Note 4.)
VCC = 3.3V, CL = 50pF, VIH = 3.3V, VIL = 0V
Min
Typ
0.8
Max
Unit
V
VOLV
Dynamic LOW Valley Voltage (Note 4.)
VCC = 3.3V, CL = 50pF, VIH = 3.3V, VIL = 0V
0.8
V
4. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is
measured in the LOW state. The LCX652 is characterized with 7 outputs switching with 1 output held LOW.
LCX DATA
BR1339 — REV 3
5
MOTOROLA
MC74LCX652
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Condition
Typical
Unit
CIN
Input Capacitance
VCC = 3.3V, VI = 0V or VCC
7
pF
CI/O
Input/Output Capacitance
VCC = 3.3V, VI = 0V or VCC
8
pF
CPD
Power Dissipation Capacitance
10MHz, VCC = 3.3V, VI = 0V or VCC
25
pF
2.7V
An, Bn,
SBA, SAB
1.5V
0V
tPLH, tPHL
VOH
Bn, An
1.5V
VOL
WAVEFORM 1 – SAB to B and SBA to A, An to Bn PROPAGATION DELAYS
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
2.7V
OEBA
1.5V
1.5V
0V
OEAB
tPZH
tPHZ
VOH – 0.3V
1.5V
An, Bn
≈ 0V
tPZL
An, Bn
tPLZ
≈ 3.0V
1.5V
VOL + 0.3V
WAVEFORM 2 – OEBA/OEAB to An/Bn OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
Figure 4. AC Waveforms
MOTOROLA
6
LCX DATA
BR1339 — REV 3
MC74LCX652
2.7V
An, Bn
1.5V
0V
ts
th
2.7V
CAB,
CBA
tw
1.5V
1.5V
0V
fmax
tPLH, tPHL
VOH
Bn, An
1.5V
VOL
WAVEFORM 3 – CLOCK to Bn/An PROPAGATION DELAYS, CLOCK MINIMUM PULSE WIDTH,
An/Bn to CLOCK SETUP AND HOLD TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted
tw
NEGATIVE
PULSE
1.5V
1.5V
POSITIVE
PULSE
1.5V
1.5V
tw
WAVEFORM 4 – INPUT PULSE DEFINITION
tR = tF = 2.5ns, 10% to 90% of 0V to 2.7V
Figure 5. AC Waveforms (continued)
VCC
PULSE
GENERATOR
R1
DUT
CL
RT
TEST
6V
OPEN
GND
RL
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V
Open Collector/Drain tPLH and tPHL
tPZH, tPHZ
6V
GND
CL = 50pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 6. Test Circuit
LCX DATA
BR1339 — REV 3
7
MOTOROLA
MC74LCX652
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
–A
–
24
13
–B
–
1
P 12 PL
0.010 (0.25)
M
B
M
12
J
D 24 PL
0.010 (0.25)
T A
M
B
S
DIM
A
B
C
D
F
G
J
K
M
P
R
S
F
R X 45°
C
–T
–
SEATING
PLANE
M
K
G 22 PL
MILLIMETERS
MIN
MAX
15.25 15.54
7.60
7.40
2.65
2.35
0.49
0.35
0.90
0.41
1.27 BSC
0.32
0.23
0.29
0.13
8°
0°
10.05 10.55
0.25
0.75
INCHES
MIN
MAX
0.601 0.612
0.292 0.299
0.093 0.104
0.014 0.019
0.016 0.035
0.050 BSC
0.009 0.013
0.005 0.011
0°
8°
0.395 0.415
0.010 0.029
SD SUFFIX
PLASTIC SSOP PACKAGE
CASE 940D–03
ISSUE B
24X
K REF
0.12 (0.005)
M
T U
S
V
ÇÇÇÇ
ÉÉÉ
ÇÇÇÇ
ÉÉÉ
ÇÇÇÇ
S
K
L/2
24
J
13
K1
B
L
J1
SECTION N–N
PIN 1
IDENT
1
12
0.20 (0.008)
M
T U
0.25 (0.010)
–U–
A
–V–
N
M
S
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4 DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
5 DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF K DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR INTRUSION
SHALL NOT REDUCE DIMENSION K BY MORE
THAN 0.07 (0.002) AT LEAST MATERIAL
CONDITION.
6 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7 DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
N
F
DETAIL E
0.076 (0.003)
–T–
SEATING
PLANE
–W–
C
D
G
H
MOTOROLA
DETAIL E
8
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
8.07
8.33
5.20
5.38
1.73
1.99
0.05
0.21
0.63
0.95
0.65 BSC
0.44
0.60
0.09
0.20
0.09
0.16
0.25
0.38
0.25
0.33
7.65
7.90
0_
8_
INCHES
MIN
MAX
0.317
0.328
0.205
0.212
0.068
0.078
0.002
0.008
0.024
0.037
0.026 BSC
0.017
0.024
0.003
0.008
0.003
0.006
0.010
0.015
0.010
0.013
0.301
0.311
0_
8_
LCX DATA
BR1339 — REV 3
MC74LCX652
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948H–01
ISSUE O
24X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
V
S
S
2X
24
L/2
13
B
–U–
L
PIN 1
IDENT.
12
1
0.15 (0.006) T U
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4 DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5 DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7 DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
S
A
–V–
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
C
0.10 (0.004)
–T– SEATING
PLANE
G
D
H
–W–
MILLIMETERS
MIN
MAX
7.70
7.90
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.303
0.311
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
DETAIL E
N
0.25 (0.010)
K
ÉÉ
ÇÇÇ
ÇÇÇ
ÉÉ
K1
J1
M
N
F
SECTION N–N
DETAIL E
J
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or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315
Mfax: [email protected] – TOUCHTONE 602–244–6609
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
INTERNET: http://www.mot.com/SPS/
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LCX DATA
BR1339 — REV 3
9
MC74LCX652/D
MOTOROLA
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