TI DAC8802 Dual, serial input 14-bit multiplying digital-to-analog converter Datasheet

DA
DAC8802
C8
802
www.ti.com
SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005
Dual, Serial Input 14-Bit Multiplying Digital-to-Analog Converter
FEATURES
DESCRIPTION
•
•
•
The DAC8802 is a dual, 14-bit, current-output
digital-to-analog converter (DAC) designed to operate
from a single +2.7 V to 5.5 V supply.
•
•
•
•
•
•
•
•
•
•
Relative Accuracy: 1 LSB Max
Differential Nonlinearity: 1 LSB Max
2-mA Full-Scale Current ±20%,
with VREF = ±10 V
0.5 µs Settling Time
Midscale or Zero-Scale Reset
Separate 4Q Multiplying Reference Inputs
Reference Bandwidth: 10 MHz
Reference Dynamics: –105 dB THD
SPI™-Compatible 3-Wire Interface:
50 MHz
Double Buffered Registers Enable
Simultaneous Multichannel Change
Internal Power-On Reset
Industry-Standard Pin Configuration
The applied external reference input voltage VREF
determines the full-scale output current. An internal
feedback resistor (RFB) provides temperature tracking
for the full-scale output when combined with an
external I-to-V precision amplifier.
A doubled-buffered, serial data interface offers
high-speed, 3-wire, SPI and microcontroller
compatible inputs using serial data in (SDI), clock
(CLK), and a chip-select (CS). A common
level-sensitive load DAC strobe (LDAC) input allows
simultaneous update of all DAC outputs from
previously loaded input registers. Additionally, an
internal power-on reset forces the output voltage to
zero at system turn-on. An MSB pin allows system
reset assertion (RS) to force all registers to zero code
when MSB = 0, or to half-scale code when MSB = 1.
APPLICATIONS
•
•
•
Automatic Test Equipment
Instrumentation
Digitally Controlled Calibration
The DAC8802 is available in an TSSOP-16 package.
VREFA B
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
A0
A1
SDI
RFBA
14
Input
Register
R
DAC A
Register
R
DAC A
IOUTA
AGNDA
RFBB
Input
Register
R
DAC B
Register
R
DAC B
IOUTB
AGNDB
CS
CLK
EN
DAC A
B
Decode
DGND
Power-On
Reset
RS
MSB
LDAC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
DAC8802
www.ti.com
SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
SPECIFIED
TEMPERATURE
RANGE
PACKAGELEAD
PACKAGE
DESIGNATOR
DAC8802
±1
±1
–40°C to +85°C
TSSOP-16
PW
(1)
ORDERING
NUMBER
TRANSPORT
MEDIA,
QUANTITY
DAC8802IPW
Tubes, 90
DAC8802IPWR
Tape and Reel, 2500
For the most current specifications and package information, see the Package Option Addendum located at the end of this document, or
see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
DAC8802
UNIT
–0.3 to +8
V
VREF to GND
–18 to +18
V
Logic inputs and output to GND
– 0.3 to + 8
V
V(IOUT) to GND
– 0.3 to VDD + 0.3
V
AGNDX to DGND
–0.3 to +0.3
V
±50
mA
(TJmax – TA)/θJA
W
Thermal resistance, θJA
100
°C/W
Maximum junction temperature (TJmax)
150
°C
– 40 to +85
°C
– 65 to + 150
°C
VDD to GND
Input current to any pin except supplies
Package power dissipation
Operating temperature range
Storage temperature range
(1)
2
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.
DAC8802
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SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS
(1)
VDD = 2.7 V to 5.5 V, IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B = 10 V, TA = full operating temperature range, unless
otherwise noted.
DAC8802
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE (2)
Resolution
Relative accuracy
Differential nonlinearity
14
Bits
INL
±1
LSB
DNL
±1
LSB
10
nA
Output leakage current
IOUTX
Full-scale gain error
GFSE
Full-scale tempco (3)
TCVFS
Feedback resistor
RFBX
Data = 0000h, TA = 25°C
Data = 0000h, TA = TA max
±0.75
Data = 3FFFh
VDD = 5 V
20
nA
±4
mV
1
ppm/°C
5
kΩ
REFERENCE INPUT
VREFX Range
VREFX
–15
Input resistance
RREFX
4
Input resistance match
RREFX
Input capacitance (3)
CREFX
Channel-to-channel
5
15
V
6
kΩ
1
%
5
pF
ANALOG OUTPUT
Output current
Output capacitance (3)
IOUTX
Data = 3FFFh
COUTX
Code-dependent
1.6
2.5
50
mA
pF
LOGIC INPUTS AND OUTPUT
Input low voltage
VIL
Input high voltage
VIH
VDD = +2.7 V
0.6
V
VDD = +5 V
0.8
V
VDD = +2.7 V
2.1
V
VDD = +5 V
2.4
V
Input leakage current
IIL
1
µA
Input capacitance (3)
CIL
10
pF
0.4
V
Logic output low voltage
Logic output high voltage
INTERFACE TIMING (3),
Clock width high
Clock width low
VOL
IOL = 1.6 mA
VOH
IOH = 100 µA
4
V
tCH
25
ns
(4)
tCL
25
ns
CS to Clock setup
tCSS
0
ns
Clock to CS hold
tCSH
25
tPD
2
Clock to SDO prop delay
Load DAC pulsewidth
ns
20
ns
tLDAC
25
ns
Data setup
tDS
20
ns
Data hold
tDH
20
ns
Load setup
tLDS
5
ns
Load hold
tLDH
25
ns
(1)
(2)
(3)
(4)
Specifications subject to change without notice.
All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OPA277 I-to-V converter
amplifier. The DAC8802 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at +25°C.
These parameters are specified by design and not subject to production testing.
All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
3
DAC8802
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SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7 V to 5.5 V, IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B = 10 V, TA = full operating temperature range, unless
otherwise noted.
DAC8802
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CHARACTERISTICS
Power supply range
VDD
Positive supply current
IDD
Power dissipation
5.5
V
Logic inputs = 0 V, VDD = +4.5 V to +5.5 V
2.7
2
5
µA
Logic inputs = 0 V, VDD = +2.7 V to +3.6 V
1
2.5
µA
Logic inputs = 0 V
0.0275
mW
∆VDD = ±5%
0.006
%
RANGE
PDISS
Power supply sensitivity
PSS
AC CHARACTERISTICS (5)
To ±0.1% of full-scale,
Data = 0000h to 3FFFh to 0000h
0.3
To ±0.006% of full-scale,
Data = 0000h to 3FFFh to 0000h
0.5
BW –3 dB
VREFX = 100 mVRMS, Data = 3FFFh, CFB = 3 pF
10
MHz
Q
VREFX = 10 V, Data = 1FFFh to 2000h to 1FFFh
5
nV/s
Feedthrough error
VOUTX/VREFX
Data = 0000h, VREFX = 100 mVRMS, f = 100 kHz
–70
Crosstalk error
VOUTA/VREFB
Data = 0000h, VREFB = 100 mVRMS,
Adjacent channel, f = 100 kHz
–100
Output voltage settling time
ts
Reference multiplying BW
DAC glitch impulse
Digital feedthrough
Q
Total harmonic distortion
THD
Output spot noise voltage
(5)
CS = 1 and fCLK = 1 MHz
µs
dB
dB
1
VREF = 5 VPP, Data = 3FFFh, f = 1 kHz
en
µs
nV/s
–105
f = 1 kHz, BW = 1 Hz
12
dB
nV/√Hz
All ac characteristic tests are performed in a closed-loop system using an THS4011 I-to-V converter amplifier.
PARAMETER MEASUREMENT INFORMATION
SDI
A1
A0
D1
D13 D12 D11 D10
D0
CLK
Input REG. LD
tCSS
CS
tds
tdh
tch
tcl
tcsh
tlds
tLDH
LDAC
tLDAC
Figure 1. DAC8802 Timing Diagram
4
DAC8802
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SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005
PIN CONFIGURATIONS
DAC8802
(TOP VIEW)
RFBA
VREFA
IOUTA
AGNDA
AGNDB
IOUTB
VREFB
RFBB
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK
LDAC
MSB
VDD
DGND
CS
RS
SDI
PIN DESCRIPTION
PIN
NAME
DESCRIPTION
1
RFBA
Establish voltage output for DAC A by connecting to external amplifier output.
2
VREFA
DAC A Reference voltage input terminal. Establishes DAC A full-scale output voltage.
Can be tied to VDD pin.
3
IOUTA
DAC A Current output.
4
AGNDA
DAC A Analog ground.
5
AGNDB
DAC B Analog ground.
6
IOUTB
DAC B Current output.
7
VREFB
DAC B Reference voltage input terminal. Establishes DAC B full-scale output voltage.
Can be tied to VDD pin.
8
RFBB
Establish voltage output for DAC B by connecting to external amplifier output.
9
SDI
Serial data input; data loads directly into the shift register.
10
RS
Reset pin; active low input. Input registers and DAC registers are set to all 0s or midscale.
Register data = 0x0000 when MSB = 0. Register data = 0x2000 when MSB = 1 for
DAC8802.
11
CS
Chip-select; active low input. Disables shift register loading when high. Transfers serial
register data to input register when CS/LDAC goes high. Does not affect LDAC operation.
12
DGND
13
VDD
Positive power-supply input. Specified range of operation is 2.7 V to 5.5 V.
14
MSB
MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system
power-on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB
pin can be permanently tied to ground or VDD.
15
LDAC
Load DAC register strobe; level sensitive active low. Transfers all input register data to
the DAC registers. Asynchronous active low input. See Table 2 for operation.
16
CLK
Digital ground.
Clock input. Positive edge clocks data into shift register.
5
DAC8802
www.ti.com
SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: VDD = +5 V
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
Channel A
LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +25°C
0.8
0.6
0.6
0.4
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-0.8
-1.0
1.0
2048
4096
6144
8192 10240 12288 14336 16383
Code
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 2.
Figure 3.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
TA = -40°C
0.8
TA = -40°C
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
0
-0.2
-0.6
0
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
1.0
2048
4096
6144
8192 10240 12288 14336 16383
Code
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 4.
Figure 5.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
TA = +85°C
0.8
TA = +85°C
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
0.2
-0.4
-1.0
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 6.
6
TA = +25°C
0.8
DNL (LSB)
INL (LSB)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 7.
DAC8802
www.ti.com
SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
Channel B
LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +25°C
0.8
0.6
0.6
0.4
0.4
0.2
0
-0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
0
1.0
2048
4096
6144
8192 10240 12288 14336 16383
Code
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 8.
Figure 9.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
TA = -40°C
0.8
TA = -40°C
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
0.2
-0.4
-1.0
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
1.0
2048
4096
6144
8192 10240 12288 14336 16383
Code
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 10.
Figure 11.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
TA = +85°C
0.8
TA = +85°C
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
TA = +25°C
0.8
DNL (LSB)
INL (LSB)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 12.
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 13.
7
DAC8802
www.ti.com
SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
REFERENCE MULTIPLYING BANDWIDTH
180
6
0
-6
-12
-18
-24
-30
-36
-42
-48
-54
-60
-66
-72
-78
-84
-90
-96
-102
-108
-114
VDD = +5.0V
Attenuation (dB)
140
120
100
80
60
40
VDD = +2.7V
20
0
Output Voltage (50mV/div)
0
8
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10
100
1k
10k
100k
1M
Logic Input Voltage (V)
Bandwidth (Hz)
Figure 14.
Figure 15.
DAC GLITCH
DAC SETTLING TIME
Code: 1FFFh to 2000h
Output Voltage (5V/div)
Supply Current, IDD (mA)
160
10M
Voltage Output Settling
LDAC Pulse
Trigger Pulse
Time (0.2ms/div)
Time (0.1ms/div)
Figure 16.
Figure 17.
100M
DAC8802
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SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: VDD = +2.7 V
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted.
Channel A
LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +25°C
0.8
0.6
0.6
0.4
0.4
0.2
0
-0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
0
1.0
2048
4096
6144
8192 10240 12288 14336 16383
Code
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 18.
Figure 19.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
TA = -40°C
0.8
TA = -40°C
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
0.2
-0.4
-1.0
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
1.0
2048
4096
6144
8192 10240 12288 14336 16383
Code
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 20.
Figure 21.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
TA = +85°C
0.8
TA = +85°C
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
TA = +25°C
0.8
DNL (LSB)
INL (LSB)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 22.
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 23.
9
DAC8802
www.ti.com
SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued)
At TA = +25°C, +VDD = +2.7 V, unless otherwise noted.
Channel B
LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +25°C
0.8
0.6
0.6
0.4
0.4
0.2
0
-0.2
-0.6
-0.6
-0.8
-0.8
-1.0
1.0
2048
4096
6144
8192 10240 12288 14336 16383
Code
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 24.
Figure 25.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
TA = -40°C
0.8
TA = -40°C
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
0
-0.2
-0.4
0
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
1.0
2048
4096
6144
8192 10240 12288 14336 16383
Code
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 26.
Figure 27.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
TA = +85°C
0.8
TA = +85°C
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
0.2
-0.4
-1.0
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 28.
10
TA = +25°C
0.8
DNL (LSB)
INL (LSB)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
0
2048
4096
6144
8192 10240 12288 14336 16383
Code
Figure 29.
DAC8802
www.ti.com
SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005
THEORY OF OPERATION
CIRCUIT OPERATION
The DAC8802 contains two 14-bit, current-output, digital-to-analog converters (DACs). Each DAC has its own
independent multiplying reference input. The DAC8802 uses a 3-wire, SPI-compatible serial data interface, with a
configurable asynchronous RS pin for half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In addition, an LDAC
strobe enables two-channel simultaneous updates for hardware-synchronized output voltage changes.
Digital-to-Analog Converters
The DAC8802 contains two current-steering R-2R ladder DACs. Figure 30 shows a typical equivalent DAC. Each
DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The RFBX pin is
connected to the output of the external amplifier. The IOUTX terminal is connected to the inverting input of the
external amplifier. The AGNDX pin should be Kelvin-connected to the load point in the circuit requiring the full
14-bit accuracy.
VDD
R
R
R
VREFX
RFBX
2R
2R
2R
R
5 kΩ
S2
S1
IOUTX
AGNDX
DGND
Digital interface connections are omitted for clarity.
Switches S1 and S2 are closed; VDD must be powered.
Figure 30. Typical Equivalent DAC Channel
The DAC is designed to operate with both negative or positive reference voltages. The VDD power pin is only
used by the logic to drive the DAC switches on and off. Note that a matching switch is used in series with the
internal 5 kΩ feedback resistor. If users are attempting to measure the value of RFB, power must be applied to
VDD in order to achieve continuity. The DAC output voltage is determined by VREF and the digital data (D)
according to Equation 1:
V OUT VREF D
16384
(1)
Note that the output polarity is opposite of the VREF polarity for dc reference voltages.
The DAC is also designed to accommodate ac reference input signals. The DAC8802 accommodates input
reference voltages in the range of -15 V to +15 V. The reference voltage inputs exhibit a constant nominal input
resistance of 5 kΩ, ±20%. On the other hand, DAC outputs IOUTA and B are code-dependent and produce
various output resistances and capacitances.
The choice of external amplifier should take into account the variation in impedance generated by the DAC8802
on the amplifiers' inverting input node. The feedback resistance, in parallel with the DAC ladder resistance,
dominates output voltage noise. For multiplying mode applications, an external feedback compensation capacitor
(CFB) may be needed to provide a critically damped output response for step changes in reference input
voltages.
11
DAC8802
www.ti.com
SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005
Figure 15 shows the gain vs frequency performance at various attenuation settings using a 3 pF external
feedback capacitor connected across the IOUTX and RFBX terminals. In order to maintain good analog
performance, power supply bypassing of 0.01 µF, in parallel with 1 µF, is recommended. Under these conditions,
a clean power supply with low ripple voltage capability should be used. Switching power supplies is usually not
suitable for this application due to the higher ripple voltage and PSS frequency-dependent characteristics. It is
best to derive the DAC8802 5-V supply from the system analog supply voltages (do not use the digital 5-V
supply); see Figure 31.
15 V
2R
5V
+
Analog
Power
Supply
R
VDD
R
R
R
RFBX
VREFX
2R
2R
2R
R
5 kΩ
15 V
S2
S1
IOUTX
VCC
VOUT
A1
+
AGNDX
VEE
Load
DGND
DGND
Digital interface connections are omitted for clarity.
Switches S1 and S2 are closed; VDD must be powered.
Figure 31. Recommended Kelvin-Sensed Hookup
VREFA B
CS
EN
VDD
CLK
SDI
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
A0
A1
RFBA
14
Input
Register R
DAC A
Register R
DAC A
AGNDA
RFBB
Input
Register R
DAC A
B
DAC B
Register R
DAC B
Decode
DGND
IOUTB
AGNDB
Set
MSB
Set
MSB
Power-On
Reset
MSB
LDAC
Figure 32. System Level Digital Interfacing
12
IOUTA
RS
DAC8802
www.ti.com
SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005
SERIAL DATA INTERFACE
The DAC8802 uses a 3-wire (CS, SDI, CLK) SPI-compatible serial data interface. Serial data of the DAC8802 is
clocked into the serial input register in an 16-bit data-word format. MSB bits are loaded first. Table 1 defines the
16 data-word bits for the DAC8802.
Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data
setup and data hold time requirements specified in the Interface Timing specifications of the Electrical
Characteristics. Data can only be clocked in while the CS chip select pin is active low. For the DAC8802, only
the last 16 bits clocked into the serial register are interrogated when the CS pin returns to the logic high state.
Since most microcontrollers output serial data in 8-bit bytes, two right-justified data bytes can be written to the
DAC8802. Keeping the CS line low between the first and second byte transfer will result in a successful serial
register update.
Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new
data to the target DAC register, determined by the decoding of address bits A1and A0. For the DAC8802,
Table 1, Table 2, Table 3, and Figure 1 define the characteristics of the software serial interface.
Table 1. Serial Input Register Data Format, Data Loaded MSB First (1)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0 (LSB)
Data
A1
A0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(1)
Only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line positive edge returns to
logic high. At this point an internally-generated load strobe transfers the serial register data contents (bits D13-D0) to the decoded
DAC-input-register address determined by bits A1 and A0. Any extra bits clocked into the DAC8802 shift register are ignored; only the
last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 2. Control Logic Truth Table (1)
CS
CLK
LDAC
RS
MSB
H
X
H
H
X
No effect
Latched
Latched
L
L
H
H
X
No effect
Latched
Latched
L
↑+
H
H
X
Shift register data advanced one bit
Latched
Latched
L
H
H
H
X
No effect
Latched
Latched
↑+
L
H
H
X
No effect
Selected DAC updated with current SR contents
Latched
H
X
L
H
X
No effect
Latched
Transparent
H
X
H
H
X
No effect
Latched
Latched
H
X
↑+
H
X
No effect
Latched
Latched
H
X
H
L
0
No effect
Latched data = 0000h
Latched data = 0000h
H
X
H
L
H
No effect
Latched data = 2000h
Latched data = 2000h
(1)
SERIAL SHIFT REGISTER
INPUT REGISTER
DAC REGISTER
↑+ = Positive logic transition; X = Do not care
Table 3. Address Decode
A1
A0
0
0
DAC DECODE
None
0
1
DAC A
1
0
DAC B
1
1
DAC A and DAC B
13
DAC8802
www.ti.com
SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005
Figure 33 shows the equivalent logic interface for the key digital control pins for the DAC8802.
To Input Register
Address
Decoder
CS
A
B
EN
Shift Register
CLK
SDI
Figure 33. DAC8802 Equivalent Logic Interface
Two additional pins RS and MSB provide hardware control over the preset function and DAC register loading. If
these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all
input and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1).
POWER ON RESET
When the VDD power supply is turned on, an internal reset strobe forces all the Input and DAC registers to the
zero-code state or half-scale, depending on the MSB pin voltage. The VDD power supply should have a smooth
positive ramp without drooping, in order to have consistent results, especially in the region of VDD = 1.5 V to
2.3 V. The DAC register data stays at the zero or half-scale setting until a valid serial register data load takes
place.
ESD Protection Circuits
All logic-input pins contain back-biased ESD protection zener diodes connected to ground (DGND) and VDD, as
shown in Figure 34.
VDD
DIGITAL
INPUTS
250 W
DGND
Figure 34. Equivalent ESD Protection Circuits
PCB LAYOUT
The DAC8802 is a high-accuracy DAC that can have its performance compromised by grounding and printed
circuit board (PCB) lead trace resistance. The 14-bit DAC8802 with a 10-V full-scale range has an LSB value of
610 µV. The ladder and associated reference and analog ground currents for a given channel can be as high as
2 mA. With this 2 mA current level, a series wiring and connector resistance of only 305 mΩ will cause 1 LSB of
voltage drop. The preferred PCB layout for the DAC8802 is to have all AGNDX pins connected directly to an
analog ground plane at the unit. The noninverting input of each channel I/V converter should also either connect
directly to the analog ground plane or have an individual sense trace back to the AGNDX pin connection. The
feedback resistor trace to the I/V converter should also be kept short and low resistance to prevent IR drops from
contributing to gain error. This attention to wiring ensures the optimal performance of the DAC8802.
14
DAC8802
www.ti.com
SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005
APPLICATION INFORMATION
The DAC8802, a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output IOUT is the inverse of the input reference voltage at VREF.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing, as shown in Figure 35.
An additional external op amp (A2) is added as a summing amp. In this circuit, the first and second amps (A1
and A2) provide a gain of 2X that widens the output span to 20 V. A 4-quadrant multiplying circuit is implemented
by using a 10-V offset of the reference voltage to bias A2. According to the following circuit transfer equation
(Equation 2), input data (D) from code 0 to full scale produces output voltages of VOUT = -10 V to VOUT = 10 V.
V OUT D 1 V
8192
REF
(2)
10 kΩ
10 kΩ
10 V
5 kΩ
VOUT
OPA277
VREF
- 10 V < VOUT < +10V
VDD
VREFX
One Channel
DAC8802
R FBX
IOUTX
OPA277
AGNDX
Digital interface connections omitted for clarity.
Figure 35. Four-Quadrant Multiplying Application Circuit
Cross-Reference
The DAC8802 has an industry-standard pinout. Table 4 provides the cross-reference information.
Table 4. Cross-Reference
PRODUCT
INL
(LSB)
DNL
(LSB)
SPECIFIED
TEMPERATURE
RANGE
DAC8802IPW
±1
±1
-40°C to +85°C
PACKAGE
DESCRIPTION
PACKAGE
OPTION
CROSS-REFERENCE
PART NUMBER
16-Lead Thin Shrink
Small-Outline Package
TSSOP-16
AD5555CRU
15
PACKAGE OPTION ADDENDUM
www.ti.com
6-Oct-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DAC8802IPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DAC8802IPWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DAC8802IPWR
ACTIVE
TSSOP
PW
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DAC8802IPWRG4
ACTIVE
TSSOP
PW
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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