Power Supply IC Series for TFT-LCD Panels High-precision Gamma Correction ICs with built-in DAC BD8132FV, BD8139AEFV No.09035EBT02 ●Description These gamma correction voltage generation ICs feature built-in DACs and provide a single-chip solution with setting control via serial communications, a high-precision 10-bit DAC, an output amp (18-channel or 10-channel), and Vcom. ●Features 1) Single-chip design means fewer components 2) Built-in 10 bit DAC (18ch: BD8132FV, 10ch: BD8139AEFV) 3) Built-in DAC output amp 4) Built-in Vcom amp 5) Built-in auto-read function 6) 3-line serial interface (BD8132FV) or 2-wire serial (BD8139AEFV) 7) Thermal shutdown circuit 8) SSOP-B40 package (BD8132FV) / HTSSOP-B40 package (BD8139AEFV) ●Applications These ICs can be used with TFT LCD panels used by large-screen and high-definition LCD TVs. ●Absolute maximum ratings (Ta = 25°C) Parameter Power supply voltage 1 Power supply voltage 2 REFIN voltage Amp output current capacity Junction temperature BD8132FV Power dissipation BD8139AEFV Operating temperature range Storage temperature range Symbol DVcc Vcc REF Io Tjmax Limit 7 20 20 50*1 150 1125*2 1600*3 -30 to +85 -55 to +150 Pd Topr Tstg Unit V V V mA ℃ mW ℃ ℃ *1 Must not exceed Pd. *2 Reduced by 9.0 mW/°C over 25°C, when mounted on a glass epoxy board (70 mm 70 mm 1.6 mm). *3 Reduced by 12.8 mW/°C over 25°C, when mounted on a glass epoxy board (70 mm 70 mm 1.6 mm). ●Recommended Operating Ranges Parameter Power supply voltage 1 Power supply voltage 2 REFIN voltage Amp output current capacity Serial clock frequency (BD8132FV) 2 wire serial frequency (BD8139AEFV) OSC frequency (BD8132FV) OSC frequency (BD8139AEFV) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Symbol DVcc Vcc REF Io fCLK fCLK fosc fosc 1/20 Limit Min. 2.3 6 6 — — — 10 — Max. 4.0 18 18 40 5 400 200 400 Unit V V V mA MHZ kHz kHz kHz 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●Electrical Characteristics BD8132FV(Unless otherwise specified, Vcc = 15 V, DVcc = 3.3 V, Ta = 25℃) Limit Parameter Symbol Unit Min. Typ. Max. Condition [REFIN] Sinking current Iref 25 50 75 µA REF = 10 V Output current capacity Io 150 Load stability ∆V — 300 — mA DAC = 3V, OUTx = 0 V 5 20 mV Io = +10 mA to -10 mA, OUTx = 6 V Slew rate SR — 3.5 — [Gamma correction amp block] VCC-0.16 VCC-0.1 V/µS Ro = 100 k, Co = 100 pF * OUT max. output voltage VOH — V Io = -5 mA OUT min. output voltage VOL — 0.15 0.24 V Io = 5 mA Input bias current Ib — 0 1 µA VFB = 6 V Output current capacity Io 150 300 — mA DAC = 3V, OUTx = 0 V mV Io = +10 mA to -10 mA, OUTx = 3 V [Common amp block] Load stability ∆V — 5 20 Slew rate SR — 3.5 — 0 — VDAC V Ro = 100 k, Co = 100 pF * — V Io = -5 mA Io = 5 mA V/µS Ro = 100 k, Co = 100 pF * Input voltage range VFB OUT max. output voltage VOH OUT min. output voltage VOL — 0.15 0.24 V Res — 10 — Bit VCC-0.16 VCC-0.1 [DAC] Resolution Nonlinearity error Differential linearity error LE -2 — 2 LSB Ideal line error: 00A to 3F5 DLE -2 — 2 LSB 1 LSB ideal increase error: 00A to 3F5 fosc — 80 — kHz [OSC] Oscillating frequency Internal frequency mode [Control signals] Sinking current Ictl — 16 25 µA Threshold voltage VTH 0.7 — 2.6 V DVCC = 3.3 V Reset time trst — 45 — µs CCT = 1000 pF Icc — 20 — mA When all output voltages are set to 5 V. [Overall] Total supply current www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/20 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●Electrical Characteristics BD8139AEFV (Unless otherwise specified, Vcc = 15 V, DVcc = 3.3 V, Ta = 25℃) Limit Parameter Symbol Unit Min. Typ. Max. Condition [REFIN] Sinking current Iref 25 50 75 µA REF = 10V Output current capacity Io 150 Load stability ∆V — 300 — mA DAC = 3 V, OUTx = 0 V 5 20 mV Io = +10 mA to -10 mA, OUTx = 6 V Slew rate SR — 3.5 — V/µs Ro = 100 k, Co = 100 pF * [Gamma correction amp block] OUT max. output voltage VOH — V Io = -5 mA OUT min. output voltage VOL Vcc-0.16 Vcc-0.1 — 0.1 0.16 V Io = 5 mA Input bias current Ib — 0 1 µA VFB = 6 V Output current capacity Io 150 300 — mA DAC = 3 V, OUTx = 0 V Load stability ∆V — 5 20 mV Io = +10 mA to -10 mA, OUTx = 3 V Slew rate SR — 3.5 — 0 — VDAC V Ro = 100 k, Co = 100 pF * — V Io = -5 mA Io = 5 mA [Common amp block] V/µS Ro = 100 k, Co = 100 pF * Input voltage range VFB OUT max. output voltage VOH OUT min. output voltage VOL — 0.1 0.16 V Res — 10 — Bit Vcc-0.16 Vcc-0.1 [DAC] Resolution Nonlinearity error Differential linearity error LE -2 — 2 LSB Ideal line error: 00A to 3F5 DLE -2 — 2 LSB 1 LSB ideal increase error: 00A to 3F5 fosc — 210 — kHz Internal frequency mode [OSC] Oscillating frequency [Control signals] Sinking current Ictl — 16 25 µA Except for osc_mode Sinking current Ioscm 26 33 40 µA Only osc_mode Min. output voltage VSDA — — 0.4 V ISDA = 3.0 mA * Sinking current ILi -10 — 10 µA 0.4 V to 0.9 V DVCC Threshold voltage VTH 0.7 — 2.6 V DVCC = 3.3 V Reset time trst — 45 — µs CCT = 1000 pF Icc — 18 — mA When all output voltages are set to 5 V. [Overall] Total supply current www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/20 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●Reference Data (Unless otherwise specified, Ta = 25℃, BD8132FV and BD8139AEFV) 40 BD8132FV 35 30 -30℃ 25 25℃ 85℃ 20 15 10 5 5 10 15 BD8132FV 30 20 1 15 10 0 -30 SUPPLY VOLTAGE : VCC[V] Fig. 1 VCC Total Supply Current 10 30 50 70 0 -30℃ 15 10 5 10 15 15 18V 6V 15V 10 5 0 -30 10 30 50 Fig. 5 Total Supply Current vs Temperature 5 10 15 -30℃ 1 0.5 1 2 3 4 5 6 12 1 85℃ 25℃ -30℃ 0.5 0 5 10 15 20 10 8 85℃ 6 4 25℃ 2 -30℃ 0 -400 -300 -200 -100 0 100 SOURCE CURRENT : IF[mA] SINK CURRENT : IF[mA] OUTPUT CURRENT : IAMP[mA] Fig. 7 High Output Voltage Fig. 8 Low Output Voltage Fig. 9 Output Current Capacity www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 7 Fig. 6 VDD Total Supply Current OUTPUT VOLTAGE : VO[V] OUTPUT VOLTAGE : VO[V] 20 25℃ 14 0 0 85℃ SUPPLY VOLTAGE : DVCC[V] 1.5 15.5 14 7 BD8139AEFV 0 Fig. 4 VCC Total Supply Current 14.5 6 1.5 70 AMBIENT TEMPERATURE : Ta [℃] 15 5 0 -10 SUPPLY VOLTAGE : VCC[V] 25℃ 85℃ 4 2 BD8139AEFV 20 -30℃ 3 Fig. 3 VDD Total Supply Current 0 5 2 Fig. 2 Total Supply Current vs Temperature SUPPLY CURRENT : IDD[mA].. 25℃ 85℃ 1 SUPPLY VOLTAGE : VDD[V] SUPPLY CURRENT : ICC[mA] . SUPPLY CURRENT : ICC[mA] . 20 0 OUTPUT VOLTAGE : VO[V] 0 -10 20 25 - 25℃ AMBIENT TEMPERATURE : Ta[℃] 30 BD8139AEFV 85℃ 0.5 5 20 BD8132FV 1.5 6V 15V 18V 25 0 0 2 35 SUPPLY CURRENT : IDD[mA] . SUPPLY CURRENT : ICC[mA] , SUPPLY CURRENT : ICC[mA] , 40 4/20 200 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●Reference Data (Unless otherwise specified, Ta = 25℃, BD8132FV and BD8139AEFV) 80 100 1000 100 100 80 Phase Phase [deg] Gain [dB] 40 20 40 0 -20 Gain -40 20 -60 Reset Time [ms] . 60 60 Reset Time [uS] 80 10 1 0.1 60 40 20 -80 0.001 1 2 10 VCC=15V VI=40mV RL=100kΩ CL=100pF TA=25℃ 8 6 4 2 2.55 2.50 2.45 Output Voltage [V] 0 5.10 5.05 5.00 4.95 4.90 0 5 10 15 20 25 30 35 40 0 45 50 5 10 TIME [usec] 15 20 25 30 35 40 0 20 40 60 80 100 Fig. 12 Power-on Reset Time vs Temperature Output Voltage [V] 4 Input Voltage [V] 6 -20 AMBIENT TEMPERATURE : Ta[ ℃] Fig. 11 Power-on Reset Time VCC=15V VI=4V RL=100kΩ CL=100pF TA=25℃ 0 0 -40 10 VCC=15V VI=5V CS=100pF RS=100Ω CL=100pF RL=1kΩ tT=0.1us TA=25℃ 45 50 +20mA -20mA -20 Fig. 10 Open Loop Waveform Output Voltage [V] 0.1 CT CAPACITOR : CT[μF] FREQUENCY : f [Hz] 10.2 10.1 9.9 9.8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 TIME [usec] TIME [usec] Fig. 15 Load Response Waveform (Small Signal) (RL = 1 k Pull-up) 10.1 9.9 9.8 2 2 1.5 1.5 1 1 0.5 0.5 DNL [LSB] 20 0 -20 10.2 INL [LSB] Fig. 14 Slew Rate Waveform (High-Amplitude) Input Current [mA] Fig. 13 Slew Rate Waveform VCC=15V VI=5V CS=100pF RS=100Ω CL=100pF RL=1kΩ tT=0.1us TA=25℃ Output Voltage [V] 0.01 20 1M 10M Input Voltage [V] 10K 100K 1 0 0.01 0.0001 -100 100 0 -0.5 TIME [usec] Fig. 16 Load Response Waveform (RL = 1 k Pull-down) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. -0.5 -1 -1 -1.5 -1.5 -2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0 200 400 600 800 step Fig. 17 Integral Linearity Error 5/20 1000 -2 0 200 400 600 800 1000 step Fig. 18 Differential Linearity Error 2009.07 - Rev.B Input Current [mA] 0 Technical Note BD8132FV, BD8139AEFV ●Pin Assignment Diagram [BD8132FV] ●Block Diagram REFIN 15 VDAC VCC 16 13 VCC DVCC 100kΩ VDAC V0 LATCH SDIN VREF V1 SDOUT V3 GND V4 R/W V5 DVCC 11 V6 MEMDO V7 MENDO MEMDI V8 OSC DVCC V9 LATCH VA CLK NC VB VCC VD REFIN VE VDAC VF CT VG DGND VH GND Vcom GND FB 40 V0 Register 1 ×2 39 V1 ×2 ×2 38 V2 ×2 37 V3 ×2 36 V4 ×2 35 V5 V6 V7 Register 2 CS VCC ×2 VDAC DVCC CS R/W MENDI VC VCC Register 0 TSD V2 CLK 100kΩ 7 8 6 9 Register 3 Register 4 AUTO Read 1 Serial 3 SDIN 2 SDOUT 4 I/F Register 5 DAC LOGIC Register 6 ×2 34 Register 7 ×2 33 Register 8 ×2 32 V8 Register 9 ×2 ×2 31 V9 30 VA Register A VDAC ×2 Register B ×2 29 VB Register C CT 17 Power On Reset Register D ×2 DAC LOGIC Register E 28 VC VD ×2 27 ×2 26 VE ×2 25 VF 24 VG Register F DGND18 Register G DGND ×2 Register H OSC ×2 Register I GND 5 10 VH 22 Vcom 21 OSC GND 23 FB Fig. 19 Pin Assignment Diagram & Block Diagram ●Pin Name and Function Pin Pin No. name Function Pin No. Pin name Function 1 LATCH Serial latch input 21 FB Vcom amp negative feedback input 2 SDIN Serial data input 22 Vcom 3 CLK Serial clock input 23 VH Gamma correction output pin 4 SDOUT Serial data output 24 VG Gamma correction output pin 5 GND GND input 25 VF Gamma correction output pin 6 R/W Auto-read on/off input (On = Low, Off = High) 26 VE Gamma correction output pin Vcom output pin 7 CS External memory selection output 27 VD Gamma correction output pin 8 MEMDO External memory output data signal 28 VC Gamma correction output pin 9 MEMDI External memory input data signal 29 VB Gamma correction output pin 10 OSC Tuning clock I/O 30 VA Gamma correction output pin 11 DVCC Logic power supply input 31 V9 Gamma correction output pin 12 NC — 32 V8 Gamma correction output pin 13 VCC Buffer amp power supply input 33 V7 Gamma correction output pin 14 VCC Buffer amp power supply input 34 V6 Gamma correction output pin 15 REFIN DAC reference input 35 V5 Gamma correction output pin 16 VDAC DAC voltage output 36 V4 Gamma correction output pin 17 CT 18 DGND Power-on reset capacitance connection pin 37 V3 Gamma correction output pin DAC GND input 38 V2 Gamma correction output pin 19 GND GND input 39 V1 Gamma correction output pin 20 GND GND input 40 V0 Gamma correction output pin www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 6/20 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●Pin Assignment Diagram [BD8139AEFV] ●Block Diagram REFIN VDAC 16 A1 A2 GND NC NC OSC NC SLAVE/AR V0 OSC_MODE V1 SDA V2 SCL V3 DGND V4 V5 NC V6 NC V7 CT V8 NC DVcc 100kΩ VREF TSD DVcc 14 A1 1 A2 2 SCL SDA SLAVE/AR REFIN NC NC NC Vcc VDAC NC NC NC VCC Register 0 ×2 36 V0 Register 1 ×2 35 V1 ×2 ×2 34 V2 ×2 33 V3 ×2 32 V4 ×2 31 V5 ×2 30 V6 ×2 29 ×2 28 V8 ×2 ×2 27 V9 26 Vcom 25 FB VDAC Register 2 DVcc Register 3 DAC Register 4 LOGIC Register 5 2wire serial I/F 8 7 Register 6 5 Register 7 Register 8 VCOM FB Vcc VDAC V9 DVcc 23 100kΩ NC DACGND Vcc 19 CT 13 DGND 9 DACGND 10 Power On Reset Register 9 Register A V7 OSC DGND DACGND GND 6 40 GND OSC_MODE 4 OSC Fig. 20 Pin Assignment Diagram & Block Diagram ●Pin Name and Function Pin Pin Function No. name Slave/address setting pin 1 A1 Auto-read/word address setting pin (1) Slave/address setting pin 2 A2 Auto-read/word address setting pin (2) 3 NC 4 OSC 5 6 SLAVE/AR — Tuning clock I/O Slave/auto-read selection pin OSC_MODE OSC switching pin Pin No. Pin name Function 21 NC — 22 NC — 23 VCC 24 NC 25 FB 26 Vcom Buffer amp power supply input — Vcom amp negative feedback input Vcom output pin 7 SDA Serial data input (2 wire serial) 27 V9 Gamma correction output pin 9 8 SCL Serial clock input (2 wire serial) 28 V8 Gamma correction output pin 8 9 DGND GND input 29 V7 Gamma correction output pin 7 10 DACGND 11 NC 12 13 14 DVCC 30 V6 Gamma correction output pin 6 — 31 V5 Gamma correction output pin 5 NC — 32 V4 Gamma correction output pin 4 CT Power-on reset capacitance connection pin 33 V3 Gamma correction output pin 3 Logic power supply input 34 V2 Gamma correction output pin 2 15 NC 16 REFIN 17 NC 18 NC 19 VDAC 20 NC DAC GND input — 35 V1 Gamma correction output pin 1 36 V0 Gamma correction output pin 0 — 37 NC — — 38 NC — 39 NC — 40 GND DAC reference input DAC voltage output www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. — 7/20 GND input 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●Block Operation ・VDAC Amp The VDAC Amp amplifies the voltage applied to REFIN by 0.5x and outputs it to the VDAC pin. Connect a 1 µF phase compensation capacitor to the VDAC pin. ・DAC LOGIC The DAC LOGIC converts the 10-bit digital signal read to the register to a voltage. ・Amp The Amp amplifies the voltage output from the DAC LOGIC by 2x. Input includes a sample and hold function and is refreshed by the OSC. ・OSC The OSC generates the frequency that determines the Amp's refresh time. External input can be selected using serial input. (For the BD8139AEFV, external input is selected using the external pin.) ・Power On Reset When the digital power supply DVCC is activated, each IC generates a reset signal to initialize the serial interface, auto-read functionality, and registers. Adding a 1,000 pF capacitor to the CT pin ensures that reset operation can be performed reliably, without regard to the speed with which the power supply starts up. ・TSD (Thermal Shut Down) The TSD circuit turns output off when the chip temperature reaches or exceeds approximately 175°C in order to prevent thermal destruction or thermal runaway. When the chip returns to a specified temperature, the circuit resets. The TSD circuit is designed only to protect the IC itself. Application thermal design should ensure operation of the IC below the thermal shutdown detection temperature of approximately 175°C. ・Register 2 A serial signal (consisting of 10-bit gamma correction voltage values) input using the serial interface or I C bus interface is held for each register address. Data is initialized by the reset signal generated during a power-on reset. ・Serial I/F(BD8132FV) The serial interface uses a 3-line serial data format (LATCH, CLK, SDIN). It is used to set gamma correction voltages, specify register addresses, and select OSC I/O. ・2 wire serial I/F(BD8139AEFV) The serial interface uses a 2-line serial data format (SCL, SDA). It is used to set gamma correction voltages and specify register addresses. ・Autoread The BD8132FV uses the R/W, CLK, CS, and MEMDO pins to enable automatic reading of the IC's 1 kbit microwire type external memory. The BD8139AEFV uses the SCL and SDA pins to enable automatic reading of the 2 wire serial bus format external memory. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/20 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV [BD8132FV] ●Serial communications The serial data control block consists of a register that stores data from the LATCH, CLK, and SDIN pins, and a DAC circuit that receives the output from this register and provides adjusted voltages to other IC blocks. When the IC's power supply is activated, the reset function operates to set the register to a preset value. The first bit is for testing use only and should always be set to 0. The next bit is used to select the OSC mode. Inputting a value of 0 selects internal frequency mode and uses a frequency of 80 kHz. Entering a value of 1 selects external frequency mode. Input an external clock signal from the OSC pin. Serial data control block diagram Clock control 10 bits 5 bits Address decoder OUT0 to OUTI registers d0 d1 d2 d3 d4 d5 d6 d7 d10 d9 d11 d12 d13 d14 d15 Shift register d16 CLK SDIN d8 LATCH 1 bit OSC mode 1 bit Test mode DAC Fig. 21 Serial Block Diagram (1) Serial communications timing The 17-bit serial data input from the SDIN pin is read into the shift register using the rising edge of the signal input to the CLK pin. This data is then loaded to the DAC register using the rising edge of the signal input to the LATCH pin. If the data loaded into the shift register while the LATCH pin is low consists of less than 17 bits, the loaded data is discarded. If the data exceeds 17 bits, the last 17 bits to be loaded are treated as valid. Serial communications timing LATCH CLK d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 SDIN Fig. 22 Serial Communications Timing Chart (2) Serial data The following table illustrates the format of serial data input to the SDIN pin. First → d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 0 X Register address Register Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Register 8 Register 9 Register A Register B Register C Register D Register E Register F Register G Register H Register I d2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 d3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Address d4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 d5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 d6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 d11 d12 Data Behavior when data increases V0 voltage value increases V1 voltage value increases V2 voltage value increases V3 voltage value increases V4 voltage value increases V5 voltage value increases V6 voltage value increases V7 voltage value increases V8 voltage value increases V9 voltage value increases VA voltage value increases VB voltage value increases VC voltage value increases VD voltage value increases VE voltage value increases VF voltage value increases VG voltage value increases VH voltage value increases Vcom voltage value increases 9/20 d13 d14 →Last d15 d16 Preset value d7 to d16 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●Auto-read function The auto-read function enables the IC's 1 kbit microwire type external memory to be automatically read. This block operates in synchronization with the external input CLK's falling edge to output the external memory chip select signal CS as well as the memory read data signal MEMDO. The read data signal consists of a start bit for the external memory, a read code, and a read address. When this signal is sent to the external memory, the memory outputs the data corresponding to the indicated address. Data output from the memory is read from the MEMDI pin, and this block automatically generates the serial DATA and LATCH signals and writes the memory data to the register. Memory reads are synchronized to the CLK's falling edge. Read addresses start from address 00H and repeat until address 12H, so data must be stored from address 00H to address 12H. The auto-read function is controlled using the R/W signal. Read access to the external memory is performed continuously while the R/W signal is low. To access the external memory from another device, the R/W signal must be set to high. When the R/W signal is set to high, the CS and MEMDO pins enter a high-impedance state. Auto-read timing R/W CLK High-impedance CS Address 00H MEMDO Address 01H High-impedance Start bit and read code MEMDI Memory data INTERNAL DATA D15 to D0 D15 to D0 INTERNAL LATCH Fig. 23 Auto-read Timing Chart External m emory data format MSB LSB D15 d1 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 OSC R egister address mode DAC data Fig. 24 External Memory Data Table ●Serial communications timing chart ●Auto-read timing chart tRW LATCH R/W tWL CLK tWH tCL tLA tCR tRC C tLC tCDO MEMDO tCCS tSC CS tDIC SDIN MEMDI Fig.25 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Fig.26 10/20 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●Timing standard values Parameter Latch setup time SDIN setup time RW setup time MEMDI setup time Clock high time Clock low time Latch hold time RW hold time LATCH high time RW high time MEMDO delay time CS delay time Symbol Limit Typ. — — — — — — — — — — — — Min. 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.6 0.6 — — tLC tSC tRC tDIC tWH tWL tCL tCR tLA tRW tCDO tCCS Unit Max. — — — — — — — — — — 0.1 0.1 µs µs µs µs µs µs µs µs µs µs µs µs ●Gamma correction output setting (BD8132FV and BD8139AEFV) Equation (1) describes the relationship between the gamma correction output voltage (V0 to VH) and the DAC setting. Output voltage (V0 to VH) = [(DAC setting + 1) / 1,024] (REFIN / 2) 2 (1) The Vcom voltage can be set by attaching resistor R1 between the Vcom and FB pins and resistor R2 between the FB and GND pins.Equation (2) describes the relationship between the Vcom voltage and the DAC setting when using these resistors. Output voltage (Vcom) = [(DAC setting + 1) / 1,024] (REFIN / 2) (R1 + R2) / R2 (2) DAC Vcom R1 FB R2 Fig. 27 Vcom Voltage Setting Circuit Diagram ●Power supply sequence Activate the digital power supply DVCC before the VCC power supply to prevent IC malfunctions due to undefined logic in the digital circuit. Input serial data after canceling the power-on reset. When turning off the IC's power supplies, turn off VCC and then DVCC. ・・・ VCC ・・・ tVcc tVD ・・・ REFIN ・・・ tVR ・・・ DVCC ・・・ ・・・ LATCH tRV ・・・ tSV tDS CLK ・・・ ・・・ SDIN ・・・ ・・・ Fig. 28 Power Supply Sequence Diagram ●Power supply sequence standard values Parameter Serial input timing VCC activation timing REFIN activation timing REFIN off timing Power supply off timing VCC startup timing Symbol tDS tSV tVR tRV tVD tVCC www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Min. 100 0 0 0 0 1 Limit Typ. — 10 10 10 10 — 11/20 Max. — — — — — — Unit Condition µs µs µs µs µs ms Cct = 1000 pF 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV [BD8139AEFV] ●Serial communications The 2 wire serial control block consists of a register that stores data from the SCL and SDA pins and a DAC circuit that receives the output from this register and provides adjusted voltages to other IC blocks. When the IC's power supply is activated, the reset function operates to set the register to a preset value. SCL EEPROM Auto-read SDA Word address setting A1 A2 + CT Acknowledge V0 to VA registers DAC Shift register Parity check STAN/INC Fig. 29 2 wire serial Control Block Diagram (1) 2 wire serial timing chart Slave mode (SLAVE/AR = low; supports write mode only; A0 = low) Fig. 30 2 wire serial Timing Chart (Slave) Of device addresses A7 to A0, A7 to A3 and A0 are specific to the gamma correction voltage generation IC and should be set as follows: (A7 to A0) = 11101(A2)(A1)0. A1 and A2 can be set externally. Because these signals are pulled down internally, they are set to 0 when in the open state. When setting them to 1, connect them to the DVcc power supply. For this reason, A1 and A2 can be used to create 4 setting combinations. When using only slave mode, a maximum of 4 BD8139AEFV ICs can be connected to the 2 wire serial line. The lower 4 bits of the second byte are used to store the register address. The following table describes the correspondence between register addresses and amp output. The third and fourth bytes are used to store the gamma correction voltage setting. The LSB acts as a parity check bit. The method for setting the LSB is described below. Register name Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Register 8 Register 9 Register A Register 0-A W3 0 0 0 0 0 0 0 0 1 1 1 1 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Address W2 W1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 W0 0 1 0 1 0 1 0 1 0 1 0 1 Behavior when data increases V0 voltage value increases V1 voltage value increases V2 voltage value increases V3 voltage value increases V4 voltage value increases V5 voltage value increases V6 voltage value increases V7 voltage value increases V8 voltage value increases V9 voltage value increases Vcom voltage value increases V0-Vcom voltage value increases 12/20 Preset value Data (9:0) 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●SDA serial data map SLAVE mode(SLAVE/AR=L) First (MSB) Last (LSB) bit Byte 7 6 5 4 3 2 1 1 Device address (11101<A2><A1>) 2 Don’t Care Register address 3 data(9:3) 4 data(2:0) Don’t Care It needs 4 byte for slave mode. When register address “1111”, it is updated same data on all addresses. 0 0 PC PC Auto-read mode (SLAVE/AR = high) 2 The auto-read function enables automatic reading of the I C bus interface's 1 kbit built-in memory. When the reset signal is cleared, automatic reads from EEPROM begin. In auto-read mode, A1 and A2 serve as the EEPROM word address setting pins. When A1 and A2 are both set to low, read access is available for word addresses 0 through 21. A2 L H L H A1 L L H H Read start word address 0 (00h) 32 (20h) 64 (40h) 96 (60h) Read end word address 21 (h) 53 (35h) 85 (55h) 117 (75h) The following table describes the 22-word data format read from the EEPROM. Word 7 6 5 4 3 2 1 0 Output 1 Data (9:3) PC V0 2 Data (2:0) Don’t Care PC 3 Data (9:3) PC V1 4 Data (2:0) Don’t Care PC ⋮ ⋮ 21 Data (9:3) PC Vcom 22 Data (2:0) Don’t Care PC The first and second words are used for the V0 setting, while the third and fourth words are used for the V1 setting. Including the Vcom setting, a total of 22 words of data are read. The LSB for all words contains an even parity check (PC). The LSBs for all EPROM data settings should be set. (Where the number 1 represents an even number.) ＜Example of setting for EEPROM＞ A1=L,A2=L REFIN 15 V data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 EEPROM WORD ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 915 Setting voltage 13.418 V0 1011111010 762 11.177 V1 1010101100 684 10.034 V2 0111100001 481 7.061 V3 1000111110 574 8.423 V4 1000000000 512 7.515 V5 0101010111 343 5.039 V6 0101111111 383 5.625 V7 0100101010 298 4.380 V8 0001111010 122 1.802 V9 1111111111 1023 7.500 VCOM R1=R2 BD8139AEFV d7 d6 d5 d4 d3 d2 d1 d0 bin dec V0① V0② V1① V1② V2① V2② V3① V3② V4① V4② V5① V5② V6① V6② V7① V7② V8① V8② V9① V9② VCOM① VCOM② 1 0 1 0 1 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 1 0 1 1 1 1110010011 ※Must set “1” at d7 of 16ch. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 13/20 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●Timing Chart Fig. 31 2-wire serial Timing Chart (Auto-Read) Only the EEPROM device address A3 = A2 = A1 = low is supported. The auto-read function specifies the read start word address in EEPROM write mode. Then after resending the start signal, the data is read in read mode. When the parity check detects an error, a stop signal is sent and the auto-read function is repeated until no error is detected.If the auto-read function never completes, the EEPROM data settings should be reviewed. ・When operating in auto-read mode, a maximum of 2 BD8139AEFV ICs (A and B) can be connected to the I2C bus line. When using 2 ICs, change the CT pin capacitance value to avoid auto-read timing collisions. The following figure illustrates auto-read timing when using 2 ICs. DVCC CT(A) CT(B) Autoread(A) Error(A) Autoread(B) Error(B) Fig 32 Auto-Read Timing Chart Set the CT pin capacitance as follows: Using an inappropriate capacitance setting may result in auto-read timing collisions, making it impossible to read data properly. BD8139AEFV A CT = 1000 pF Scatter: Within 5% BD8139AEFV B CT = 3300 pF ●2 wire serial bus data timing Scatter: Within 5% tR tF tHIGH SCL tHD:STA tSU:DAT tLOW tHD:DAT SDA (IN) tBUF tPD tDH SDA (OUT) SCL tSU:STA tHD:STA tI tSU:STO SDA START BIT * SDA latches at the SCL rising edge. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. STOP BIT Fig 33 14/20 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●Timing standard values Parameter FAST-MODE 2.3 V ≤ DVCC ≤ 4.0 V Min. Typ. Max. Symbol Unit SCL frequency fSCL — — 400 kHz SCL high time tHIGH 0.6 — — µs SCL low time tLOW 1.2 — — µs tR — — 0.3 µs Rise Time Fall Time Start condition hold time tF — — 0.3 µs tHD:STA 0.6 — — µs Start condition setup time tSU:STA 0.6 — — µs SDA hold time tHD:DAT 100 — — ns SDA setup time tSU:DAT 100 — — ns Acknowledge delay time tPD 0.1 — 0.9 µs Acknowledge hold time tDH 0.1 — — µs tSU:STO 0.6 — — µs tBUF 1.2 — — µs Stop condition setup time Bus release time ●Power supply sequence Activate the digital power supply DVCC before the VCC power supply to prevent IC malfunctions due to undefined logic in the digital circuit. Input serial data after canceling the power-on reset. When turning off the IC's power supplies, turn off VCC and then DVCC. ・・・ VCC ・・・ tVcc tVD ・・・ REFIN ・・・ tVR ・・・ DVCC tDS SCL ・・・ SDA ・・・ tRV ・・・ tSV ・・・ ・・・ Fig. 34 Power Supply Sequence Diagram ●Power supply sequence standard values Parameter Symbol Serial input timing tDS Limit Min. Typ. Max. 100 — — Unit µs VCC activation timing tSV 0 10 — µs REFIN activation timing tVR 0 10 — µs REFIN off timing tRV 0 10 — µs Power supply off timing tVD 0 10 — µs VCC startup timing tVCC 1 — — ms www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 15/20 Condition Cct = 1000 pF 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●Closing time for auto-read (Input VCC ～ Beginning auto-read ～ Taking time for auto-read, when 2use.) 0.9DVcc DVcc Vcc Auto-read for one AR1 Auto-read for other AR2 Vout 0.9Vout （First gamma output） Vout 0.9Vout （Final gamma output） t5 t1 t2 t3 t2 t4 Fig. 35 Time from input VCC until final gamma output t total1 = t1 + t2 x 2 + t3 + t4 min. typ. max t1 108 169 240 t2 730 1160 1660 t3 156 248 356 t4 - - 145 t total 1724 2737 4061 Unit : µsec Time from input voltage until first gamma output (condition of input VCC already) t total2 = t1 + t5 min. typ. max t1 108 169 240 t5 194 308 442 t total 302 477 682 Unit : µsec ※CT1=1000pF, CT2=3300pF, scatter within 5% www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 16/20 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●When it inputs VCC, it outputted the gamma output voltage. 0.9Vcc 0.1Vcc Vcc tVcc V0 V1 ・ ・ ・ ・ tref Tref V9 Fig. 36 DAC 1ch supports all gamma output amps by sample/hold function. So, each amp operates reflesh by Tref. Min. Typ. Max. Tref 63 101 145 Unit : µsec Reflesh time of each amp is following. tref = Tref / 11ch Under condition of the small difference between setting voltage of amp and slew rate of VCC is fast, when it inputs VCC, it is possible that output voltage come from behind next output voltage. V0 = VDAC×2× V1 = VDAC’×2× VDAC’ = VDAC + n0 + 1 1024 n1+ 1 1024 SR ×tref 2 (n0 : Setting voltage of 10bit) (SR : Slew rate of VCC) Condition of non-reverse-voltage is following V0-V1>0 n0 + 1 n1 + 1 >1+ SR×tref 2VDAC Under condition of the big difference between output voltage or slew rate of VCC is slow, reverse-voltage don’t occur much. Worst condition is following. n0 / n1 > 1.0469 Notice that the setting voltage between V0 and V1 is within 720mV. It is possible for reverse of voltage in transition. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 17/20 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●Input equivalent circuit diagrams [BD8132FV] 1.LATCH 2.SDIN 3.CLK 6.RW 9.MEMDI 4.SDOUT 7.CS DVCC 8.MEMDO 10.OSC VCC DVCC 4kΩ 15.REFIN DVCC 4kΩ 10Ω 100kΩ 10Ω 100kΩ 200kΩ 200kΩ GND GND GND 16.VDAC 17.CT VCC 22.Vcom 21.FB DVCC GND VCC VCC 88kΩ 1kΩ 1kΩ 10Ω 200kΩ 50kΩ GND 114kΩ GND GND GND 23.VH 24.VG 25.VF 26.VE 27.VD 28.VC 29.VB 30.VA 31.V9 32.V8 33.V7 34.V6 35.V5 36.V4 37.V3 38.V2 39.V1 40.V0 VCC 10Ω 30kΩ Fig.37 I/O Equivalent Circuit Diagrams 30kΩ GND [BD8139AEFV] 1.A1 2.A2 5.STAN/INC 6.OSC_MODE (Pull down R 100kΩ) 7.SDA 8.SCL 4.OSC 16.REFIN VCC DVCC DVCC DVCC 100kΩ 4kΩ 4kΩ 100kΩ 10Ω 200kΩ 200kΩ GND GND GND 19.VDAC 13.CT 25.FB 26.Vcom VCC DVCC VCC GND VCC 88kΩ 1kΩ 1kΩ 10Ω 200kΩ 50kΩ 114kΩ GND GND GND GND 27.V9 28.V8 29.V7 30.V6 31.V5 32.V4 33.V3 34.V2 35.V1 36.V0 VCC 30kΩ 10Ω 30kΩ Fig.38 I/O Equivalent Circuit Diagrams GND www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 18/20 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●Notes for use 1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) GND potential Ensure a minimum GND pin potential in all operating conditions. 3) Setting of heat Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4) Pin short and mistake fitting Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the presence of a foreign object may result in damage to the IC. 5) Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. 6) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 7) Ground wiring patterns When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of any external components. 8) Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements.For example, when the resistors and transistors are connected to the pins as shown in Fig.39, a parasitic diode or a transistor operates by inverting the pin voltage and GND voltage.The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as the application of voltages lower than the GND (P substrate) voltage to input and output pins. Resistor Transistor (NPN) (Pin B) C E B ～ ～ ～ ～ (Pin B) ～ ～ B (Pin A) GND N N N Parasitic elements P＋ N N (Pin A) P substrate Parasitic element GND P P＋ ～ ～ P＋ N P GND N P P＋ Parasitic elements C E Parasitic element GND Fig.39 Example of a Simple Monolithic IC GND 9) Overcurrent protection circuits An overcurrent protection circuit designed according to the output current is incorporated for the prevention of IC damage that may result in the event of load shorting. This protection circuit is effective in preventing damage due to sudden and unexpected accidents. However, the IC should not be used in applications characterized by the continuous operation or transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capacity has negative characteristics to temperatures. 10) TSD (Thermal shutdown) circuit This IC incorporates a built-in TSD circuit for the protection from thermal destruction. The IC should be used within the specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power dissipation limits, the attendant rise in the chip's junction temperature Tj will trigger the TSD circuit to turn off all output power elements. The circuit automatically resets once the junction temperature Tj drops. Operation of the TSD circuit presumes that the IC's absolute maximum ratings have been exceeded. Application designs should never make use of the TSD circuit. 11) Testing on application boards At the time of inspection of the installation boards, when the capacitor is connected to the pin with low impedance, be sure to discharge electricity per process because it may load stresses to the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 19/20 2009.07 - Rev.B Technical Note BD8132FV, BD8139AEFV ●Ordering part number B D 8 Part No. 1 3 2 F Part No. 8132 : 3-line serial 8139A: 2 wire serial V - E 2 Package Packaging and forming specification FV: SSOP-B40 E2: Embossed tape and reel EFV: HTSSOP-B40 SSOP-B40 <Tape and Reel information> 13.6 ± 0.2 (MAX 13.95 include BURR) 0.5 ± 0.2 1 2000pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 20 0.15 ± 0.1 0.1 1.8 ± 0.1 Embossed carrier tape Quantity 21 5.4 ± 0.2 7.8 ± 0.3 40 Tape 0.1 S 0.65 0.22 ± 0.1 0.08 M 1pin Reel (Unit : mm) Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. HTSSOP-B40 <Tape and Reel information> 13.6±0.1 (MAX 13.95 include BURR) 4 +6 −4 (8.4) 1 Embossed carrier tape (with dry pack) Quantity 2000pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 20 1PIN MARK 1.0Max. 0.625 1.2 ± 0.2 (3.2) 0.5 ± 0.15 21 5.4±0.1 7.8±0.2 40 Tape +0.05 0.17 −0.03 0.85±0.05 0.08±0.05 S +0.05 0.24 −0.04 0.65 0.08 M 0.08 S 1pin Reel (Unit : mm) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 20/20 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2009.07 - Rev.B Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. R0039A