IDT IDT74FCT807CTP Fast cmos 1-to-10 clock driver Datasheet

IDT54/74FCT807BT/CT
FAST CMOS
1-TO-10
CLOCK DRIVER
Integrated Device Technology, Inc.
> 200V using machine model (C = 200pF, R = 0)
• Available in DIP, SOIC, SSOP, QSOP, Cerpack and
LCC packages
• Military product compliant to MIL-STD-883, Class B
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
Guaranteed low skew < 250ps (max.)
Very low duty cycle distortion < 350ps (max.)
High speed: propagation delay < 2.5ns (max.)
100MHz operation
TTL compatible inputs and outputs
TTL level output voltage swings
1:10 fanout
Output rise and fall time < 1.5ns (max.)
Low input capacitance: 4.5pF typical
High Drive: -32mA IOH, 48mA IOL
ESD > 2000V per MIL STD-883, Method 3015;
DESCRIPTION:
The IDT54/74FCT807BT/CT clock driver is built using
advanced dual metal CMOS technology. This low skew clock
driver features 1:10 fanout, providing minimal loading on the
preceding drivers. The IDT54/74FCT807BT/CT offers low
capacitance inputs with hysteresis for improved noise margins.
TTL level outputs and multiple power and grounds reduce
noise. The device also features -32/48mA drive capability for
driving low impedance traces.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
O1
IN
1
20
VCC
GND
2
19
O10
O1
3
18
O9
VCC
4
O2
5
GND
6
O3
7
VCC
O4
O2
O3
O4
O5
IN
O6
GND
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
17
GND
16
O8
15
VCC
14
O7
8
13
GND
9
12
O6
10
11
O5
O7
3017 drw 02
O10
3017 drw 01
VCC
4
O2
5
GND
6
O3
7
VCC
8
1
VCC
2
O10
3
IN
INDEX
O9
GND
O8
O1
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
20 19
L20-2
18
O9
17
GND
16
O8
15
VCC
14
O7
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.3
O6
GND
O5
LCC
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1995 Integrated Device Technology, Inc.
GND
O4
9 10 11 12 13
3017 drw 03
OCTOBER 1995
DSC-4242/3
1
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
IN
Input
Ox
Outputs
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
CIN
Input
Capacitance
COUT
Output
Capacitance
Description
3017 tbl 01
Conditions
VIN = 0V
Typ.
4.5
VOUT = 0V
5.5
Max. Unit
6.0
pF
8.0
pF
3017 lnk 02
NOTE:
1. This parameter is measured at characterization but not tested.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
TSTG
Storage
Temperature
I OUT
DC Output
Current
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
–0.5 to VCC
+0.5
–0.5 to VCC
+0.5
V
0 to +70
–55 to +125
°C
–55 to +125
–65 to +135
°C
–55 to +125
–65 to +150
°C
–60 to +120
–60 to +120
mA
3017 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability. No terminal voltage may exceed VCC by
+0.5V unless otherwise noted.
2. Input and VCC terminals.
3. Output and I/O terminals.
9.3
2
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified
Commercial: TA = 0°C to +70°C, V CC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
VIH
VIL
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Input LOW Level
Min.
2.0
Typ.(2)
—
Max.
—
Unit
V
Guaranteed Logic LOW Level
—
—
0.8
V
Input HIGH
Current (5)
VCC = Max.
VI = 2.7V
—
—
±1
µA
II L
Input LOW
Current (5)
VCC = Max.
VI = 0.5V
—
—
±1
µA
I OZH
High Impedance Output Current
VCC = Max.
VO = 2.7V
—
—
±1
µA
VO = 0.5V
—
—
±1
µA
II H
I OZL
(3-State Output
pins) (5)
Current (5)
II
Input HIGH
VIK
Clamp Diode Voltage
VCC = Max., VI = VCC (Max.)
—
—
±1
µA
VCC = Min., IIN= –18mA
—
–0.7
–1.2
V
–60
–120
–225
mA
2.4
3.3
—
V
2.0
3.0
—
—
0.3
0.55
V
—
—
±1
µA
—
150
—
mV
—
5
500
µA
Max.(3) ,
I OS
Short Circuit Current
VCC =
VOH
Output HIGH Voltage
VCC = Min.
VIN = VIH or VIL
VOL
Output LOW Voltage
IOFF
Input/Output Power Off Leakage(5)
VH
Input Hysteresis for all inputs
I CCL
I CCH
I CCZ
Quiescent Power Supply Current
VO = GND
I OH = –12mA MIL.
I OH = –15mA COM'L.
I OH = –24mA MIL.
I OH = –32mA COM'L.(4)
VCC = Min.
I OL = 32mA MIL.
VIN = VIH or VIL
I OL = 48mA COM'L.
VCC = 0V, VIN or VO ≤ 4.5V
—
VCC = Max., VIN = GND or V CC
3017 lnk 04
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
POWER SUPPLY CHARACTERISTICS
Symbol
ICCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current (3)
IC
Total Power Supply Current (5)
∆ICC
Test Conditions(1)
VCC = Max.
VIN = 3.4V
VCC = Max.
Input toggling
50% Duty Cycle
Outputs Open
VCC = Max.
Input toggling
50% Duty Cycle
Outputs Open
fi = 50MHz
Min.
Typ.(2)
Max.
Unit
—
0.5
2.0
mA
VIN = VCC
VIN = GND
—
0.4
0.6
mA/
MHz
VIN = VCC
VIN = GND
—
20.0
30.5 (4)
mA
VIN = 3.4V
VIN = GND
—
20.3
31.3 (4)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fi= Input Frequency
All currents are in milliamps and all frequencies are in megahertz.
9.3
3017 tbl 05
3
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
IDT54/74FCT807BT
Com'l.
Symbol
Parameter
tPLH
Propagation Delay
tPHL
tR
Output Rise Time
Conditions(1) Min.(2)
50Ω to VCC/2,
CL = 10pF
(See figure 1)
Max.
1.3
2.7
—
1.5
Mil.
Min.(2)
Max.
—
IDT54/74FCT807CT
Com'l.
Min.(2)
Max.
1.3
2.5
—
1.5
Mil.
Min.(2)
Max.
—
Unit
ns
ns
tF
Output Fall Time
or 50Ω ac
—
1.5
—
—
1.5
—
ns
tSK(o)
Output skew: skew between outputs of
same package (same transition)
termination,
CL = 10pF
—
0.5
—
—
0.25
—
ns
tSK(p)
Pulse skew: skew between opposite
transitions of same output (|tPHL -– tPLH|)
(See figure 2)
f ≤ 100MHz
—
0.5
—
—
0.35
—
ns
tSK(t)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
Outputs
connected in
groups of two
—
0.9
—
—
0.65
—
ns
3017 tbl 06
Symbol
Parameter
tPLH
Propagation Delay
tPHL
tR
Output Rise Time
IDT54/74FCT807BT
IDT54/74FCT807CT
Com'l.
Com'l.
Conditions(1) Min.(2)
Max.
CL = 30pF
f ≤ 67MHz
(See figure 3)
1.5
3.8
—
1.5
Mil.
Min.(2)
Max.
—
Min.(2)
Max.
1.5
3.5
—
1.5
Mil.
Min.(2)
Max.
—
Unit
ns
ns
tF
Output Fall Time
—
1.5
—
—
1.5
—
ns
tSK(o)
Output skew: skew between outputs of
same package (same transition)
—
0.5
—
—
0.25
—
ns
tSK(p)
Pulse skew: skew between opposite
transitions of same output (|tPHL -– tPLH|)
—
0.5
—
—
0.35
—
ns
tSK(t)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
—
0.9
—
—
0.75
—
ns
3017 tbl 07
Symbol
Parameter
tPLH
Propagation Delay
tPHL
tR
Output Rise Time
IDT54/74FCT807BT
IDT54/74FCT807CT
Com'l.
Com'l.
Conditions(1) Min.(2)
Max.
CL = 50pF
f ≤ 40MHz
(See figure 4)
1.5
3.8
—
1.5
Mil.
Min.(2)
Mil.
Min.(2)
Max.
1.5
3.5
—
—
1.5
—
ns
Max.
Min.(2)
Max.
Unit
ns
tF
Output Fall Time
—
1.5
—
—
1.5
—
ns
tSK(o)
Output skew: skew between outputs of
same package (same transition)
—
0.5
—
—
0.35
—
ns
tSK(p)
Pulse skew: skew between opposite
transitions of same output (|tPHL -– tPLH|)
—
0.60
—
—
0.45
—
ns
tSK(t)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
—
1.0
—
—
0.75
—
ns
3017 tbl 08
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay
limits do not imply skew.
9.3
4
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS
50Ω TO VCC/2, CL = 10pF
50Ω AC TERMINATION, CL = 10pF
V CC
V CC
V CC
100Ω
V IN
V IN
V OUT
Pulse
Generator
V OUT
Pulse
Generator
D.U.T.
50Ω
10pF
100Ω
RT
D.U.T.
10pF
RT
220pF
3017 drw 04
3017 drw 05
The capacitor value for ac termination is determined by the operating
frequency. For very low frequencies a higher capacitor value should be
selected.
Figure 2.
Figure 1.
CL = 50pF CIRCUIT
CL = 30pF CIRCUIT
V CC
V CC
V OUT
V IN
Pulse
Generator
V OUT
V IN
Pulse
Generator
D.U.T.
D.U.T.
30pF
RT
50pF
RT
CL
CL
3017 drw 06
3017 drw 07
Figure 3.
Figure 4.
ENABLE AND DISABLE TIME CIRCUIT
ENABLE AND DISABLE TIME
SWITCH POSITION
V CC
7.0V
500Ω
V OUT
V IN
Pulse
Generator
D.U.T.
50pF
RT
Test
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
Switch
Closed
Open
3017 lnk 09
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
500Ω
CL
3017 drw 08
Figure 5.
9.3
5
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST WAVEFORMS
PACKAGE DELAY
OUTPUT SKEW- tSK(o)
3V
1.5V
INPUT
INPUT
tPLH1
0V
tPLH
3V
1.5V
0V
tPHL1
VOH
1.5V
VOL
tPHL
VOH
2.0V
OUTPUT 1
tSK(o)
tSK(o)
1.5V
VOH
1.5V
VOL
0.8V VOL
OUTPUT
OUTPUT 2
tPLH2
tF
tR
tPHL2
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
3017 drw 09
PULSE SKEW - tSK(p)
3017 drw 10
PACKAGE SKEW - tSK(t)
3V
1.5V
0V
INPUT
tPHL
tPLH
OUTPUT
INPUT
VOH
1.5V
VOL
tPHL1
tPLH1
PACKAGE 1 OUTPUT
tSK(t)
tSK(p) = |tPHL - tPLH|
PACKAGE 2 OUTPUT
tPLH2
tSK(t)
tPHL2
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
3017 drw 11
Package 1 and Package 2 are same device type and speed grade
3017 drw 12
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
CONTROL
INPUT
1.5V
0V
t PLZ
t PZL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
3.5V
1.5V
SWITCH
OPEN
0.3V
VOL
0.3V
VOH
t PHZ
t PZH
OUTPUT
NORMALLY
HIGH
3.5V
1.5V
0V
0V
3017 drw 13
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
9.3
6
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
Temp. Range
FCT
XXXX
Device Type
X
X
Package
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
D
SO
L
E
PY
Q
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Shrink Small Outline IC
Quarter-size Small Outline IC
807BT
807CT
1-to-10 Clock Driver
54
74
–55°C to +125°C
0°C to +70°C
3017 drw 14
9.3
7
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