MITSUBISHI ICs (TV)
M65667FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION
APPLICATION
The M65667FP is a NTSC PIP (Picture in Picture) signal
NTSC color TV
processing LSI, whose sub and main-picture inputs are composite
and Y/C separated signals, respectively. The built-in field memory
RECOMMENDED OPERATING CONDITION
(96k-bit RAM) ,V-chip data slicer and analog circuitries lead the PIP
Supply voltage range........................................................3.1 to 3.5V
system low cost and small size.
Operating frequency.........................................................14.32 MHz
Operating temperature....................................................-20 to 75 °C
FEATURES
"L".............................0 to VDD×0.3V
Output current (output buffer)........................................ ±4mA (MAX)
Output load capacitance............................................20pF (MAX)
∗1
Circuit current.........................................................................160mA
NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS
pins.
∗1 : Include pin capacitance (7pF)
33 NC
34 LOCK/TEST7
35 DVdd3
37 Cout-sub
36 DVss3
38 ADJ-Csub
39 Yout-sub
41 Y-PIPin
40 ADJ-Ysub
42 AVss4 (da)
43 AVss4 (da)
44 C-PIPin
46 AVdd4 (da)
45 AVdd4 (da)
47 AVdd4 (da)
PIN CONFIGURATION (TOP VIEW)
48 C-PIP
32 NC
NC 49
31 VD/CSYNC/TEST6
TEST8 50
30 HD/TEST5
Y-PIP 51
29 SWM/TEST4
TEST9 52
28 MCK
Yin 53
27 fsc/TEST3
TESTEN 54
26 BGP (m)/TEST2
Cin 55
AVss (ana) 56
25 DVdd2 (ram)
M65667FP
AVss3 (VCXO) 57
24 DVss2 (ram)
23 CLK
VCXO out 58
22 DATA
VCXO in 59
FILTER 60
21 ACK
20 CSYNC (s)/TEST1
BIAS 61
19 SCK
AVdd3 (VCXO) 62
Outline 64P6N-A
NC 16
DVss1 14
DVdd1 15
RESET 13
AVss1 (s) 12
AVss1 (s) 11
Vrb (s) 10
Vrt (s) 9
Vin (s) 8
AVdd1 (s) 7
AVdd1 (s) 6
17 NC
AVss2 (m) 5
18 BGP (s)/TEST0
AVdd2 (m) 64
AVss2 (m) 4
AVdd2 (m) 63
Vrb (m) 3
•
Vrt (m) 2
•
•
Input voltage (CMOS interface) "H"........................V DD×0.7 to VDD V
Built-in 96k-bit field memory (sub-picture data storage)
Internal V-chip data slicer (for sub-picture)
Vertical filter for sub-picture (Y signal )
Single sub-picture (selectable picture size : 1/9 , 1/16)
Sub-picture processing sepecification (1/9 size / 1/16 size) :
Quantization bits
Y, B-Y, R-Y : 6bits
Horizontal sampling 171 pixels (Y) , 28.5 pixels (B-Y, R-Y)
Vertical lines
69/ 52 lines
Frame (sub-picture) on/off
Built-in analog circuits :
Two 8-bit A/D converters (main and sub-picture signals)
Two 8-bit D/A converters (Y and C sub-picture signals)
Sync-tip-clump, VCXO, Analog switch ... etc.
I2C BUS control (parallel/serial control) :
PIP on/off , Sub-picture size(1/9 or 1/16), Frame on/off
(programmable luma level), PIP position (4 corners fixed
position), Picture freeze , Y delay adjustment, Chroma level, Tint,
Black level, Contrast ... etc.
Vin (m) 1
•
•
•
•
•
NC : NO CONNECTION
1
MITSUBISHI ICs (TV)
M65667FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
BLOCK DIAGRAM
CSYNC(s)
/TEST1
SCK
BGP(s)
/TEST0
Yin
Y- PIP
Sync tip
Clamp
Cin
Vdd / Vss
for test
DATA
CLK
Bias
RAM(1H)
3
3
V-chip
data slicer
I2C
I/F
ACK
Vin(s)
Bias
A/D
8bit
Vert-filter
Sync
Sep
Phase
Select
C
Timing Gen
(Decode)
AFC
Demod
Tint
B-Y
6
R-Y
6
2
(I C)
Delay
Encode
D/A
8bit
Yout-sub
D/A
8bit
Cout-sub
Delay
Delay
MIX
SWMG
/TEST7
Y
6 B-Y
LPF
&MPY
fsc
6
6 R-Y
Vin(m)
Bias
A/D
8bit
Timing Gen
(Memory
Cont)
RAM
96Kbits
VD
/CSYNC
/TEST6
HD
/TEST5
FILTER
Lock/Free-run
via I2C
2
RESET
MCK
BGP(m)
/TEST2
fsc
/TEST3
BIAS
4fsc
Phase
Detect
Burst Data
Sampling
Y- PIPin
&
Level
Detect
ADJ-Csub
Vrt(m)
Vrb(m)
4fsc
Back Porch
Clamp
MUX
Y
B-Y
R-Y
Demux
HPLL
ADJ-Ysub
C- PIPin
6
Y/C SEP
(LPF,BPF)
2
HD
Y
Delay
Luma
Clamp
Y
Sync tip
Clamp
Vrt(m)
Vrb(m)
C- PIP
15
VCXO
Driver
VCXO
VCXO in
VCXO out
SWM
/TEST4
2
MITSUBISHI ICs (TV)
M65667FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION OF PIN
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Name
Vin (m)
Vrt (m)
Vrb (m)
AVss2 (m)
AVss2 (m)
AVdd1 (s)
AVdd1 (s)
Vin (s)
Vrt (s)
Vrb (s)
AVss1 (s)
AVss1 (s)
RESET
DVss1
DVdd1
NC
NC
I/O
I
O
O
GND
GND
Vdd
Vdd
I
O
O
GND
GND
I
GND
Vdd
Function
Chroma signal input (main-picture)
A/D Vref+ (main-picture)
A/D Vref- (main-picture)
Connect to analog GND
Connect to analog GND
Connect to analog power supply
Connect to analog power supply
Composite video signal input (sub-picture)
A/D Vref+ (sub-picture)
A/D Vref- (sub-picture)
Connect to analog GND
Connect to analog GND
Power on reset input signal ("L" reset)
Connect to digital GND
Connect to digital power supply
BGP(s)/TEST0
For test
For test (connect to digital GND)
For test (connect to digital GND)
ACK
(I/)O
I
I(/O)
O
22
DATA
I
I2C bus-data input signal
23
CLK
I
24
25
26
27
28
29
30
DVss2(ram)
DVdd2(ram)
GND
Vdd
(I/)O
I(/O)
I
(I/)O
I(/O)
I2C bus-clock input signal
Connect to digital GND
Connect to digital power supply
For test
For test (pull down to digital GND by resistor 15k Ω)
For test (connect to digital GND)
For test
Horizontal sync input signal (Positive going edge is used)
I(/O)
Vertical sync input signal (active "H")
I(/O)
Vdd
GND
O
I
O
I
I
GND
GND
I
Vdd
Vdd
Vdd
O
Enable input signal to display sub picture ("H" enable)
Connect to digital power supply
Connect to digital GND
D/A output signal (Chroma signal of sub-picture)
D/A adjust for chroma signal (sub-picture)
D/A output signal (Luma signal of sub-picture)
D/A adjust for luma signal (sub-picture)
PIP luma signal re-input
Connects to analog GND
Connects to analog GND
PIP chroma signal re-input
Connect to analog power supply
Connect to analog power supply
Connect to analog power supply
PIP chroma signal output
pull up 15k Ω
For test (connect to analog GND)
PIP luma signal output
For test (connect to analog GND)
pull up 15k Ω
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
SCK
CSYNC(s)/TEST1
BGP(m)/TEST2
fsc/TEST3
MCK
SWM/TEST4
HD/TEST5
VD/CSYNC
/TEST6
NC
NC
SWMG/TEST7
DVdd3
DVss3
Cout-sub
ADJ-Csub
Yout-sub
ADJ-Ysub
Y-PIPin
AVss4 (da)
AVss4 (da)
C-PIPin
AVdd4 (da)
AVdd4 (da)
AVdd4 (da)
C-PIP
NC
TEST8
Y-PIP
TEST9
I
O
I
Remarks
100kΩ to VDD,10µF to GND
non connect
connect to GND
pull down 15k Ω
I2C bus-data/Acknowledge output signal
non connect
pull down 15kΩ
connect to GND
non connect
connect to GND
3
MITSUBISHI ICs (TV)
M65667FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION OF PIN (cont.)
Pin No.
53
54
55
56
57
58
59
60
61
62
63
64
Name
Yin
TESTEN
Cin
AVss (ana)
AVss3 (VCXO)
VCXO out
VCXO in
FILTER
BIAS
AVdd3 (VCXO)
AVdd2 (m)
AVdd2 (m)
I/O
I
I
I
GND
GND
O
I
I
O
Vdd
Vdd
Vdd
Function
Luma input signal (main-picture)
For test (connect to analog GND)
Chroma input signal (main-picture)
Connect to analog GND
Connects to analog GND
VCXO output signal
VCXO input signal
Filter
Bias
Connect to analog power supply
Connect to analog power supply
Connect to analog power supply
Remarks
connect to GND
ABSOLUTE MAXIMUM RATINGS (VSS=0V)
Symbol
Parameter
VDD3
VI
VO
Supply voltage (3.3V)
Input voltage
Output voltage
IO
Output current (∗1)
Pd
Topr
Tstg
Power dissipation
Operating temperature
Storage temperature
Limits
Min.
Max.
-0.3
4.6
-0.3 VDD3+0.3
-0.3 VDD3+0.3
−
IOL=20
IOH=-26
−
−
-20
-50
1400
75
125
Unit
V
V
V
mA
mW
°C
°C
∗1: Output current per output terminal. But Pd limits all current.
4
MITSUBISHI ICs (TV)
M65667FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
DC CHARACTERISTICS (Ta=25°C, unless otherwise noted, VSS=0V)
Symbol
VIL
VIH
VTV T+
VH
VOL
VOH
IOL
IOH
IIH
IIL
IOZL
IOZH
CI
CO
CIO
IDD
Parameter
Test conditions
Input voltage
(CMOS interface)
Input voltage schmitt trigger
(CMOS interface)
L
H
–
+
VDD=2.7V
VDD=3.6V
VDD=3.3V
Hysteresis
L
Output voltage
VDD=3.3V, | IO | <1µA
H
L
H
Output current
VDD=3.0V, VOL=0.4V
VDD=3.0V, VOH=2.6V
VDD=3.6V, VI=0V
VDD=3.6V, VI=3.6V
VDD=3.6V, VO=0V
VDD=3.6V, VO=3.6V
L
H
L
H
Input current
Output leakage current
Input pin capacitance
Output pin capacitance
Bidirectional pin capacitance
Operating current
f=1MHz, VDD=0V
3.3V supply
Min.
Limits
Typ.
Max.
0
2.52
0.5
1.4
0.3
−
3.25
4
−
-1
-1
-1
-1
−
−
−
−
−
−
−
−
−
−
−
−
−
0.81
3.6
1.65
2.4
1.2
0.05
−
−
-4
1
1
1
1
V
V
V
V
V
V
V
mA
mA
µA
µA
µA
µA
−
−
−
−
7
7
7
−
15
15
15
140
pF
pF
pF
mA
Unit
TYPICAL CHARACTERISTICS
THERMAL DERATING (MAXIMUM RATING)
POWER DISSIPATION Pd (mW)
2000
1600
1280
1200
800
400
0
0
25
50
75
100
125
AMBIENT TEMPERATURE Ta (°C)
5
MITSUBISHI ICs (TV)
M65667FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
470
Ana.
10µ
103
Ana.
150p
360
Dig
10µ
104
104 103
103
103
Ana.
32
50
31
51
30
52
29
104 53
28
54
27
104 55
26
15k
PIP Luma signal output
Luma signal input
(main-picture)
Chroma input signal
(main-picture)
56
51 14p
104 330
103
103
2k
10µ
Ana.
3.3µ
470k
100k
24
58
23
59
22
60
21
61
20
62
19
63
18
64
2
3
4
5
6
7
104 103 103
Digital GND
Composite video
input signal
(sub-picture)
8
9
100 SCL
47k
SDA
10k
103 10µ
Dig5V 12k
100
100
47k
560
330
10 11 12 13 14 15 16
10µ
103
100k
103
Ana.
104
Ana. Analog +3.3V
power supply
Analog GND
Dig5V 12k
103 103
10µ
Ana.
Dig
17
1
Digital +3.3V
power supply
10k
15k
25
M65667FP
57
I2C BUS Clock
input signal
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
I2C BUS DATA
input /output signal
68p
Horizontal sync input signal (main-picture)
Ana.
Vertical sync input signal (main-picture)
Sub-picture displaying on/off
PIP Chroma signal output
APPLICATION EXAMPLE
10µ
SYNC SEP
CIRCUIT
(OPTIONAL)
Dig
Separate Y/C signals by using LC-tank circuit or LPF,BPF for Y/C signals level adjust.
And then mix both signals for sub-picture input video signal.
Units Resistance : Ω
Capacitance : F
6
MITSUBISHI ICs (TV)
M65667FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
PIP TV SYSTEM BLOCK DIAGRAM
(BASIC)
Composite
Y/C
Y
Video Signal
Separation
C
Y
M65667FP
Y
C
Video
Signal
Processing
C
BLPLL
B-LD
Y/C Separated
Y
Video Signal
C
CV
Y
PIP Signal
Processing
Deflection
Unit
Yoke
C
HD
(Driving Method and Operating Specification for
Serial Interface Data)
VD
In right after the forming of serial data transmitting state, the slave
address 24h (00100100b) is transferred. Afterwards, the internal
register address (1 byte) and setting data (by 1 byte unit) are
(1) Serial data transmission completion and start
transferred successively. Several bytes of setting data can be
A low-to-high transition of the DATA (serial data) line while the CLK
handled in the one transmission. In this operation, the setting data
(serial clock) is high, that completes the serial transmission and
are written into the address register whose address is increased
makes the bus free.
one in initially transferred internal register address. (The next
A high-to-low transition of the DATA line while the CLK is high, that
address of 7Fh, it returns to 00h).
starts the serial transmission and waits for the following CLK and
2. The byte format during data reading from M65667FP are shown
DATA inputs.
as follows.
(2) Serial data transmission
Before data reading from M65667FP, whose internal address need
The data are transmitted in the most significant bit (MSB) first by
to be set by the data reading/transmitting. After the data reading/
one-byte unit on the DATA line successively. One-byte data
transmitting, the operation of "serial data transmission completion
transmission is completed by 9 clock cycles, the former 8 cycles are
and start" (described in (1)) is necessary. Continuously, the slave
for address/data and the latter one is for acknowledge detection. (In
address 25h (00100101b) is sent, and then the inverted read out
reading state, ACK is 'H' under these two conditions ; 1) the
data are available on ACK. Several bytes of writing data can be
coincidence of two address data for the address data transmission,
handled in the one transmission, too. In this operation, the setting
2) the completion of 8-bit setting data transfer. In writing state, ACK
data also are written into the address register whose address is
is 'H' with the address coincidence and ACK is 'L' for detecting
increased one in initially transferred internal register address. (The
acknowledge input from the master (micro processor) after sending
next address of 7Fh, it returns to 00h).
8-bit setting data.)
For address/data transmission, DATA must change while CLK is 'L'.
(The data change while CLK is 'H' or the simultaneous change of
CLK and DATA, that will be a false operation because of
undistinguished condition from the completion/start of serial data
transfer).
After the beginning of serial data transmission, the total number of
data bytes that can be transferred are not limited.
(3) The byte format of data transmission (The sequence of data
transmission)
1. The byte format during data setting to M65667FP are shown as
follows.
7
MITSUBISHI ICs (TV)
M65667FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
(The examples of serial byte transmission format)
(1) The writing operation of the setting data (AAh) into M65667FP internal address of 00h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
yes
S
24h
A
00h
A
AAh
A D E
no
S : Operation of serial transmission start
A : Acknowledge detection
is applied
on CLk for the
release of
output state
D : Dummy clock feed for the release of
acknowledge output state
E : Operation of serial transmission completion
(2) The writing operation of the setting data (FFh, 80h, EEh) into M65667FP internal address of 04h to 06h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
yes
S
24h
A
04h
A
FFh
A
80h
A
A D E
EEh
no
is applied
on CLk for the
release of
output state
(3) The reading operation of the setting data from M65667FP internal address of 00h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
yes
S
24h
A
00h
A D E
S
25h
A
$$h
A’
no
A’ : Bus free operation by the
is applied
on CLk for the
release of
output state
master (micro processor)
8
MITSUBISHI ICs (TV)
M65667FP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
(4) The reading operation of the setting data from M65667FP internal address of 04h to 06h
Confirmation
of bus free
(DATA='H')
Transmission
Activation
yes
S
24h
A
04h
A D E
S
25h
A
SSh
A’’
SSh
A’’
SSh
A’
no
A’’ : Output ‘L’ operation by the
is applied
on CLk for the
release of
output state
master (micro processor)
TIMING DIAGRAM
1
2
3
4
5
6
8
7
9
1
CLK
DATA
Bit7
(MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit7
(MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
(LSB)
ACK
Detec.
Bit7
(MSB)
ACK
_ Acknowledge
ACK
_ Readout data
Bit0
(LSB)
Bit7
(MSB)
9