MITSUBISHI ICs (TV) M65677FP DIGITAL NTSC/PAL ENCODER DESCRIPTION The M65677FP encodes CCIR601 or CCIR656 format Y/Cb/Cr data Note into analog NTSC and PAL video signals, including Digital Signal (Note1): This device is protected by U.S. patent numbers 4631603, Processing functions such as Closed Caption encoding, Overlay 4577216 and 4819098 and other intellectual property OSD, Anti Video Copy Processing (Note1) e.t.c. It also includes rights. The use of Macrovision Corporation's copy peripheral processing function such as 10bit DAC e.t.c., so that low protection technology in the device must be authorized by cost and compact system can be realized. Macrovision and is intended for home and other limited pay-par-view uses only, unless otherwise authorized in FEATURES writing by Macrovision. Reverse engineering or • disassembly is prohibited. • • • • • • • • • • • • • • • • Macrovision’s video anti copy process Rev 7.01 supported (Note1) Overlay CGMS signal on line 20/283 for 525/60 (Note3) Generate CRCC for CGMS Signal Overlay WSS signal on line 23 for 625/50 (Note4) Color adjustment (TINT/color control) NTSC, B/G PAL or MPAL Video Outputs Component Y/C Video (S-Video) and CVBS or Y/U/V Outputs Supporting CCIR601 and CCIR656 format data Closed Caption Manager on line 21/284 for NTSC Generate ODD parity for Closed Caption Manager H/V Sync and Composite generating Overlay Digital OSD Supporting Y/Cb/Cr 4:4:4 Over sampling Filter 2ch 10bit DAC and 3ch 6dB Amp (Note2) 3.3V I/O interface I2C Bus Interface for Controls Power down mode (Note2): 6dB Amp max. output is 1.0VP-P. (Note3): Copy Generation Management System-A (IEC1880) (Note4): Wide Screen Signaling (ETS300 294) APPLICATION DVB, DVD , Digital CATV, Video CD 33 C CVBS 34 N.C. 35 Y 37 36 AVSS2 Y in 39 38 AVDD2 C in 40 N.C 41 DAC 42 Ccomp 44 AVDD1 DAY 46 43 Cref 47 Ycomp 49 32 N.C. N.C. 50 31 N.C. DVDD1 51 30 DVDD1 DVSS1 52 29 TEST X out 53 28 SCL X in 54 27 SDA DVSS2 55 26 ACK 25 RESET PXD7 56 PXD6 57 24 Master/slave PXD5 58 23 OSD2 PXD4 59 22 OSD1 PXD3 60 21 OSD0 PXD2 61 20 OSDCK PXD1 62 19 DVSS1 PXD0 63 18 DVDD1 DVDD2 64 17 DVDD2 15 VD0 Outline 64P6N-A DVSS2 16 14 11 VD4 VD1 10 VD5 12 9 VD6 13 8 VD7 VD2 7 VD8 VD3 5 6 HD VD 3 4 DVASEL VD9 2 PXCLK M65677FP DVSS2 1 1 45 AVSS1 Yref 48 PIN CONFIGURATION (TOP VIEW) NC : NO CONNECTION CCIR601 or 656 Pixel Data from MPEG decoder From/To MPEG decoder SCL SDA ACK Master /Slave VD serial interface Sync Processing OSDCK Cr Cb OSD2 OSD1 OSD0 Cr Cb Y/U/V V U Anti Copy Processing ENCODE CGMS/WSS Manager C/V DAC DAC Y/C MIX 6dB 6dB 6dB DVss1(X2) DVss2(X2) DVdd2(X2) DVdd1(X2) RESET TEST CVBS C Y Video output HD Input Interface Y/U AVSS2 AVDD2 VD [9:0] Y Y/Cb/Cr Closed Caption Manager Y ref C ref AVdd1 OSD Interface Y AVss1 Yin PXD [7:0] Y Cin Clamp & bias BPF LPF Y OSD Control I/F MITSUBISHI ICs (TV) M65677FP DIGITAL NTSC/PAL ENCODER BLOCK DIAGRAM DAC DAY From micro controler 2 MITSUBISHI ICs (TV) M65677FP DIGITAL NTSC/PAL ENCODER ABSOLUTE MAXIMUM RATINGS Symbol VDD VI VO Ta Tstg Parameter Supply voltage Digital input voltage Digital output voltage Operating temperature Storage temperature Min. -0.3 -0.3 -0.3 -20 -40 Limits Typ. Max. 4.5 VDD+0.3 VDD+0.3 +25 +75 +125 Unit V V V °C °C RECOMMENDED OPERATING CONDITION (Ta=25°C, DVDD=AVDD=3.3V, DVSS=AVSS=0V, unless otherwise noted) Symbol Parameter Supply Digital supply voltage DVDDX AVDDX Analog supply voltage DIDD Digital current consumption AIDD Analog current consumption Digital input VIL Input voltage VIH IIL/IIL Input leakage current CI Input capacitance Digital output VOL Output voltage VOH CO Output capacitance I2C bus IO Output current IOZ Output leakage current (off) D/A converter Res Resolution INL Integral non-linearity error DNL Differential non-linearity error VfSMAX Maximum output amplitude Test conditions 3.0 3.15 0 0 DVDD=3.0V DVDD=3.6V DVDD=3.0V, VI=0V or VI=3.6V f=1MHz, VDD=0V DVDD=3.3V, | IO |<1µA DVDD=3.0V, VIL=0.4V DVDD=3.6V, VI=0V or VI=3.6V 3 Yin clamp discharge current Vyicl Vyocl Vcvcl Vcin Vcob Iamp Yin input clamp voltage Y output clamp voltage CVBS output clamp voltage Cin input bias voltage C output bias voltage Output current Limits Typ. 3.3 3.3 0 2.5 7 Max. 7 V V mA mA 0.8 3.6 ±15 15 V V µA pF 0.05 15 V V pF ±15 mA µA ±2.0 ±1.0 Bit LSB LSB 4.0 10 1.5 Ryicl= - Iyich Iyids Unit 3.6 3.45 45 55 3.25 f=1MHz, VDD=0V 6-dB amplifier Rbias Bias resistor GV_YC Output gain (Y/C) GV_CV Output gain (CVBS) DRin Input dynamic range DRout Output dynamic range Iyich Yin clamp charge current Iyids Yin clamp discharge current Ryicl Min. VP-P 7.5 5.50 5.10 0.8 1.6 -12 0.26 10.0 6.00 6.00 11.5 6.50 6.85 -26 0.65 -50 1.80 20 0.65 70 0.45 0.40 0.30 0.95 0.90 1.00 0.50 0.50 0.50 1.00 1.00 0.55 0.60 0.70 1.05 1.10 kΩ dB dB VP-P VP-P µA µA – V V V V V mA MITSUBISHI ICs (TV) M65677FP DIGITAL NTSC/PAL ENCODER DESCRIPTION OF PIN Pin No. 1 Pin name DVSS2 Type Supply Digital ground for the I/O. Function 2 PXCLK O Reference clock for input pixel data. The clock frequency is 27.0MHz. 3 DVASEL I I2C slave address setting. "Low" is for the address of 40h, "High" is for the address of 42h. 4 HD I/O Horizontal sync signal input or output. It is an input and output in the slave and master mode, respectively. 5 VD I/O Vertical sync input or output. Or OddEven signal output. It is an input and output in the slave and master mode, respectively. 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 DVSS2 DVDD2 DVDD1 DVSS1 I/O Video data outputs. In the Y/U/V output mode, the output is the 10-bit digital luma signal with a composite sync. VD9 is MSB and VD0 is LSB. 20 OSDCK 21 OSD0 22 23 OSD1 OSD2 I 24 Master/Slave I 25 26 27 28 RESET ACK SDA SCL 29 TEST 30 31 32 DVDD1 N.C. N.C. 33 C 34 N.C. 35 CVBS 36 AVSS2 37 Y 38 AVDD2 39 Yin 40 N.C. 41 Cin Supply Supply Supply Supply O I O I/O I Digital ground for the I/O. Digital supply for the I/O. Digital supply for the internal logic. Digital ground for the internal logic. The reference clock for an external OSD microcontroller. The frequency is 13.5MHz or 6.25MHz, alternated by the I 2C bus control. The color look-up table address input. MSB and LSB is OSD2 and OSD0, respectively. Synchronizing mode selection. "Low" is for the slave mode. "High" is for the master mode. Initializing reset. "LOW" is active. Acknowledge line (Open drain output). Serial data line/Acknowledge line (Open drain output). Serial clock line. For testing. It should be grounded during an actual use. Supply Digital supply for the internal logic. No connection. No connection. I O The analog chroma output from a 6dB amplifier. The output amplitude is 1.0VP-P (typ.), while the input is 0.5VP-P. No connection. The analog composite video signal from a 6dB amplifier. The output amplitude is 1.24VP-P (typ.). Supply Analog ground for 6dB amplifiers. O The analog luma output from a 6dB amplifier. The output amplitude is 1.2VP-P (typ.), while input is 0.6VP-P. Supply Analog supply for 6dB amplifiers. O I I The analog luma input from an external LPF. This input has bias circuit. The signal must input via a capacitor. No connection. The analog chroma input from an external LPF. This input has bias circuit. The signal must input via a capacitor. 4 MITSUBISHI ICs (TV) M65677FP DIGITAL NTSC/PAL ENCODER DESCRIPTION OF PIN (cont.) Pin No. 5 Pin name Type Function Phase compensation for chroma or V output DAC. I It should be connected to the analog ground via a capacitor. Chroma or V signal output. O The DAC output should be connected to the analog supply via a load resistor (R L). The output amplitude is set up by reference resistor (Rref) and RL. Supply Analog supply for DACs. Supply Analog ground for DACs. Luma or U signal output. O It should be connected to the analog supply via a load resistor (RL). The output amplitude is set up by reference resistor (Rref) and RL. 42 Ccomp 43 DAC 44 45 AVDD1 AVSS1 46 DAY 47 Cref I A reference current source for chroma or V signal output DAC. It should be connected to the analog supply via a reference resistor (Rref). 48 Yref I A reference current source for Y or U DAC. It should be connected to the analog supply via a reference resistor (Rref). 49 Ycomp 50 51 52 N.C. DVDD1 DVSS1 53 Xout 54 Xin 55 56 57 58 59 60 61 62 63 64 DVSS2 PXD7 PXD6 PXD5 PXD4 PXD3 PXD2 PXD1 PXD0 DVDD2 Phase compensation for Y or U DAC. It should be connected to the analog ground via a capacitor. No connection. Supply Digital supply for the internal logic. Supply Digital ground for the internal logic. I O System clock output. It must be in no connection except for a connection to a X'tal oscillator. System clock input. The clock frequency is only 27.0MHz. Supply Digital ground for the I/O. I I Pixel data inputs. The acceptable video data are; • multiplexed video data (Y/Cb/Cr) including timing reference code of SAV and EAV, defined in CCIR Rec656 • multiplexed video data (Y/Cb/Cr) defined in CCIR Rec601 MSB and LSB is PXD7 and PXD0, respectively. Supply Digital supply for the I/O. MITSUBISHI ICs (TV) M65677FP DIGITAL NTSC/PAL ENCODER APPLICATION EXAMPLE 220µ C 75 0.1µ Y 75 75 220µ 75Ω Driver Audio out (R) Rch OSD micro computer M35041 DIN LRCIN BCKIN XTI Audio DAC PXD HSYNC VSYNC 8 BDER CLK in BCLK BDEN BDREQ SCL SDA/ACK RESET AO0 MPEG2 AO1 System/ AO2 Video/Audio AO3 Decoder M65773FP LRCLK BD 27MHz XO 16M SDRAM PXCLK 47µ 0.01µ VSS VDD Audio out (L) VDD VSS 3.3k R/G/B OSC1 VD HD RESET CS SCK SIN HD VD PXD(7:0) PXCLK SDA SCL 3 RESET OSD(2:0) OSDCK ACK 47µ 0.01µ Lch Y C CVBS Y in 2.2µ 2.2µ 0.1µ 2.2µ Filter Stage 200 M65677FP DVDD X out X in DAC 200 C in 0.1µ DAY Yref Digital NTSC/PAL Encoder VD(9:0) 47µ 0.01µ TEST Master/Slave DVASEL DVSS 27MHz Filter Stage 10k 10k 0.1µ 0.1µ AVDD AVss Ccomp Ycomp Cref 47µ 0.01µ CVBS (CCIR656 I/F, Y/C/CVBS Output Mode) DOCLK DACCLK ACLKO ACLKI Chanel Decoder RESET CS SCK SIN BDER BD RCLK BDEN BDREQ 8 3.3k Host CPU : 3.3V Power Supply (for Digital/Analog) : 5.0V Power Supply (for Analog) Units Resistance : Ω Capacitance : F 6