AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 Integrated Analog Front-End for Heart Rate Monitors and Low-Cost Pulse Oximeters Check for Samples: AFE4400 FEATURES APPLICATIONS • • • • 23 • • • • • • Fully-Integrated Analog Front-End for Pulse Oximeter Applications: – Flexible Pulse Sequencing and Timing Control Transmit: – Integrated LED Driver (H-Bridge or Push/Pull) – 95-dB Dynamic Range – LED Current: – Programmable to 50 mA with 8-Bit Current Resolution – Low Power: – 100 µA + Average LED Current – Programmable LED On-Time – Independent LED2 and LED1 Current Reference Receive Channel with High Dynamic Range: – 13 Noise-Free Bits (0.1 Hz to 5 Hz) – Low Power: < 670 µA at 3.3-V Supply – Flexible Receive Sample Time – Flexible Transimpedance Amplifier with Programmable LED Settings – Integrated Digital Ambient Estimation and Subtraction Integrated Fault Diagnostics: – Photodiode and LED Open and Short Detection – Cable On/Off Detection Supplies: – Rx = 2.0 V to 3.6 V – Tx = 3.0 V to 3.6 V Package: Compact QFN-40 (6 mm × 6 mm) Specified Temperature Range: 0°C to +70°C Low-Cost Medical Pulse Oximeter Applications Optical HRM Industrial Photometry Applications DESCRIPTION The AFE4400 is a fully-integrated analog front-end (AFE) that is ideally suited for pulse oximeter applications. The device consists of a low-noise receiver channel with an integrated analog-to-digital converter (ADC), an LED transmit section, and diagnostics for sensor and LED fault detection. The AFE4400 is a very configurable timing controller. This flexibility enables the user to have complete control of the device timing characteristics. To ease clocking requirements and provide a low-jitter clock to the AFE4400, an oscillator is also integrated that functions from an external crystal. The device communicates to an external microcontroller or host processor using an SPI™ interface. The AFE4400 is a complete AFE solution packaged in a single, compact QFN-40 package (6 mm × 6 mm) and is specified over the operating temperature range of 0°C to +70°C. Supply (2.2 V to 3.6 V) AFE4400 RX RED TIA Amb (RED) û ADC IR AFE SPI SPI Interface Amb (IR) Photodiode Diagnostic PD Open or Short Cable Off LED Open or Short LED Driver LED Timing Controller LED Current Control DAC Tx Diagnostic Signals 1 OSC AFE Tx Driver Supply 5-V Supply 32 kHz 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FAMILY AND ORDERING INFORMATION LED DRIVE CURRENT (mA, max) POWER SUPPLY (V) OPERATING TEMPERATURE RANGE PRODUCT PACKAGE-LEAD LED DRIVE CONFIGURATION AFE4400 QFN-40 Bridge, push-pull 50 3 to 3.6 0°C to +70°C Bridge, push-pull 50, 75, 100, 150, and 200 3 to 5.25 –40°C to +85°C AFE4490 QFN-40 ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. VALUE UNIT AVDD to AVSS –0.3 to +7 V DVDD to DGND –0.3 to +7 V AGND to DGND –0.3 to +0.3 V Analog input to AVSS AVSS – 0.3 to AVDD + 0.3 V Digital input to DVDD DVSS – 0.3 to DVDD + 0.3 V Input current to any pin except supply pins Input current (2) ±7 mA Momentary ±50 mA Continuous ±7 mA 0 to +70 °C –60 to +150 °C +125 °C Human body model (HBM) JEDEC standard 22, test method A114-C.01, all pins ±4000 V Charged device model (CDM) JEDEC standard 22, test method C101, all pins ±1500 V Operating temperature range Storage temperature range, Tstg Maximum junction temperature, TJ Electrostatic discharge (ESD) ratings (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing beyond the supply rails must be current-limited to 10 mA or less. THERMAL INFORMATION AFE4400 THERMAL METRIC (1) RHA (QFN) UNITS 40 PINS θJA Junction-to-ambient thermal resistance 35 θJCtop Junction-to-case (top) thermal resistance 31 θJB Junction-to-board thermal resistance 26 ψJT Junction-to-top characterization parameter 0.1 ψJB Junction-to-board characterization parameter n/a θJCbot Junction-to-case (bottom) thermal resistance n/a (1) 2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range, unless otherwise noted. PARAMETER VALUE UNIT SUPPLIES RX_ANA_SUP AFE analog supply 2.0 to 3.6 V RX_DIG_SUP AFE digital supply 2.0 to 3.6 V TX_CTRL_SUP Transmit controller supply 3.0 to 3.6 V (1) (2) H-bridge configuration LED_DRV_SUP Transmit LED driver supply Common anode configuration Difference between LED_DRV_SUP and TX_CTRL_SUP [3.0 or (1.4 + VLED + VCABLE) whichever is greater] to 5.25 , V (1) (2) [3.0 or (1.3 + VLED + VCABLE) whichever is greater] to 5.25 , V –0.3 to +0.3 V 0 to +70 °C –60 to +150 °C TEMPERATURE Specified temperature range Storage temperature range (1) (2) VLED refers to the voltage drop across the external LED connected between the TXP and TXM pins (in H-bridge mode) and from the TXP and TXM pins to LED_DRV_SUP (in the common anode configuration). VCABLE refers to voltage drop across any cable, connector, or any other component in series with the LED. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 3 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS Minimum and maximum specifications are at TA = –20°C to +85°C. Typical specifications are at +25°C. All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and fCLK = 8 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PERFORMANCE (Full-Signal Chain) IIN_FS Full-scale input current RF = 10 kΩ 50 µA RF = 25 kΩ 20 µA RF = 50 kΩ 10 µA RF = 100 kΩ 5 µA RF = 250 kΩ 2 µA RF = 500 kΩ 1 µA RF = 1 MΩ PRF Pulse repetition frequency DCPRF PRF duty cycle IIN_FS Full-scale input current CMRR Common-mode rejection ratio 0.5 61 µA 5000 SPS 25% RF = 10 kΩ 50 µA RF = 1 MΩ 0.5 µA fCM = 50 Hz and 60 Hz, LED1 and LED2 with RSERIES = 1 MΩ, RF = 500 kΩ 80 dB fCM = 50 Hz and 60 Hz, LED1-AMB and LED2-AMB with RSERIES = 1 MΩ, RF = 500 kΩ 100 dB fPS = 50 Hz, 60 Hz at PRF = 200 Hz 100 dB fPS = 50 Hz, 60 Hz at PRF = 600 Hz 106 dB PSRR Power-supply rejection ratio PSRRLED PSRR, transmit LED driver With respect to ripple on LED_DRV_SUP 75 dB PSRRTx PSRR, transmit control With respect to ripple on TX_CTRL_SUP 60 dB PSRR, receiver With respect to ripple on RX_ANA_SUP and RX_DIG_SUP 60 dB Total integrated noise current, input-referred (receiver with transmitter loop back, 0.1-Hz to 5-Hz bandwidth) RF = 100 kΩ, PRF = 625 Hz, duty cycle = 5% 36 pARMS RF = 500 kΩ, PRF = 625 Hz, duty cycle = 5% 13 pARMS Noise-free bits (receiver with transmitter loop back, 0.1-Hz to 5-Hz bandwidth) RF = 100 kΩ, PRF = 625 Hz, duty cycle = 5% 14.3 Bits RF = 500 kΩ, PRF = 625 Hz, duty cycle = 5% 13.5 Bits 1.4 pARMS 5 pARMS PSRRRx NFB RECEIVER FUNCTIONAL BLOCK LEVEL SPECIFICATION RF = 500 kΩ, ambient cancellation enabled, stage 2 gain = 4, PRF = 1300 Hz, LED duty cycle = 25% Total integrated noise current, input referred (receiver alone) over 0.1-Hz to 5-Hz bandwidth RF = 500 kΩ, ambient cancellation enabled, stage 2 gain = 4, PRF = 1300 Hz, LED duty cycle = 5% I-V TRANSIMPEDANCE AMPLIFIER G Gain See the Receiver Channel section for details RF = 10 kΩ to 1 MΩ Gain accuracy ±7% Feedback resistance RF Feedback resistor tolerance RF Feedback capacitance CF Feedback capacitor tolerance CF 10k, 25k, 50k, 100k, 250k, 500k, and 1M ±20% pF ±20% Common-mode voltage on input pins Set internally External differential input capacitance Includes equivalent capacitance of photodiode, cables, EMI filter, and so forth Shield output voltage, VCM With a 1-kΩ series resistor and a 10-nF decoupling capacitor to ground Submit Documentation Feedback Ω 5, 10, 25, 50, 100, and 250 Full-scale differential output voltage 4 V/µA 1 V 0.9 V 10 1000 0.9 pF V Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications are at TA = –20°C to +85°C. Typical specifications are at +25°C. All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and fCLK = 8 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AMBIENT CANCELLATION STAGE Gain 1, 1.414, 2, 2.828, and 4 Current DAC range 0 Current DAC step size V/V 10 µA 1 µA LOW-PASS FILTER Low-pass corner frequency Pass-band attenuation, 2 Hz to 10 Hz 3-dB attenuation 500 Hz Duty cycle = 25% 0.004 dB Duty cycle = 10% 0.041 dB ANALOG-TO-DIGITAL CONVERTER Resolution Sample rate 22 See the ADC Operation and Averaging Module section 4 × PRF ADC full-scale voltage ADC conversion time Bits SPS ±1.2 See the ADC Operation and Averaging Module section ADC reset time 50 V PRF / 4 µs 2 tCLK TRANSMITTER Selectable, 0 to 50 (see the LEDCNTRL: LED Control Register for details) Output current range LED current DAC error ±10% Output current resolution Transmitter noise dynamic range, over 0.1-Hz to 5-Hz bandwidth 8 Bits At 5-mA output current 95 dB At 25-mA output current 95 dB 95 dB At 50-mA output current Voltage on TXP (or TXM) pin when low-side switch connected to TXP (or TXM) turns on At 50-mA output current, H-bridge LED driver configuration 1.4 + (voltage drop across LED, cable, and so forth) to 5.25 V At 50-mA output current, common anode LED driver configuration 1.3 + (voltage drop across LED, cable, and so forth) to 5.25 V Minimum sample time of LED1 and LED2 pulses LED current DAC leakage current mA 50 µs LED_ON = 0 1 µA LED_ON = 1 50 µA LED current DAC linearity Percent of full-scale current 0.5% Output current settling time (with resistive load) From zero current to 50 mA 7 µs From 50 mA to zero current 7 µs 16 4k cycles of 4-MHz clock DIAGNOSTICS Duration of diagnostics state machine Start of diagnostics after the DIAG_EN register bit is set. End of diagnostic is indicated by DIAG_END going high. Open fault resistance > 100 kΩ Short fault resistance < 10 kΩ INTERNAL OSCILLATOR fCLKOUT CLKOUT frequency With an 8-MHz crystal connected to the XIN, XOUT pins CLKOUT duty cycle Crystal oscillator start-up time 4 MHz 50% With an 8-MHz crystal connected to the XIN, XOUT pins 200 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 µs 5 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications are at TA = –20°C to +85°C. Typical specifications are at +25°C. All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and fCLK = 8 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EXTERNAL CLOCK Maximum allowable external clock jitter External clock input frequency External clock input voltage 50 ±10% 8 ps MHz Voltage input high (VIH) 0.75 × RX_DIG_SUP V Voltage input low (VIL) 0.25 × RX_DIG_SUP V TIMING Wake-up time from complete power-down 1000 ms Wake-up time from Rx power-down 100 µs Wake-up time from Tx power-down 1000 ms tRESET Active low RESET pulse duration 1 ms tDIAGEND DIAG_END pulse duration at the completion of diagnostics 4 CLKOUT cycles tADCRDY ADC_RDY pulse duration 1 CLKOUT cycle DIGITAL SIGNAL CHARACTERISTICS VIH Logic high input voltage AFE_PDN, SCLK, SPISIMO, SPISTE, RESET 0.8 DVDD > 1.3 DVDD + 0.1 V VIL Logic low input voltage AFE_PDN, SCLK, SPISIMO, SPISTE, RESET –0.1 < 0.4 0.2 DVDD V IIN Logic input current 0 V < VDigitalInput < DVDD –10 10 µA VOH Logic high output voltage DIAG_END, LED_ALM, PD_ALM, SPISOMI, ADC_RDY, CLKOUT VOL Logic low output voltage DIAG_END, LED_ALM, PD_ALM, SPISOMI, ADC_RDY, CLKOUT > (RX_DIG_SUP – 0.9 DVDD 0.2 V) < 0.4 0.1 DVDD V V SUPPLY CURRENT Receiver analog supply current RX_ANA_SUP = 3.0 V, with 8-MHz clock running, Rx stage 2 disabled 0.6 mA RX_ANA_SUP = 3.0 V, with 8-MHz clock running, Rx stage 2 enabled 0.7 mA 0.27 mA 55 µA 15 µA Receiver current only (RX_ANA_SUP) 3 µA Receiver current only (RX_DIG_SUP) 3 µA Transmitter current only (LED_DRV_SUP) 1 µA Transmitter current only (TX_CTRL_SUP) 1 µA Receiver current only (RX_ANA_SUP) 220 µA Receiver current only (RX_DIG_SUP) 220 µA Transmitter current only (LED_DRV_SUP) 2 µA Transmitter current only (TX_CTRL_SUP) 2 µA Receiver digital supply current RX_DIG_SUP = 3.0 V LED_DRV _SUP LED driver supply current With zero LED current setting TX_CTRL _SUP Transmitter control supply current Complete power-down (using AFE_PDN pin) Power-down Rx alone Power-down Tx alone 6 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications are at TA = –20°C to +85°C. Typical specifications are at +25°C. All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and fCLK = 8 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER DISSIPATION 2.84 mW 0.1 mW 1 µA TX_CTRL_SUP 1 µA RX_ANA_SUP 5 µA RX_DIG_SUP 0.1 µA 1 µA TX_CTRL_SUP 1 µA RX_ANA_SUP 15 µA RX_DIG_SUP 20 µA 50 µA TX_CTRL_SUP 15 µA RX_ANA_SUP 220 µA RX_DIG_SUP 220 µA 2 µA Quiescent power dissipation LED_DRV_SUP Power-down with the AFE_PDN pin LED_DRV_SUP Power-down with the PDNAFE register bit LED_DRV_SUP Power-down Rx LED_DRV_SUP Power-down Tx LED_DRV_SUP current value. Does not include LED current. LED_DRV_SUP current value. Does not include LED current. LED_DRV_SUP current value. Does not include LED current. LED_DRV_SUP current value. Does not include LED current. 2 µA RX_ANA_SUP 600 µA RX_DIG_SUP 230 µA 55 µA TX_CTRL_SUP 15 µA RX_ANA_SUP 600 µA RX_DIG_SUP 230 µA 55 µA TX_CTRL_SUP 15 µA RX_ANA_SUP 700 µA RX_DIG_SUP 270 µA LED_DRV_SUP With stage 2 mode enabled and 8-MHz clock running Power-down TX_CTRL_SUP LED_DRV_SUP After reset, with 8-MHz clock running Normal operation (excluding LEDs) LED_DRV_SUP current value. Does not include LED current. LED_DRV_SUP current value. Does not include LED current. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 7 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com PARAMETRIC MEASUREMENT INFORMATION SERIAL INTERFACE TIMING tCLK XIN tSTECLK SPI STE tSPICLK tCLKSTEH 31 SCLK 7 23 0 tCLKSTEL tSIMOHD tSIMOSU SPI SIMO A7 A6 A1 A0 tSOMIHD tSOMIPD tSOMIPD D23 SPI SOMI }v[š D22 D17 D16 D7 D6 D1 D0 Œ , can be high or low. (1) The SPI_READ register bit must be enabled before attempting a register read. (2) Specify the register address whose contents must be read back on A[7:0]. (3) The AFE outputs the contents of the specified register on the SOMI pin. Figure 1. Serial Interface Timing Diagram, Read Operation (1)(2)(3) 8 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 PARAMETRIC MEASUREMENT INFORMATION (continued) tSTECLK SPI STE 31 SCLK 23 0 tSIMOHD tSIMOSU A7 SPI SIMO A6 A1 A0 D23 D22 D1 D0 Figure 2. Serial Interface Timing Diagram, Write Operation Table 1. Timing Requirements for Figure 1 and Figure 2 PARAMETER tCLK Clock frequency on XIN pin tSCLK Serial shift clock period tSTECLK tCLKSTEH,L MIN TYP 8 MAX UNIT MHz 62.5 ns STE low to SCLK rising edge, setup time 10 ns SCLK transition to SPI STE high or low 10 ns tSIMOSU SIMO data to SCLK rising edge, setup time 10 ns tSIMOHD Valid SIMO data after SCLK rising edge, hold time 10 ns tSOMIPD SCLK falling edge to valid SOMI, setup time 17 ns tSOMIHD SCLK rising edge to invalid data, hold time 0.5 tSCLK Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 9 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com PIN CONFIGURATION RX_ANA_GND RX_ANA_SUP XIN XOUT RX_ANA_GND DNC DNC RX_ANA_SUP RX_DIG_GND RX_DIG_SUP RHA PACKAGE QFN-40 (Top View) 40 39 38 37 36 35 34 33 32 31 ADC_RDY VCM 4 27 SPISTE (1) 5 26 SPISIMO DNC 6 25 SPISOMI BG 7 24 SCLK VSS 8 23 PD_ALM TX_REF 9 22 LED_ALM DNC 10 21 DIAG_END DNC 11 12 13 14 15 16 17 18 19 20 AFE_PDN 28 RX_DIG_GND 3 LED_DRV_SUP RESET RX_ANA_GND LED_DRV_SUP 29 LED_DRV_GND 2 TXP INP TXN CLKOUT LED_DRV_GND 30 LED_DRV_GND 1 TX_CTRL_SUP INN (1) DNC = Do not connect. 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 PIN DESCRIPTIONS NAME (1) NO. FUNCTION DESCRIPTION ADC_RDY 28 Digital Output signal that indicates ADC conversion completion. Can be connected to the interrupt input pin of an external microcontroller. AFE_PDN 20 Digital AFE-only power-down input; active low. Can be connected to the port pin of an external microcontroller. BG 7 Reference CLKOUT 30 Digital Buffered 4-MHz output clock output. Can be connected to the clock input pin of an external microcontroller. DIAG_END 21 Digital Output signal that indicates completion of diagnostics. Can be connected to the port pin of an external microcontroller. DNC (1) 5, 6, 10, 34, 35 — Do not connect these pins. Leave as open circuit. INN 1 Analog Receiver input pin. Connect to photodiode anode. INP 2 Analog Receiver input pin. Connect to photodiode cathode. LED_DRV_GND 12, 13, 16 Supply LED driver ground pin, H-bridge. Connect to common board ground. LED_DRV_SUP 17, 18 Supply LED driver supply pin, H-bridge. Connect to an external power supply capable of supplying the large LED current, which is drawn by this supply pin. LED_ALM 22 Digital Output signal that indicates an LED cable fault. Can be connected to the port pin of an external microcontroller. PD_ALM 23 Digital Output signal that indicates a PD sensor or cable fault. Can be connected to the port pin of an external microcontroller. RESET 29 Digital AFE-only reset input, active low. Can be connected to the port pin of an external microcontroller RX_ANA_GND 3, 36, 40 Supply Rx analog ground pin. Connect to common board ground. RX_ANA_SUP 33, 39 Supply Rx analog supply pin; 0.1-µF decoupling capacitor to ground RX_DIG_GND 19, 32 Supply Rx digital ground pin. Connect to common board ground. RX_DIG_SUP 31 Supply Rx digital supply pin; 0.1-µF decoupling capacitor to ground SCLK 24 SPI SPI clock pin SPISIMO 26 SPI SPI serial in master out SPISOMI 25 SPI SPI serial out master in SPISTE 27 SPI SPI serial interface enable TX_CTRL_SUP 11 Supply TX_REF 9 Reference TXN 14 Analog LED driver out B, H-bridge output. Connect to LED. TXP 15 Analog LED driver out B, H-bridge output. Connect to LED. VCM 4 Reference VSS 8 Supply Substrate ground. Connect to common board ground. XOUT 37 Digital Crystal oscillator pins. Connect an external 8-MHz crystal between these pins with the correct load capacitor (as specified by vendor) to ground. XIN 38 Digital Crystal oscillator pins. Connect an external 8-MHz crystal between these pins with the correct load capacitor (as specified by vendor) to ground. Decoupling capacitor for internal band-gap voltage to ground. (2.2-µF decoupling capacitor to ground) Transmit control supply pin (0.1-µF decoupling capacitor to ground) Tx reference voltage Input common-mode voltage output. Connect a series resistor (1 kΩ) and a decoupling capacitor (10 nF) to ground. The voltage across the capacitor can be used to shield (guard) the INP, INM traces. Leave pins as open circuit. Do not connect. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 11 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and fCLK = 8 MHz, unless otherwise noted. 900 15.00 Stage 2 & Amb Cancel Disabled PRF = 600Hz TX_CTRL_SUP Current ( A) RX Analog Current ( A) Stage 2 & Amb Cancel Enabled 800 700 600 500 RX_ANA_SUP = RX_DIG_SUP PRF = 600Hz Stage 2 Gain = 4 400 14.95 14.90 14.85 14.80 14.75 14.70 14.65 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 RX Supply Voltage (V) 2.5 600 Input Referred Noise Current, pA rms in 5Hz Bandwidth LED_DRV_SUP Current ( A) 47.2 47.0 46.8 46.6 46.4 500 400 C002 200 For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). Noise is calculated in 5Hz B/W. 100 0 2.5 3.0 3.5 4.0 4.5 0 5.0 LED_DRV_SUP Voltage (V) 500 400 700 300 200 For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). Noise is calculated in 5Hz B/W. 100 0 0 10 20 30 40 Pleth Current ( A) 40 50 C004 50 Duty cycle 1% Duty cycle 5% Duty cycle 10% Duty cycle 15% Duty cycle 20% Duty cycle 25% 600 500 400 300 200 For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA.) Noise is calculated in 5Hz band. 100 0 0 10 20 30 40 Pleth Current ( A) C005 Figure 7. INPUT-REFERRED NOISE CURRENT vs PLETH CURRENT (PRF = 300 Hz) 30 Figure 6. INPUT-REFERRED NOISE CURRENT vs PLETH CURRENT (PRF = 100 Hz) Duty Cycle = 1% Duty Cycle = 5% Duty Cycle = 10% Duty Cycle = 15% Duty Cycle = 20% Duty Cycle = 25% 600 20 Pleth Current ( A) Input Referred Noise Current, pA rms in 5Hz Bandwidth 700 10 C003 Figure 5. LED_DRV_SUP CURRENT vs LED_DRV_SUP VOLTAGE Input Referred Noise Current, pA rms in 5Hz Bandwidth 5.0 300 With LED Current = 0mA 46.0 12 4.5 Duty Cycle = 1% Duty Cycle = 5% Duty Cycle = 10% Duty Cycle = 15% Duty Cycle = 20% Duty Cycle = 25% 47.8 47.4 4.0 Figure 4. TX_CTRL_SUP CURRENT vs TX_CTRL_SUP VOLTAGE 48.0 47.6 3.5 TX_CTRL_SUP Voltage (V) Figure 3. TOTAL Rx CURRENT vs Rx SUPPLY VOLTAGE 46.2 3.0 C001 50 C006 Figure 8. INPUT-REFERRED NOISE CURRENT vs PLETH CURRENT (PRF = 600 Hz) Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and fCLK = 8 MHz, unless otherwise noted. 1200 Duty Cycle = 1% Duty Cycle = 5% Duty Cycle = 10% Duty Cycle = 15% Duty Cycle = 20% Duty Cycle = 25% 700 600 500 400 300 200 For each RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). Noise is calculated in 5Hz band. 100 0 0 10 20 30 40 Pleth Current ( A) Input Referred Noise Current, pA rms in 5Hz Bandwidth Input Referred Noise Current, pA rms in 5Hz Bandwidth 800 1000 800 400 200 0 50 0 1200 1000 800 16 For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). Noise is calculated in 5Hz band. 400 200 0 30 10 20 30 40 13 Duty cycle 1% Duty cycle 5% Duty cycle 10% Duty cycle 15% Duty cycle 20% Duty cycle 25% 12 11 0 14 13 Duty cycle 1% Duty cycle 5% Duty cycle 10% Duty cycle 15% Duty cycle 20% Duty cycle 25% 10 20 30 Pleth Current ( A) 40 20 30 C010 15 14 13 Duty cycle 1% Duty cycle 5% Duty cycle 10% Duty cycle 15% Duty cycle 20% Duty cycle 25% 12 11 0 10 20 30 40 Pleth Current ( A) C011 Figure 13. NOISE-FREE BITS vs PLETH CURRENT (PRF = 300 Hz) 50 For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise. 10 50 40 Figure 12. NOISE-FREE BITS vs PLETH CURRENT (PRF = 100 Hz) Noise-Free Bits in 5Hz Bandwidth 15 0 10 Pleth Current ( A) 16 For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low pleth currents (0.125uA, 0.25uA & 0.5uA.) RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise. 10 C008 14 C009 Figure 11. INPUT-REFERRED NOISE CURRENT vs PLETH CURRENT (PRF = 5000 Hz) 11 50 15 50 Pleth Current ( A) 12 40 For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise. 10 0 Noise-Free Bits in 5Hz Bandwidth 20 Pleth Current ( A) Figure 10. INPUT-REFERRED NOISE CURRENT vs PLETH CURRENT (PRF = 2500 Hz) 600 16 10 C007 Noise-Free Bits in 5Hz Bandwidth Input Referred Noise Current, pA rms in 5Hz Bandwidth Duty cycle 1% Duty cycle 5% Duty cycle 10% Duty cycle 15% Duty cycle 20% Duty cycle 25% For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). Noise is calculated in 5Hz band. 600 Figure 9. INPUT-REFERRED NOISE CURRENT vs PLETH CURRENT (PRF = 1200 Hz) 1400 Duty cycle 1% Duty cycle 5% Duty cycle 10% Duty cycle 15% Duty cycle 20% Duty cycle 25% 50 C012 Figure 14. NOISE-FREE BITS vs PLETH CURRENT (PRF = 600 Hz) Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 13 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and fCLK = 8 MHz, unless otherwise noted. 15 16 For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise. Noise-Free Bits in 5Hz Bandwidth Noise-Free Bits in 5Hz Bandwidth 16 14 13 Duty Cycle = 1% Duty Cycle = 5% Duty Cycle = 10% Duty Cycle = 15% Duty Cycle = 20% Duty Cycle = 25% 12 11 10 0 10 20 30 40 14 13 12 10 0 110 TX Dynamic Range (dB) 15 13 Duty cycle 1% Duty cycle 5% Duty cycle 10% Duty cycle 15% Duty cycle 20% Duty cycle 25% 11 10 0 10 20 30 40 Pleth Current, uA 50 C014 90 80 70 TX_CTRL_SUP = LED_DRV_SUP = 3V TX Vref = 0.5V 60 50 0 50 20 300 TX Current (mA) 0 ±100 ±200 ±300 80 100 C016 Expected + 1% Actual DAC Current Expected - 1% 50 100 60 Figure 18. TRANSMITTER DYNAMIC RANGE (5-Hz BW) 400 200 40 % of Full-Scale LED Current C015 500 DAC Current Step Error (mA) 40 100 Figure 17. NOISE-FREE BITS vs PLETH CURRENT (PRF = 5000 Hz) 40 30 20 10 ±400 TX_REF = 0.5V TX Reference Voltage = 0.5V 0 ±500 0 50 100 150 TX LED DAC Setting 200 250 0 50 100 150 200 250 TX LED DAC Setting C021 Figure 19. TRANSMITTER DAC CURRENT STEP ERROR (50 mA, Max) 14 30 Figure 16. NOISE-FREE BITS vs PLETH CURRENT (PRF = 2500 Hz) 120 14 20 Pleth Current, uA 16 For each setting RF adjusted for Full-Scale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise. 10 C013 Figure 15. NOISE-FREE BITS vs PLETH CURRENT (PRF = 1200 Hz) 12 Duty Cycle = 1% Duty Cycle = 5% Duty Cycle = 10% Duty Cycle = 15% Duty Cycle = 20% Duty Cycle = 25% For each setting RF adjusted for FullScale Output. Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA). RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise. 11 50 Pleth Current ( A) Noise-Free Bits in 5Hz Bandwidth 15 C022 Figure 20. TRANSMITTER CURRENT LINEARITY (50-mA Range) Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and fCLK = 8 MHz, unless otherwise noted. 500 400 TX_RANGE = 50mA, Data from 2326 devices 300 200 100 0 300 200 100 0 4.5 4.6 4.6 4.7 4.7 4.8 4.8 4.9 4.9 5.0 5.0 5.1 5.1 5.2 5.2 5.3 5.3 5.4 5.4 5.5 5.5 Number of Occurences 400 1.80 1.83 1.85 1.88 1.90 1.93 1.95 1.98 2.00 2.03 2.05 2.08 2.10 2.13 2.15 2.18 2.20 2.23 2.25 2.28 2.30 LED Current (mA) LED Current (mA) C023 C024 Figure 21. LED CURRENT WITH Tx DAC SETTING = 10 (2 mA) Figure 22. LED CURRENT WITH Tx DAC SETTING = 25 (5 mA) 400 400 LED Current (mA) 22.0 21.8 21.5 21.3 21.0 20.8 20.5 20.3 20.0 19.8 19.3 0 19.0 0 100 18.8 100 200 18.5 200 300 18.3 300 18.0 Number of Occurences TX_RANGE = 50mA, Data from 7737 devices 9.0 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 10.0 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11.0 Number of Occurences TX_RANGE = 50mA, Data from 2326 devices 19.5 Number of Occurences TX_RANGE = 50mA, Data from 2326 devices LED Current (mA) C025 C026 Figure 23. LED CURRENT WITH Tx DAC SETTING = 51 (10 mA) Figure 24. LED CURRENT WITH Tx DAC SETTING = 102 (20 mA) 400 800 700 RX Supply Current, uA Number of Occurences TX_RANGE = 50mA, Data from 7737 devices 300 200 100 600 500 RX_ANA_SUP = 2V (STG2=DIS) RX_ANA_SUP = 2V (STG2=EN) RX_DIG_SUP=2V RX_ANA_SUP = 3.3V (STG2=DIS) RX_ANA_SUP = 3.3V (STG2=EN) RX_DIG_SUP=3.3V 400 300 0 45.0 45.5 46.0 46.5 47.0 47.5 48.0 48.5 49.0 49.5 50.0 50.5 51.0 51.5 52.0 52.5 53.0 53.5 54.0 54.5 55.0 200 100 100 300 500 700 900 1100 PRF, Hz LED Current (mA) C028 C027 Figure 25. LED CURRENT WITH Tx DAC SETTING = 255 (50 mA) Figure 26. RECEIVER SUPPLIES vs PRF Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 15 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and fCLK = 8 MHz, unless otherwise noted. 100.00 80.00 Supply Current, uA TX Supply Current, uA TX_CTRL_SUP = LED_DRV_SUP = 3V TO 3.6V 60.00 40.00 TX_CTRL_SUP LED_DRV_SUP 20.00 0.00 0.50 0.75 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 0 1.00 TX_VREF, V RX_ANA_SUP (STG2DIS) RX_ANA_SUP (STG2EN) RX_DIG_SUP TX_CTRL_SUP LED_DRV_SUP 10 20 30 40 50 60 Temperature, C C029 Figure 27. TRANSMITTER SUPPLIES vs TX_REF 70 C030 Figure 28. POWER SUPPLIES vs TEMPERATURE PRF = 1200 Hz, Duty cycle = 10% 1) RF = 100K, Stage 2 & ambient cancellation disabled 2) RF = 500K, Stage 2 & ambient cancellation enabled with stage 2 gain = 4 STG2=DIS, 5Hz BW (Note 2) STG2=EN, 5Hz BW (Note 3) 80 15 STG2=DIS, 20Hz BW (Note 2) STG2=EN, 20Hz BW (Note 3) Noise Free Bits Input referred noise current, pA rms 100 60 40 STG2=DIS, 5Hz BW (Note 2) PRF = 1200 Hz, Duty cycle = 10% 1) RF = 100K, Stage 2 & ambient cancellation disabled 2) RF = 500K, Stage 2 & ambient cancellation enabled with stage 2 gain = 4 20 STG2=EN, 5Hz BW (Note 3) STG2=DIS, 20Hz BW (Note 2) STG2=EN, 20Hz BW (Note 3) 10 0 0 10 20 30 40 50 Temperature, C 60 0 70 10 20 30 40 50 60 Temperature, C C031 Figure 29. INPUT-REFERRED NOISE vs TEMPERATURE 70 C032 Figure 30. NOISE-FREE BITS vs TEMPERATURE 0 Attenuation, dB ±10 ±20 ±30 ±40 5% Duty cycle 25% Duty cycle ±50 1 10 100 Input signal frequency, Hz C033 Figure 31. FILTER RESPONSE vs DUTY CYCLE 16 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 OVERVIEW BG RXOUTN RXOUTP RX_DIG_SUP RX_ANA_SUP RX_ANA_SUP TX_CTRL_SUP LED_DRV_SUP LED_DRV_SUP The AFE4400 is a complete analog front-end (AFE) solution targeted for pulse oximeter applications. The device consists of a low-noise receiver channel, an LED transmit section, and diagnostics for sensor and LED fault detection. To ease clocking requirements and provide the low-jitter clock to the AFE, an oscillator is also integrated that functions from an external crystal. The device communicates to an external microcontroller or host processor using an SPI interface. Figure 32 shows a detailed block diagram for the AFE4400. The blocks are described in more detail in the following sections. Device Reference SPISTE RF SPISIMO SPI + CPD INP + + Stage 2 Gain TIA Filter SPISOMI SCLK Digital Filter 4G ADC Buffer SPI Interface CF INN RF Photodiode CF Control VCM Timing Controller AFE_PDN ADC_RDY CF RESET LED TXN LED Driver LED Current Control DAC TXP DIAG_END DNC(1) DNC(1) DNC(1) Diagnostic Signals Diagnostics LED_ALM PD_ALM/ADC Reset VSS XOUT XIN CLKOUT RX_DIG_GND RX_DIG_GND RX_ANA_GND RX_ANA_GND RX_ANA_GND LED_DRV_GND LED_DRV_GND LED_DRV_GND TX_REF OSC 8 MHz Figure 32. Detailed Block Diagram Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 17 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com RECEIVER CHANNEL This section describes the functionality of the receiver channel. Receiver Front-End The receiver consists of a differential current-to-voltage (I-V) transimpedance amplifier that converts the input photodiode current into an appropriate voltage, as shown in Figure 33. The feedback resistor of the amplifier (RF) is programmable to support a wide range of photodiode currents. Available RF values include: 1 MΩ, 500 kΩ, 250 kΩ, 100 kΩ, 50 kΩ, 25 kΩ, and 10 kΩ. Rx SLED2 CONVLED2 LED2 CF RF RF ADC + CPD +Stage 2 TIA Amb SLED2_amb CONVLED2_amb Gain Buffer SLED1 ADC Output Rate PRF Sa/sec + û ADC CONVLED1 LED1 RF RF CF ADC Convert Ambient DAC I-V Amplifier Amb cancellation DAC Amb SLED1_amb ADC Clock CONVLED1_amb Filter Buffer ADC Ambient-cancellation current can be set digitally using SPI interface. Figure 33. Receiver Front-End The RF amplifier and the feedback capacitor (CF) form a low-pass filter for the input signal current. Always ensure that the low-pass filter has sufficiently high bandwidth (as shown by Equation 1) because the input current consists of pulses. For this reason, the feedback capacitor is also programmable. Available CF values include: 5 pF, 10 pF, 25 pF, 50 pF, 100 pF, and 250 pF. Any combination of these capacitors can also be used. Rx Sample Time R F ´ CF £ 10 (1) The output voltage of the I-V amplifier includes the pleth component (the desired signal) and a component resulting from the ambient light leakage; see . The I-V amplifier is followed by the second stage, which consists of a current digital-to-analog converter (DAC) that sources the cancellation current and an amplifier that gains up the pleth component alone. The amplifier has five programmable gain settings: 1, 1.414, 2, 2.828, and 4. The gained-up pleth signal is then low-pass filtered (500-Hz bandwidth) and buffered before driving a 22-bit ADC. The current DAC has a cancellation current range of 10 µA with 10 steps (1 µA each). The DAC value can be digitally specified with the SPI interface. The output of the ambient cancellation amplifier is separated into LED2 and LED1 channels. When LED2 is on, the amplifier output is filtered and sampled on capacitor CR. Similarly, the LED1 signal is sampled on the CLED1 capacitor when LED1 is ON. In between the LED2 and LED1 pulses, the idle amplifier output is sampled to estimate the ambient signal on capacitors CLED2_amb and CLED1_amb. The sampling duration is termed the Rx sample time and is programmable for each signal, independently. The sampling can start after the I-V amplifier output is stable (to account for LED and cable settling times). The Rx sample time is used for all dynamic range calculations; the minimum time supported is 50 µs. 18 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 A single, 22-bit ADC converts the sampled LED2, LED1, and ambient signals sequentially. Each conversion takes 25% of the pulse repetition period and provides a single digital code at the ADC output. As discussed in the Receiver Timing section, the conversions are staggered so that the LED2 conversion starts after the end of the LED2 sample phase, and so on. This configuration also means that the Rx sample time for each signal is no greater than 25% of the pulse repetition period. Note that four data streams are available at the ADC output (LED2, LED1, ambient LED2, and ambient LED1) at the same rate as the pulse repetition frequency. The ADC is followed by a digital ambient subtraction block that additionally outputs the (LED2 – ambient LED2) and (LED1 – ambient LED1) data values. Ambient Cancellation Scheme The receiver provides digital samples corresponding to ambient duration. The host processor (external to the AFE) can use these ambient values to estimate the amount of ambient light leakage. The processor must then set the value of the ambient cancellation DAC using the SPI, as shown in Figure 34. Device Host Processor LED2 Data ADC Output Rate PRF Samples per Second Ambient (LED2) Data Front End (LED2 ± Ambient) Data SPI Interface ADC Rx Digital SPI Block LED1 Data Ambient Estimation Block Ambient information is available in the host processor. The processor can: * Read ambient data Ambient (LED1) Data * Estimate ambient value to be cancelled * Set the value to be used by the ambient cancellation DAC using the SPI of AFE (LED1 ± Ambient) Data Digital Control for Ambient-Cancellation DAC Figure 34. Ambient Cancellation Loop (Closed by the Host Processor) Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 19 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com Using the set value, the ambient cancellation stage subtracts the ambient component and gains up only the pleth component of the received signal; see Figure 35. The amplifier gain is programmable to 1, 1.5, 2, 3, and 4. ICANCEL Cf Rg Rf IPLETH + IAMB Ri Rx VDIFF Ri Rf Rg ICANCEL Cf Value of ICANCEL set using the SPI interface. Figure 35. Front-End (I-V Amplifier and Cancellation Stage) The differential output of the second stage is VDIFF, as given by Equation 2: RF RF + IAMB ´ - ICANCEL ´ RG VDIFF = 2 ´ IPLETH ´ RI RI where: • • • • 20 RI = 100 kΩ, IPLETH = photodiode current pleth component, IAMB = photodiode current ambient component, and ICANCEL = the cancellation current DAC value (as estimated by the host processor). Submit Documentation Feedback (2) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 Receiver Control Signals LED2 sample phase (SLED2): When this signal is high, the amplifier output corresponds to the LED2 on-time. The amplifier output is filtered and sampled into capacitor CLED2. To avoid settling effects resulting from the LED or cable, program SLED2 to start after the LED turns on. This settling delay is programmable. Ambient sample phase (SLED2_amb): When this signal is high, the amplifier output corresponds to the LED2 offtime and can be used to estimate the ambient signal (for the LED2 phase). The amplifier output is filtered and sampled into capacitor CLED2_amb. LED1 sample phase (SLED1): When this signal is high, the amplifier output corresponds to the LED1 on-time. The amplifier output is filtered and sampled into capacitor CLED1. To avoid settling effects resulting from the LED or cable, program SLED1 to start after the LED turns on. This settling delay is programmable. Ambient sample phase (SLED1_amb): When this signal is high, the amplifier output corresponds to the LED1 offtime and can be used to estimate the ambient signal (for the LED1 phase). The amplifier output is filtered and sampled into capacitor CLED1_amb. LED2 convert phase (CONVLED2): When this signal is high, the voltage sampled on CLED2 is buffered and applied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. At the end of the conversion, the ADC provides a single digital code corresponding to the LED2 sample. Ambient convert phases (CONVLED2_amb, CONVLED1_amb): When this signal is high, the voltage sampled on CLED2_amb (or CLED1_amb) is buffered and applied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. At the end of the conversion, the ADC provides a single digital code corresponding to the ambient sample. LED1 convert phase (CONVLED1): When this signal is high, the voltage sampled on CLED1 is buffered and applied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. At the end of the conversion, the ADC provides a single digital code corresponding to the LED1 sample. Receiver Timing See Figure 36 for a timing diagram detailing the control signals related to the LED on-time, Rx sample time, and the ADC conversion times for each channel. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 21 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com N+1 N+2 N+1 Plethysmograph Signal N N Photodiode Current Or I-V Output Ambient Level (Dark Level) SR, Sample RED SR_amb, Sample Ambient (RED Phase) CONVR, RED ADC Converts (RED ± Ambient) SIR, Sample IR SIR_amb, Sample Ambient (IR Phase) CONVIR, IR ADC Converts (IR ± Ambient) ADCLKR, Red ADC Sample Clock ADCLKIR, IR ADC Sample Clock RED ADC Output Data IR ADC Output Data RED RED N N+1 IR IR N-1 N NOTE: Relationship to the AFE4400 EVM is: LED1 = IR and LED2 = RED. Figure 36. Rx Timing Diagram 22 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 CLOCKING AND TIMING SIGNAL GENERATION The crystal oscillator generates a master clock signal using an external 8-MHz crystal. A divide-by-2 block converts the 8-MHz clock to 4 MHz, which is used by the AFE to operate the timer modules, ADC, and diagnostics. The 4-MHz clock is buffered and output from the AFE in order to clock an external microcontroller. The clocking functionality is shown in Figure 37. Timer Module Divideby-2 ADC Diagnostics Module Oscillator XIN XOUT CLKOUT 4 MHz 8-MHz Crystal Figure 37. AFE Clocking TIMER MODULE See Figure 38 for a timing diagram detailing the various timing edges that are programmable using the timer module. The rising and falling edge positions of 11 signals can be controlled. The module uses a single 16-bit counter (running off of the 4-MHz clock) to set the time-base. All timing signals are set with reference to the pulse repetition period (PRP). Therefore, a dedicated compare register compares the 16-bit counter value with the reference value specified in the PRF register. Every time that the 16-bit counter value is equal to the reference value in the PRF register, the counter is reset to '0'. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 23 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com LED2 (RED LED) On Signal tLED LED on-time d 0.25 T. LED1 (IR LED) On Signal Rx sample time = tLED ± settle time. SLED2_amb, Sample Ambient [LED2 (RED) Phase] SLED1, Sample LED1 (IR) SLED1_amb, Sample Ambient [LED1 (IR) Phase] SLED2, Sample LED2 (RED) CONVLED2, Convert LED2 (RED) Sample CONVLED2_amb, Convert Ambient Sample [LED2 (RED) Phase] CONVLED1, Convert LED1 (IR) Sample CONVLED1_amb, Convert Ambient Sample [LED1 (IR) Phase] ADC Conversion ADC Reset 1.0 T 0.75 T 0.50 T 0.25 T 0T ADC_RDY Pin Pulse Repetition Period T = 1 / PRF NOTE: Programmable edges are shown in blue and red. Figure 38. AFE Control Signals 24 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 For the 11 signals in Figure 36, the start and stop edge positions are programmable with respect to the PRF period. Each signal uses a separate timer compare module that compares the counter value with preprogrammed reference values for the start and stop edges. All reference values can be set using the SPI interface. When the counter value equals the start reference value, the output signal is set. When the counter value equals the stop reference value, the output signal is reset. Figure 39 shows a diagram of the timer compare register. With a 4-MHz clock, the edge placement resolution is 0.25 µs. The ADC conversion signal requires four pulses in each PRF clock period. The 11th timer compare register uses four sets of start and stop registers to control the ADC conversion signal. Set Output Signal Reset START STOP Start Reference Register Counter Input Stop Reference Register Enable Timer Compare Register Figure 39. Compare Register Enable Reset The ADC conversion signal requires four pulses in each PRF clock period. Timer compare register 11 uses four sets of start and stop registers to control the ADC conversion signal, as shown in Figure 40. Reset CLKIN 16-Bit Counter Reset Counter Enable RED LED IR LED SR Sample RED SIR Sample IR SR_amb, Sample Ambient (red phase) SIR_amb, Sample Ambient (IR phase) S Start R Stop S Start R Stop S Start R Stop S Start R Stop S Start R Stop S Start R Stop Timer Compare 16-Bit Register 1 Timer Compare 16-Bit Register 2 Timer Compare 16-Bit Register 3 Timer Compare 16-Bit Register 4 Timer Compare 16-Bit Register 5 Timer Compare 16-Bit Register 6 En En En En En En En En En En PRF Pulse Timer Compare 16-Bit PRF Register Timer Compare 16-Bit Register 7 Start S Stop R Timer Compare 16-Bit Register 8 Start S Stop R Timer Compare 16-Bit Register 9 Start S Stop R Timer Compare 16-Bit Register 10 Start S Stop R CONVR, Convert RED Sample CONVIR, Convert IR Sample CONVIR_amb, Convert Ambient Sample (IR Phase) CONVR_amb, Convert Ambient Sample (RED Phase) START-A STOP-A En START-B STOP-B Timer Compare 16-Bit Register 11 START-C STOP-D En ADC Conversion START-D STOP-D Timer Module Figure 40. Timer Module Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 25 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com Using the Timer Module The timer module registers can be used to program the start and end instants in units of 4-MHz clock cycles. These timing instants and the corresponding registers are listed in Table 2. Note that the device does not restrict the values in these registers; thus, the start and end edges can be positioned anywhere within the pulse repetition period. Care must be taken by the user to program suitable values in these registers to avoid overlapping the signals and to make sure none of the edges exceed the value programmed in the PRP register. Writing the same value in the start and end registers results in a pulse duration of one clock cycle. The following steps describe the timer sequencing configuration: 1. With respect to the start of the PRP period (indicated by timing instant t0 in Figure 41), the following sequence of conversions must be followed in order: convert LED2 → LED2 ambient → LED1 → LED1 ambient. 2. Also, starting from t0, the sequence of sampling instants must be staggered with respect to the respective conversions as follows: sample LED2 ambient → LED1 → LED1 ambient → LED2. 3. Finally, align the edges for the two LED pulses with the respective sampling instants. Table 2. Clock Edge Mapping to SPI Registers TIME INSTANT (See Figure 41 and Figure 42) 26 DESCRIPTION CORRESPONDING REGISTER ADDRESS AND REGISTER BITS EXAMPLE (Decimal) t0 Start of pulse repetition period No register control t1 Start of sample LED2 pulse LED2STC[15:0], register 01h 4800 t2 End of sample LED2 pulse LED2ENDC[15:0], register 02h 6399 t3 Start of LED2 pulse LED2LEDSTC[15:0], register 03h 4800 t4 End of LED2 pulse LED2LEDENDC[15:0], register 04h 6399 t5 Start of sample LED2 ambient pulse ALED2STC[15:0], register 05h t6 End of sample LED2 ambient pulse ALED2ENDC[15:0], register 06h 1599 t7 Start of sample LED1 pulse LED1STC[15:0], register 07h 1600 t8 End of sample LED1 pulse LED1ENDC[15:0], register 08h 3199 t9 Start of LED1 pulse LED1LEDSTC[15:0], register 09h 1600 t10 End of LED1 pulse LED1LEDENDC[15:0], register 0Ah 3199 t11 Start of sample LED1 ambient pulse ALED1STC[15:0], register 0Bh 3200 t12 End of sample LED1 ambient pulse ALED1ENDC[15:0], register 0Ch 4799 t13 Start of convert LED2 pulse LED2CONVST[15:0], register 0Dh t14 End of convert LED2 pulse LED2CONVEND[15:0], register 0Eh Must start one AFE clock cycle after the ADC reset pulse ends. 1599 t15 Start of convert LED2 ambient pulse ALED2CONVST[15:0], register 0Fh Must start one AFE clock cycle after the ADC reset pulse ends. 1602 t16 End of convert LED2 ambient pulse ALED2CONVEND[15:0], register 10h 3199 t17 Start of convert LED1 pulse LED1CONVST[15:0], register 11h Must start one AFE clock cycle after the ADC reset pulse ends. 3202 t18 End of convert LED1 pulse LED1CONVEND[15:0], register 12h 4799 t19 Start of convert LED1 ambient pulse ALED1CONVST[15:0], register 13h Must start one AFE clock cycle after the ADC reset pulse ends. 4802 t20 End of convert LED1 ambient pulse ALED1CONVEND[15:0], register 14h 6399 t21 Start of first ADC conversion reset pulse ADCRSTCNT0[15:0], register 15h t22 End of first ADC conversion reset pulse ADCRSTENDCT0[15:0], register 16h t23 Start of second ADC conversion reset pulse ADCRSTSTCT1[15:0], register 17h 1600 t24 End of second ADC conversion reset pulse ADCRSTENDCT1[15:0], register 18h 1600 t25 Start of third ADC conversion reset pulse ADCRSTSTCT2[15:0], register 19h 3200 t26 End of third ADC conversion reset pulse ADCRSTENDCT2[15:0], register 1Ah 3200 t27 Start of fourth ADC conversion reset pulse ADCRSTSTCT3[15:0], register 1Bh 4800 t28 End of fourth ADC conversion reset pulse ADCRSTENDCT3[15:0], register 1Ch 4800 t29 End of pulse repetition period PRPCOUNT[15:0], register 1Dh 6399 Submit Documentation Feedback — 0 2 0 0 Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 LED2 (RED LED) On Signal t3 LED1 (IR LED) On Signal SLED2_amb, Sample Ambient [LED2 (RED) Phase] t9 t10 t6 t5 SLED1, Sample LED1 (IR) t7 t8 SLED1_amb, Sample Ambient [LED1 (IR) Phase] t11 t12 SLED2, Sample LED2 (RED) CONVLED2, Convert LED2 (RED) Sample t4 t1 t13 t2 t14 CONVLED2_amb, Convert Ambient Sample [LED2 (RED) Phase] t15 t16 CONVLED1, Convert LED1 (IR) Sample t17 t18 CONVLED1_amb, Convert Ambient Sample [LED1 (IR) Phase] t19 t20 ADC Conversion ADC Reset t23 t21 t22 t0 t25 t24 t27 t26 t28 Pulse Repetition Period, One Cycle t29 (1) RED = LED2, IR = LED1. Figure 41. Programmable Clock Edges Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 27 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com CONVLED2, Convert LED2 (RED) Sample t14 t13 CONVLED2_amb, Convert Ambient Sample [LED2 (RED) Phase] t16 t15 CONVLED1, Convert LED1 (IR) Sample t18 t17 CONVLED1_amb, Convert Ambient Sample [LED1 (IR) Phase] t20 t19 ADC Conversion One 4-MHz Clock Cycle t21 ADC Reset t0 t23 t22 t25 t27 t24 t26 Pulse Repetition Period, One Cycle t28 t29 (1) RED = LED2, IR = LED1. Figure 42. Relationship Between the ADC Reset and ADC Conversion Signals 28 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 ADC OPERATION AND AVERAGING MODULE The ADC reset signal must be positioned at 25% intervals of the pulse repetition period (that is, 0%, 25%, 50%, and 75%). After the falling edge of the ADC reset signal, the ADC conversion phase starts (refer to Figure 42). Each ADC conversion takes 50 µs. The ADC operates with averaging. The averaging module averages multiple ADC samples and reduce noise to improve dynamic range because the ADC conversion time is usually shorter than 25% of the pulse repetition period. Figure 43 shows a diagram of the averaging module. Rx Digital ADC Reset ADC 22-Bits ADC Output Rate PRF Samples per Second ADC Register 42 LED2 Data Register 43 LED2_Ambient Data Register 44 LED1 Data Register 45 LED1_Ambient Data LED2 Data Ambient (LED2) Data Averager ADC Reset ADC Convert Register 30 LED1 Data Ambient (LED1) Data Number of Averages ADC Clock Figure 43. Averaging Module Operation With Averaging In this mode, the ADC digital samples are accumulated and averaged after every 50 µs. At the next rising edge of the ADC reset signal, the average value (22-bit) is written into the output registers sequentially as follows (see Figure 44): • At the 25% reset signal, the averaged 22-bit word is written to register 2Ah. • At the 50% reset signal, the averaged 22-bit word is written to register 2Bh. • At the 75% reset signal, the averaged 22-bit word is written to register 2Ch. • At the next 0% reset signal, the averaged 22-bit word is written to register 2Dh. The contents of registers 2Ah and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register 2Fh. At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out. The number of samples to be used per conversion phase is preset to 3. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 29 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com ADC Conversion ADC Data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ADC Reset 25% 0% Average of ADC data 1 to 3 are written into register 42. 50% 75% Average of ADC data 5 to 7 are written into register 43. Average of ADC data 9 to 11 are written into register 44. 0% Average of ADC data 13 to 15 are written into register 45. Register 42 and register 43 are written into register 46. Register 44 and register 45 are written into register 47. ADC_RDY Pin 0T Pulse repetition period T = 1/PRF 1.0 T NOTE: This example shows data 3 averages. Figure 44. ADC Data with Averaging 30 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 RECEIVER SUBSYSTEM POWER PATH The block diagram in Figure 45 shows the AFE4400 Rx subsystem power routing. 1.8 V RX_ANA_SUP (2.0 V to 3.6 V) RX_ANA_SUP to 1.8-V Regulator Rx Analog Modules RX_DIG_SUP (2.0 V to 3.6 V) RX_DIG_SUP to 1.8-V Regulator 1.8 V Rx I/O Block Rx Digital I/O Pins Device Figure 45. Receive Subsystem Power Routing Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 31 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com TRANSMIT SECTION The transmit section integrates the LED driver and the LED current control section with 8-bit resolution. This integration is designed to meet a dynamic range of better than 105 dB (based on a 1-sigma LED current noise). The LED2 and LED1 reference currents can be independently set. The current source (ILED) locally regulates and ensures that the actual LED current tracks the specified reference. Two LED driver schemes are supported: • An H-bridge drive for a two-terminal back-to-back LED package, as shown in Figure 46. The minimum Hbridge supply voltage must be 2.5 V + (maximum voltage drop across the LED). • A push-pull drive for a three-terminal LED package; see Figure 47. The minimum external supply voltage = 2.0 V + (maximum voltage drop across the LED). 3.3-V Supply H-Bridge Supply External Supply Tx CBULK H-Bridge LED2_ON H-Bridge Driver LED1_ON LED2_ON Or LED1_ON LED2 Current Reference ILED LED Current Control 8-Bit Resolution LED1 Current Reference Register LED2 Current Reference Register LED1 Current Reference Figure 46. Transmit: H-Bridge Drive 32 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 3.3-V Supply External Supply H-Bridge Supply CBULK Tx LED2_ON H-Bridge Driver LED1_ON LED2_ON Or LED1_ON LED2 Current Reference ILED LED Current Control 8-Bit Resolution LED1 Current Reference Register RED Current Reference Register IR Current Reference Figure 47. Transmit: Push-Pull LED Drive for Common Anode LED Configuration Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 33 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com Transmitter Power Path The block diagram in Figure 48 shows the AFE4400 Tx subsystem power routing. TX_CTRL_SUP_3.3V Tx Reference and Control LED_DRV_SUP_3.3V LED Current Control DAC Tx LED Bridge Device Figure 48. Transmit Subsystem Power Routing LED Power Reduction During Periods of Inactivity The diagram in Figure 49 shows how LED bias current passes 50 µA whenever LED_ON occurs. In order to minimize power consumption in periods of inactivity, the LED_ON control must be turned off. Furthermore, the TIMEREN bit in the CONTROL1 register should be disabled by setting the value to '0'. Note that depending on the LEDs used, the LED may sometimes appear dimly lit even when the LED current is set to 0 mA. This appearance is because of the switching leakage currents (as shown in Figure 49) inherent to the timer function. The dimmed appearance does not effect the ambient light level measurement because during the ambient cycle, LED_ON is turned off for the duration of the ambient measurement. 1 PA 50 PA 0 mA to 50 mA (See the LEDRANGE bits in the LEDCNTRL register.) LED_ON Figure 49. LED Bias Current 34 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 DIAGNOSTICS The device includes diagnostics to detect open or short conditions of the LED and photosensor, LED current profile feedback, and cable on or off detection. Photodiode-Side Fault Detection Figure 50 shows the diagnostic for the photodiode-side fault detection. Internal TX_CTRL_SUP 10 k 10 k 1k Cable Rx On/Off INM To Rx Front-End INP Rx On/Off PD Wires LED Wires 100 PA 100 PA GND Wires Legend for Cable Figure 50. Photodiode Diagnostic Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 35 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com Transmitter-Side Fault Detection Figure 51 shows the diagnostic for the transmitter-side fault detection. Internal TX_CTRL_SUP SW1 Cable SW3 10 k 10 k TX_OUTP LED 2 LED 1 D C SW2 SW4 TX_OUTM LED Wires 100 PA PD Wires 100 PA GND Wires LED DAC Legend for Cable Figure 51. Transmitter Diagnostic 36 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 Diagnostics Module The diagnostics module, when enabled, checks for nine types of faults sequentially. The results of all faults are latched in 11 separate flags. At the end of the sequence, the state of the 11 flags are combined to generate two interrupt signals: PD_ALM for photodiode-related faults and LED_ALM for transmitrelated faults. The status of all flags can also be read using the SPI interface. Table 3 details each fault and flag used. Note that the diagnostics module requires all AFE blocks to be enabled in order to function reliably. Table 3. Fault and Flag Diagnostics (1) MODULE SEQ. FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7 FLAG8 FLAG9 FLAG10 FLAG11 — — No fault 0 0 0 0 0 0 0 0 0 0 0 1 Rx INP cable shorted to LED cable 1 2 Rx INM cable shorted to LED cable 3 Rx INP cable shorted to GND cable 4 Rx INM cable shorted to GND cable 5 PD open or shorted 1 1 6 Tx OUTM line shorted to GND cable 7 Tx OUTP line shorted to GND cable 8 LED open or shorted 1 1 9 LED open or shorted PD LED (1) FAULT 1 1 1 1 1 1 Resistances below 10 kΩ are considered to be shorted. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 37 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com Figure 52 shows the timing for the diagnostic function. DIAG_EN Register Bit = 1 Diagnostic State Machine Diagnostic State Machine Diagnostic Ends Diagnostic Starts DIAG_END Pin tWIDTH = Four 4-MHz Clock Cycles tDIAG Figure 52. Diagnostic Timing Diagram By default, the diagnostic function takes tDIAG = 8 ms to complete. 38 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 SERIAL PROGRAMMING INTERFACE The SPI-compatible serial interface consists of four signals: SCLK (serial clock), SPISOMI (serial interface data output), SPISIMO (serial interface data input), and SPISTE (serial interface enable). The serial clock (SCLK) is the serial peripheral interface (SPI) serial clock. SCLK shifts in commands and shifts out data from the device. SCLK features a Schmitt-triggered input and clocks data out on the SPISOMI. Data are clocked in on the SPISIMO pin. Even though the input has hysteresis, TI recommends keeping SCLK as clean as possible to prevent glitches from accidentally shifting the data. When the serial interface is idle, hold SCLK low. The SPI serial out master in (SPISOMI) pin is used with SCLK to clock out the AFE4400 data. The SPI serial in master out (SPISIMO) pin is used with SCLK to clock in data to the AFE4400. The SPI serial interface enable (SPISTE) pin enables the serial interface to clock data on the SPISIMO pin in to the device. READING AND WRITING DATA The device has a set of internal registers that can be accessed by the serial programming interface formed by the SPISTE, SCLK, SPISIMO, and SPISOMI pins. Writing Data When SPISTE is low, • Serially shifting bits into the device is enabled. • Serial data (on the SPISIMO pin) are latched at every SCLK rising edge. • The serial data are loaded into the register at every 32nd SCLK rising edge. In case the word length exceeds a multiple of 32 bits, the excess bits are ignored. Data can be loaded in multiples of 32-bit words within a single active SPISTE pulse. The first eight bits form the register address and the remaining 24 bits form the register data. Figure 53 shows a diagram of the write timing. SPISTE SPISIMO A7 A6 A1 A0 D23 D22 D17 D16 D15 D14 D9 D8 D7 D6 D1 D0 SCLK 'RQ¶W FDUH, can be high or low. Figure 53. AFE SPI Write Timing Diagram Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 39 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com Reading Data The AFE4400 includes a mode where the contents of the internal registers can be read back on the SPISOMI pin. This mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the AFE. To enable this mode, first set the SPI_READ register bit using the SPI write command, as described in the Writing Data section. In the next command, specify the SPI register address with the desired content to be read. Within the same SPI command sequence, the AFE outputs the contents of the specified register on the SPISOMI pin. Figure 54 shows a timing diagram for the SPI read operation. SPISTE SPISIMO A7 A6 A1 A0 SPISOMI D23 D22 D17 D16 D15 D14 D9 D8 D7 D6 D1 D0 SCLK 'RQ¶W FDUH, can be high or low. (1) The SPI_READ register bit must be enabled before attempting a serial readout from the AFE. (2) Specify the register address of the content that must be readback on bits A[7:0]. (3) The AFE outputs the contents of the specified register on the SPISOMI pin. Figure 54. AFE SPI Read Timing Diagram Register Initialization After power-up, the internal registers must be initialized to the default values. This initialization can be done in one of two ways: • Through a hardware reset by applying a low-going pulse on the RESET pin, or • By applying a software reset. Using the serial interface, set SW_RESET (bit D3 in register 00h) high. This setting initializes the internal registers to the default values and then self-resets to '0'. In this case, the RESET pin is kept high (inactive). AFE SPI Interface Design Considerations Note that when the AFE4400 is deselected, the SPISOMI, CLKOUT, ADC_RDY, PD_ALM, LED_ALM, and DIAG_END digital output pins do not enter a 3-state mode. This condition, therefore, must be taken into account when connecting multiple devices to the SPI port and for power-management considerations. AFE REGISTER MAP The AFE consists of a set of registers that can be used to configure it, such as receiver timings, I-V amplifier settings, transmit LED currents, and so forth. The registers and their contents are listed in Table 4. These registers can be accessed using the AFE SPI interface. 40 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 Table 4. AFE Register Map ADDRESS REGISTER DATA Hex Dec D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CONTROL0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_RST DIAG_EN TIM_COUNT_RST SPI_READ NAME 0 0 0 0 0 1 0 LED2STC 01 1 0 0 0 0 0 0 0 0 LED2STC[15:0] LED2ENDC 02 2 0 0 0 0 0 0 0 0 LED2ENDC[15:0] LED2LEDSTC 03 3 0 0 0 0 0 0 0 0 LED2LEDSTC[15:0] LED2LEDENDC 04 4 0 0 0 0 0 0 0 0 LED2LEDENDC[15:0] ALED2STC 05 5 0 0 0 0 0 0 0 0 ALED2STC[15:0] ALED2ENDC 06 6 0 0 0 0 0 0 0 0 ALED2ENDC[15:0] LED1STC 07 7 0 0 0 0 0 0 0 0 LED1STC[15:0] LED1ENDC 08 8 0 0 0 0 0 0 0 0 LED1ENDC[15:0] LED1LEDSTC 09 9 0 0 0 0 0 0 0 0 LED1LEDSTC[15:0] LED1LEDENDC 0A 10 0 0 0 0 0 0 0 0 LED1LEDENDC[15:0] ALED1STC 0B 11 0 0 0 0 0 0 0 0 ALED1STC[15:0] ALED1ENDC 0C 12 0 0 0 0 0 0 0 0 ALED1ENDC[15:0] LED2CONVST 0D 13 0 0 0 0 0 0 0 0 LED2CONVST[15:0] LED2CONVEND 0E 14 0 0 0 0 0 0 0 0 LED2CONVEND[15:0] ALED2CONVST 0F 15 0 0 0 0 0 0 0 0 ALED2CONVST[15:0] ALED2CONVEND 10 16 0 0 0 0 0 0 0 0 ALED2CONVEND[15:0] LED1CONVST 11 17 0 0 0 0 0 0 0 0 LED1CONVST[15:0] LED1CONVEND 12 18 0 0 0 0 0 0 0 0 LED1CONVEND[15:0] ALED1CONVST 13 19 0 0 0 0 0 0 0 0 ALED1CONVST[15:0] ALED1CONVEND 14 20 0 0 0 0 0 0 0 0 ALED1CONVEND[15:0] 15 21 0 0 0 0 0 0 0 0 ADCRSTCT0[15:0] 16 22 0 0 0 0 0 0 0 0 ADCRENDCT0[15:0] ADCRSTSTCT1 17 23 0 0 0 0 0 0 0 0 ADCRSTCT1[15:0] ADCRSTENDCT1 18 24 0 0 0 0 0 0 0 0 ADCRENDCT1[15:0] ADCRSTSTCT2 19 25 0 0 0 0 0 0 0 0 ADCRSTCT2[15:0] ADCRSTENDCT2 1A 26 0 0 0 0 0 0 0 0 ADCRENDCT2[15:0] ADCRSTSTCT3 1B 27 0 0 0 0 0 0 0 0 ADCRSTCT3[15:0] ADCRSTENDCT3 1C 28 0 0 0 0 0 0 0 0 ADCRENDCT3[15:0] PRPCOUNT 1D 29 0 0 0 0 0 0 0 0 PRPCT[15:0] CONTROL1 1E 30 0 0 0 0 0 0 0 0 0 0 0 0 TIMEREN ADCRSTCNT0 ADCRSTENDCT0 0 SPARE1 1F 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIAGAIN 20 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKALMPIN[2:0] Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 41 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com Table 4. AFE Register Map (continued) ADDRESS REGISTER DATA 42 Dec D23 D22 D21 D20 TIA_AMB_GAIN 21 33 0 0 0 0 LEDCNTRL 22 34 0 0 0 0 0 0 1 CONTROL2 23 35 0 0 0 0 0 0 1 0 0 0 0 0 SPARE2 24 36 0 0 0 0 0 0 0 0 0 0 0 0 SPARE3 25 37 0 0 0 0 0 0 0 0 0 0 0 0 SPARE4 26 38 0 0 0 0 0 0 0 0 0 0 0 RESERVED1 27 39 0 0 0 0 0 0 0 0 0 0 RESERVED2 28 40 0 0 0 0 0 0 0 0 0 ALARM 29 41 0 0 0 0 0 0 0 0 0 D14 D13 D12 D11 0 0 0 0 D10 CF_LED[4:0] PDNRX PDNAFE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INPSCLED 0 0 0 INNSCLED 0 PDNTX 0 0 0 INPSCGND 0 0 0 INNSCGND 0 0 0 PDSC 0 0 0 PDOC 0 0 0 OUTNSHGND 0 0 ALMPINCLKEN 0 44 LED1VAL[23:0] 2D 45 ALED1VAL[23:0] LED2-ALED2VAL 2E 46 LED2-ALED2VAL[23:0] LED1-ALED1VAL 2F 47 LED1-ALED1VAL[23:0] DIAG 30 48 Submit Documentation Feedback LED_ALM 2C PD_ALM LED1VAL 0 RF_LED[2:0] OUTPSHGND 0 0 0 D0 LED2[7:0] 0 ALED1VAL 0 D1 0 LED2VAL[23:0] 0 D2 0 ALED2VAL[23:0] 0 D3 0 43 0 D4 0 42 0 D5 0 2B 0 D6 1 2A 0 D7 STG2GAIN[2:0] 0 LED2VAL 0 D8 LED1[7:0] ALED2VAL 0 D9 LEDSC AMBDAC[3:0] D15 XTALDIS D16 LED2OPEN D17 LED1OPEN D18 TXBRGMOD D19 STAGE2EN Hex LEDCUROFF NAME Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 AFE REGISTER DESCRIPTION CONTROL0: Control Register 0 (Address = 00h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 TIM_ SW_RST DIAG_EN COUNT_ RST SPI_ READ This register is used for AFE software and count timer reset, diagnostics enable, and SPI read functions. Bits D[23:4] Must be '0' Bit D3 SW_RST: Software reset 0 = No action (default after reset) 1 = Software reset applied; resets all internal registers to the default values and self-clears to '0' Bit D2 DIAG_EN: Diagnostic enable 0 = No action (default after reset) 1 = Diagnostic mode is enabled and the diagnostics sequence starts when this bit is set. At the end of the sequence, all fault status are stored in the DIAG: Diagnostics Flag Register. Afterwards, the DIAG_EN register bit self-clears to '0'. Bit D1 TIM_CNT_RST: Timer counter reset 0 = Disables timer counter reset, required for normal timer operation (default after reset) 1 = Timer counters are in reset state Bit D0 SPI READ: SPI read 0 = SPI read is disabled (default after reset) 1 = SPI read is enabled LED2STC: Sample LED2 Start Count Register (Address = 01h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED2STC[15:0] D3 D2 D1 D0 LED2STC[15:0] This register sets the start timing value for the LED2 signal sample. Bits D[23:16] Must be '0' Bits D[15:0] LED2STC[15:0]: Sample LED2 start count The contents of this register can be used to position the start of the sample LED2 signal with respect to the pulse repetition period (PRP), as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 43 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com LED2ENDC: Sample LED2 End Count Register (Address = 02h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED2ENDC[15:0] D3 D2 D1 D0 LED2ENDC[15:0] This register sets the end timing value for the LED2 signal sample. Bits D[23:16] Must be '0' Bits D[15:0] LED2ENDC[15:0]: Sample LED2 end count The contents of this register can be used to position the end of the sample LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. LED2LEDSTC: LED2 LED Start Count Register (Address = 03h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED2LEDSTC[15:0] D3 D2 D1 D0 LED2LEDSTC[15:0] This register sets the start timing value for when the LED2 signal turns on. Bits D[23:16] Must be '0' Bits D[15:0] LED2LEDSTC[15:0]: LED2 start count The contents of this register can be used to position the start of the LED2 with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4MHz clock cycles. Refer to the Using the Timer Module section for details. LED2LEDENDC: LED2 LED End Count Register (Address = 04h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED2LEDENDC[15:0] D3 D2 D1 D0 LED2LEDENDC[15:0] This register sets the end timing value for when the LED2 signal turns off. Bits D[23:16] Must be '0' Bits D[15:0] LED2LEDENDC[15:0]: LED2 end count The contents of this register can be used to position the end of the LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 44 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 ALED2STC: Sample Ambient LED2 Start Count Register (Address = 05h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED2STC[15:0] D3 D2 D1 D0 ALED2STC[15:0] This register sets the start timing value for the ambient LED2 signal sample. Bits D[23:16] Must be '0' Bits D[15:0] ALED2STC[15:0]: Sample ambient LED2 start count The contents of this register can be used to position the start of the sample ambient LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. ALED2ENDC: Sample Ambient LED2 End Count Register (Address = 06h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED2ENDC[15:0] D3 D2 D1 D0 ALED2ENDC[15:0] This register sets the end timing value for the ambient LED2 signal sample. Bits D[23:16] Must be '0' Bits D[15:0] ALED2ENDC[15:0]: Sample ambient LED2 end count The contents of this register can be used to position the end of the sample ambient LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. LED1STC: Sample LED1 Start Count Register (Address = 07h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED1STC[15:0] D3 D2 D1 D0 LED1STC[15:0] This register sets the start timing value for the LED1 signal sample. Bits D[23:17] Must be '0' Bits D[16:0] LED1STC[15:0]: Sample LED1 start count The contents of this register can be used to position the start of the sample LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 45 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com LED1ENDC: Sample LED1 End Count (Address = 08h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED1ENDC[15:0] D3 D2 D1 D0 LED1ENDC[15:0] This register sets the end timing value for the LED1 signal sample. Bits D[23:17] Must be '0' Bits D[16:0] LED1ENDC[15:0]: Sample LED1 end count The contents of this register can be used to position the end of the sample LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. LED1LEDSTC: LED1 LED Start Count Register (Address = 09h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED1LEDSTC[15:0] D3 D2 D1 D0 LED1LEDSTC[15:0] This register sets the start timing value for when the LED1 signal turns on. Bits D[23:16] Must be '0' Bits D[15:0] LED1LEDSTC[15:0]: LED1 start count The contents of this register can be used to position the start of the LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. LED1LEDENDC: LED1 LED End Count Register (Address = 0Ah, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED1LEDENDC[15:0] D3 D2 D1 D0 LED1LEDENDC[15:0] This register sets the end timing value for when the LED1 signal turns off. Bits D[23:16] Must be '0' Bits D[15:0] LED1LEDENDC[15:0]: LED1 end count The contents of this register can be used to position the end of the LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 46 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 ALED1STC: Sample Ambient LED1 Start Count Register (Address = 0Bh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED1STC[15:0] D3 D2 D1 D0 ALED1STC[15:0] This register sets the start timing value for the ambient LED1 signal sample. Bits D[23:16] Must be '0' Bits D[15:0] ALED1STC[15:0]: Sample ambient LED1 start count The contents of this register can be used to position the start of the sample ambient LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. ALED1ENDC: Sample Ambient LED1 End Count Register (Address = 0Ch, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED1ENDC[15:0] D3 D2 D1 D0 ALED1ENDC[15:0] This register sets the end timing value for the ambient LED1 signal sample. Bits D[23:16] Must be '0' Bits D[15:0] ALED1ENDC[15:0]: Sample ambient LED1 end count The contents of this register can be used to position the end of the sample ambient LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. LED2CONVST: LED2 Convert Start Count Register (Address = 0Dh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED2CONVST[15:0] D3 D2 D1 D0 LED2CONVST[15:0] This register sets the start timing value for the LED2 conversion. Bits D[23:16] Must be '0' Bits D[15:0] LED2CONVST[15:0]: LED2 convert start count The contents of this register can be used to position the start of the LED2 conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 47 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com LED2CONVEND: LED2 Convert End Count Register (Address = 0Eh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED2CONVEND[15:0] D3 D2 D1 D0 LED2CONVEND[15:0] This register sets the end timing value for the LED2 conversion. Bits D[23:16] Must be '0' Bits D[15:0] LED2CONVEND[15:0]: LED2 convert end count The contents of this register can be used to position the end of the LED2 conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. ALED2CONVST: LED2 Ambient Convert Start Count Register (Address = 0Fh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED2CONVST[15:0] D3 D2 D1 D0 ALED2CONVST[15:0] This register sets the start timing value for the ambient LED2 conversion. Bits D[23:16] Must be '0' Bits D[15:0] ALED2CONVST[15:0]: LED2 ambient convert start count The contents of this register can be used to position the start of the LED2 ambient conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. ALED2CONVEND: LED2 Ambient Convert End Count Register (Address = 10h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED2CONVEND[15:0] D3 D2 D1 D0 ALED2CONVEND[15:0] This register sets the end timing value for the ambient LED2 conversion. Bits D[23:16] Must be '0' Bits D[15:0] ALED2CONVEND[15:0]: LED2 ambient convert end count The contents of this register can be used to position the end of the LED2 ambient conversion signal with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 48 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 LED1CONVST: LED1 Convert Start Count Register (Address = 11h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED1CONVST[15:0] D3 D2 D1 D0 LED1CONVST[15:0] This register sets the start timing value for the LED1 conversion. Bits D[23:16] Must be '0' Bits D[15:0] LED1CONVST[15:0]: LED1 convert start count The contents of this register can be used to position the start of the LED1 conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. LED1CONVEND: LED1 Convert End Count Register (Address = 12h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 LED1CONVEND[15:0] D3 D2 D1 D0 LED1CONVEND[15:0] This register sets the end timing value for the LED1 conversion. Bits D[23:16] Must be '0' Bits D[15:0] LED1CONVEND[15:0]: LED1 convert end count The contents of this register can be used to position the end of the LED1 conversion signal with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. ALED1CONVST: LED1 Ambient Convert Start Count Register (Address = 13h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED1CONVST[15:0] D3 D2 D1 D0 ALED1CONVST[15:0] This register sets the start timing value for the ambient LED1 conversion. Bits D[23:16] Must be '0' Bits D[15:0] ALED1CONVST[15:0]: LED1 ambient convert start count The contents of this register can be used to position the start of the LED1 ambient conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 49 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com ALED1CONVEND: LED1 Ambient Convert End Count Register (Address = 14h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ALED1CONVEND[15:0] D3 D2 D1 D0 ALED1CONVEND[15:0] This register sets the end timing value for the ambient LED1 conversion. Bits D[23:16] Must be '0' Bits D[15:0] ALED1CONVEND[15:0]: LED1 ambient convert end count The contents of this register can be used to position the end of the LED1 ambient conversion signal with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. ADCRSTCNT0: ADC Reset 0 Start Count Register (Address = 15h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTCNT0[15:0] D3 D2 D1 D0 ADCRSTCNT0[15:0] This register sets the start position of the ADC0 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTCNT0[15:0]: ADC RESET 0 start count The contents of this register can be used to position the start of the ADC reset conversion signal (default value after reset is 0000h). Refer to the Using the Timer Module section for details. ADCRSTENDCT0: ADC Reset 0 End Count Register (Address = 16h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTENDCT0[15:0] D3 D2 D1 D0 ADCRSTENDCT0[15:0] This register sets the end position of the ADC0 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTENDCT0[15:0]: ADC RESET 0 end count The contents of this register can be used to position the end of the ADC reset conversion signal (default value after reset is 0000h). Refer to the Using the Timer Module section for details. 50 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 ADCRSTSTCT1: ADC Reset 1 Start Count Register (Address = 17h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTSTCT1[15:0] D3 D2 D1 D0 ADCRSTSTCT1[15:0] This register sets the start position of the ADC1 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTSTCT1[15:0]: ADC RESET 1 start count The contents of this register can be used to position the start of the ADC reset conversion. Refer to the Using the Timer Module section for details. ADCRSTENDCT1: ADC Reset 1 End Count Register (Address = 18h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTENDCT1[15:0] D3 D2 D1 D0 ADCRSTENDCT1[15:0] This register sets the end position of the ADC1 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTENDCT1[15:0]: ADC RESET 1 end count The contents of this register can be used to position the end of the ADC reset conversion. Refer to the Using the Timer Module section for details. ADCRSTSTCT2: ADC Reset 2 Start Count Register (Address = 19h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTSTCT2[15:0] D3 D2 D1 D0 ADCRSTSTCT2[15:0] This register sets the start position of the ADC2 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTSTCT2[15:0]: ADC RESET 2 start count The contents of this register can be used to position the start of the ADC reset conversion. Refer to the Using the Timer Module section for details. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 51 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com ADCRSTENDCT2: ADC Reset 2 End Count Register (Address = 1Ah, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTENDCT2[15:0] D3 D2 D1 D0 ADCRSTENDCT2[15:0] This register sets the end position of the ADC2 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTENDCT2[15:0]: ADC RESET 2 end count The contents of this register can be used to position the end of the ADC reset conversion. Refer to the Using the Timer Module section for details. ADCRSTSTCT3: ADC Reset 3 Start Count Register (Address = 1Bh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTSTCT3[15:0] D3 D2 D1 D0 ADCRSTSTCT3[15:0] This register sets the start position of the ADC3 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTSTCT3[15:0]: ADC RESET 3 start count The contents of this register can be used to position the start of the ADC reset conversion. Refer to the Using the Timer Module section for details. ADCRSTENDCT3: ADC Reset 3 End Count Register (Address = 1Ch, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 ADCRSTENDCT3[15:0] D3 D2 D1 D0 ADCRSTENDCT3[15:0] This register sets the end position of the ADC3 reset conversion signal. Bits D[23:16] Must be '0' Bits D[15:0] ADCRSTENDCT3[15:0]: ADC RESET 3 end count The contents of this register can be used to position the end of the ADC reset conversion signal (default value after reset is 0000h). Refer to the Using the Timer Module section for details. 52 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 PRPCOUNT: Pulse Repetition Period Count Register (Address = 1Dh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 PRPCOUNT[15:0] D3 D2 D1 D0 PRPCOUNT[15:0] This register sets the device pulse repetition period count. Bits D[23:16] Must be '0' Bits D[15:0] PRPCOUNT[15:0]: Pulse repetition period count The contents of this register can be used to set the pulse repetition period (in number of clock cycles of the 4-MHz clock). CONTROL1: Control Register 1 (Address = 1Eh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TIMEREN 0 0 0 0 0 0 1 0 D11 CLKALMPIN[2:0] This register configures the clock alarm pin and timer. Bits D[23:12] Must be '0' Bits D[11:9] CLKALMPIN[2:0]: Clocks on ALM pins Internal clocks can be brought to the PD_ALM and LED_ALM pins for monitoring. Note that the CLKALMPIN[2:0] register bits must be set before using this register bit. Table 5 defines the settings for the two alarm pins. Bit D8 TIMEREN: Timer enable 0 = Timer module is disabled and all internal clocks are off (default after reset) 1 = Timer module is enabled Bits D[7:2] Must be '0' Bit D1 Must be '1' Bit D0 Must be '0' Table 5. PD_ALM and LED_ALM Pin Settings CLKALMPIN[2:0] PD_ALM PIN SIGNAL LED_ALM PIN SIGNAL 000 Sample LED2 Sample LED1 001 LED2 pulse LED1 pulse 010 Sample LED2 Sample LED1 pulse 011 LED2 convert LED1 convert 100 LED2 ambient LED1 ambient 101 No output No output 110 No output No output 111 No output No output Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 53 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com SPARE1: SPARE1 Register For Future Use (Address = 1Fh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 This register is a spare register and is reserved for future use. Bits D[23:0] Must be '0' TIAGAIN: Transimpedance Amplifier Gain Setting Register (Address = 20h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 This register is reserved for factory use. Bits D[23:0] 54 Must be '0' Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 TIA_AMB_GAIN: Transimpedance Amplifier and Ambient Cancellation Stage Gain Register (Address = 21h, Reset Value = 0000h) D23 D22 0 0 D11 D10 0 D21 D20 0 0 D9 D8 D19 D18 D17 D16 D15 D14 D13 D12 0 STAGE2 EN 0 0 D3 D2 D1 D0 AMBDAC[3:0] D7 D6 STG2GAIN[2:0] D5 D4 CF_LED[4:0] RF_LED[2:0] This register configures the ambient light cancellation amplifier gain, cancellation current, and filter corner frequency. Bits D[23:20] Must be '0' Bits D[19:16] AMBDAC[3:0]: Ambient DAC value These bits set the value of the cancellation current. 0000 0001 0010 0011 0100 0101 0110 0111 = = = = = = = = 0 µA (default after reset) 1 µA 2 µA 3 µA 4 µA 5 µA 6 µA 7 µA Bit D15 Must be '0' Bit D14 STAGE2EN: Stage 2 enable 1000 1001 1010 1011 1100 1101 1110 1111 = = = = = = = = 8 µA 9 µA 10 µA Do not Do not Do not Do not Do not use use use use use 0 = Stage 2 is bypassed (default after reset) 1 = Stage 2 is enabled with the gain value specified by the STG2GAIN[2:0] bits Bits D[13:11] Must be '0' Bits D[10:8] STG2GAIN[2:0]: Stage 2 gain setting 000 001 010 011 100 101 110 111 Bits D[7:3] = = = = = = = = 0 dB, or linear gain of 1 (default after reset) 3 dB, or linear gain of 1.414 6 dB, or linear gain of 2 9 dB, or linear gain of 2.818 12 dB, or linear gain of 4 Do not use Do not use Do not use CF_LED[4:0]: Program CF for LEDs 00000 = 5 pF (default after reset) 00001 = 5 pF + 5 pF 00010 = 15 pF + 5 pF 00100 = 25 pF + 5 pF 01000 = 50 pF + 5 pF 10000 = 150 pF + 5 pF Note that any combination of these CF settings is also supported by setting multiple bits to '1'. For example, to obtain CF = 100 pF, set D[7:3] = 01111. Bits D[2:0] RF_LED[2:0]: Program RF for LEDs 000 001 010 011 = = = = 500 kΩ 250 kΩ 100 kΩ 50 kΩ 100 101 110 111 = = = = 25 kΩ 10 kΩ 1 MΩ None Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 55 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com LEDCNTRL: LED Control Register (Address = 22h, Reset Value = 0000h) D23 D22 0 0 D11 D10 D21 D20 D19 D18 D17 D16 1 D4 0 0 0 0 LEDCUR OFF D9 D8 D7 D6 D5 LED1[7:0] D15 D14 D13 D12 LED1[7:0] D3 D2 D1 D0 LED2[7:0] This register sets the LED current range and the LED1 and LED2 drive current. Bits D[23:18] Must be '0' Bit D17 LEDCUROFF: Turns the LED current source on or off 0 = On (50 mA) 1 = Off Bit D16 Must be '1' Bits D[15:8] LED1[7:0]: Program LED current for LED1 signal Use these register bits to specify the LED current setting for LED1 (default after reset is 00h). The nominal value of the LED current is given by Equation 3, where the full-scale LED current is 50 mA. Bits D[7:0] LED2[7:0]: Program LED current for LED2 signal Use these register bits to specify the LED current setting for LED2 (default after reset is 00h). The nominal value of LED current is given by Equation 4, where the full-scale LED current is 50 mA. LED1[7:0] 256 LED2[7:0] 256 56 ´ Full-Scale Current (3) ´ Full-Scale Current (4) Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 CONTROL2: Control Register 2 (Address = 23h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 1 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TXBRG MOD 0 XTAL DIS 1 0 0 0 0 0 PDNTX PDNRX PDNAFE This register controls the LED transmitter, crystal, and the AFE, transmitter, and receiver power modes. Bits D[23:18] Must be '0' Bit D17 Must be '1' Bits D[16:12] Must be '0' Bit D11 TXBRGMOD: Tx bridge mode 0 = LED driver is configured as an H-bridge (default after reset) 1 = LED driver is configured as a push-pull Bit D10 Must be '0' Bit D9 XTALDIS: Crystal disable mode 0 = The crystal module is enabled; the 8-MHz crystal must be connected to the XIN and XOUT pins 1 = The crystal module is disabled; an external 8-MHz clock must be applied to the XIN pin Bit D8 Must be '1' Bits D[7:3] Must be '0' Bit D2 PDN_TX: Tx power-down 0 = The Tx is powered up (default after reset) 1 = Only the Tx module is powered down Bit D1 PDN_RX: Rx power-down 0 = The Rx is powered up (default after reset) 1 = Only the Rx module is powered down Bit D0 PDN_AFE: AFE power-down 0 = The AFE is powered up (default after reset) 1 = The entire AFE is powered down (including the Tx, Rx, and diagnostics blocks) SPARE2: SPARE2 Register For Future Use (Address = 24h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 This register is a spare register and is reserved for future use. Bits D[23:0] Must be '0' Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 57 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com SPARE3: SPARE3 Register For Future Use (Address = 25h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 This register is a spare register and is reserved for future use. Bits D[23:0] Must be '0' SPARE4: SPARE4 Register For Future Use (Address = 26h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 This register is a spare register and is reserved for future use. Bits D[23:0] Must be '0' RESERVED1: RESERVED1 Register For Factory Use Only (Address = 27h, Reset Value = XXXXh) (1) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 X (1) X X X X X X X X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X X X X = don't care. This register is reserved for factory use. Readback values vary between devices. RESERVED2: RESERVED2 Register For Factory Use Only (Address = 28h, Reset Value = XXXXh) (1) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 X (1) X X X X X X X X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X X X X = don't care. This register is reserved for factory use. Readback values vary between devices. 58 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 ALARM: Alarm Register (Address = 29h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 ALMPIN CLKEN 0 0 0 0 0 0 0 This register controls the Alarm pin functionality. Bits D[23:8] Must be '0' Bit D7 ALMPINCLKEN: Alarm pin clock enable 0 = Disables the monitoring of internal clocks; the PD_ALM and LED_ALM pins function as diagnostic fault alarm output pins (default after reset) 1 = Enables the monitoring of internal clocks; these clocks can be brought out on PD_ALM and LED_ALM selectively (depending on the value of the CLKALMPIN[2:0] register bits). Bits D[6:0] Must be '0' LED2VAL: LED2 Digital Sample Value Register (Address = 2Ah, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D4 D3 D2 D1 D0 LED2VAL[23:0] D11 D10 D9 D8 D7 D6 D5 LED2VAL[23:0] Bits D[23:0] LED2VAL[23:0]: LED2 digital value This register contains the digital value of the latest LED2 sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. ALED2VAL: Ambient LED2 Digital Sample Value Register (Address = 2Bh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D4 D3 D2 D1 D0 ALED2VAL[23:0] D11 D10 D9 D8 D7 D6 D5 ALED2VAL[23:0] Bits D[23:0] ALED2VAL[23:0]: LED2 ambient digital value This register contains the digital value of the latest LED2 ambient sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 59 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 www.ti.com LED1VAL: LED1 Digital Sample Value Register (Address = 2Ch, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D4 D3 D2 D1 D0 LED1VAL[23:0] D11 D10 D9 D8 D7 D6 D5 LED1VAL[23:0] Bits D[23:0] LED1VAL[23:0]: LED1 digital value This register contains the digital value of the latest LED1 sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. ALED1VAL: Ambient LED1 Digital Sample Value Register (Address = 2Dh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D4 D3 D2 D1 D0 ALED1VAL[23:0] D11 D10 D9 D8 D7 D6 D5 ALED1VAL[23:0] Bits D[23:0] ALED1VAL[23:0]: LED1 ambient digital value This register contains the digital value of the latest LED1 ambient sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. LED2-ALED2VAL: LED2-Ambient LED2 Digital Sample Value Register (Address = 2Eh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D4 D3 D2 D1 D0 LED2-ALED2VAL[23:0] D11 D10 D9 D8 D7 D6 D5 LED2-ALED2VAL[23:0] Bits D[23:0] LED2-ALED2VAL[23:0]: (LED2 – LED2 ambient) digital value This register contains the digital value of the LED2 sample after the LED2 ambient is subtracted. The host processor must readout this register before the next sample is converted by the AFE. Note that this value is inverted when compared to waveforms shown in many publications. LED1-ALED1VAL: LED1-Ambient LED1 Digital Sample Value Register (Address = 2Fh, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D4 D3 D2 D1 D0 LED1-ALED1VAL[23:0] D11 D10 D9 D8 D7 D6 D5 LED1-ALED1VAL[23:0] Bits D[23:0] LED1-ALED1VAL[23:0]: (LED1 – LED1 ambient) digital value This register contains the digital value of the LED1 sample after the LED1 ambient is subtracted from it. The host processor must readout this register before the next sample is converted by the AFE. Note that this value is inverted when compared to waveforms shown in many publications. 60 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 AFE4400 www.ti.com SBAS601D – DECEMBER 2012 – REVISED MAY 2013 DIAG: Diagnostics Flag Register (Address = 30h, Reset Value = 0000h) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 0 0 0 0 0 0 0 0 0 0 0 PD_ALM D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LED_ ALM LED1 OPEN LED2 OPEN LEDSC OUTPSH GND OUTNSH GND PDOC PDSC INNSC GND INPSC GND INNSC LED INPSC LED This register is read only. This register contains the status of all diagnostic flags at the end of the diagnostics sequence. The end of the diagnostics sequence is indicated by the signal going high on DIAG_END pin. Bits D[23:13] Read only Bit D12 PD_ALM: Power-down alarm status diagnostic flag This bit indicates the status of PD_ALM (and the PD_ALM pin). 0 = No fault (default after reset) 1 = Fault present Bit D11 LED_ALM: LED alarm status diagnostic flag This bit indicates the status of LED_ALM (and the LED_ALM pin). 0 = No fault (default after reset) 1 = Fault present Bit D10 LED1OPEN: LED1 open diagnostic flag This bit indicates that LED1 is open. 0 = No fault (default after reset) 1 = Fault present Bit D9 LED2OPEN: LED2 open diagnostic flag This bit indicates that LED2 is open. 0 = No fault (default after reset) 1 = Fault present Bit D8 LEDSC: LED short diagnostic flag This bit indicates an LED short. 0 = No fault (default after reset) 1 = Fault present Bit D7 OUTPSHGND: OUTP to GND diagnostic flag This bit indicates that OUTP is shorted to the GND cable. 0 = No fault (default after reset) 1 = Fault present Bit D6 OUTNSHGND: OUTN to GND diagnostic flag This bit indicates that OUTN is shorted to the GND cable. 0 = No fault (default after reset) 1 = Fault present Bit D5 PDOC: PD open diagnostic flag This bit indicates that PD is open. 0 = No fault (default after reset) 1 = Fault present Bit D4 PDSC: PD short diagnostic flag This bit indicates a PD short. 0 = No fault (default after reset) 1 = Fault present Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 61 AFE4400 SBAS601D – DECEMBER 2012 – REVISED MAY 2013 Bit D3 www.ti.com INNSCGND: INN to GND diagnostic flag This bit indicates a short from the INN pin to the GND cable. 0 = No fault (default after reset) 1 = Fault present Bit D2 INPSCGND: INP to GND diagnostic flag This bit indicates a short from the INP pin to the GND cable. 0 = No fault (default after reset) 1 = Fault present Bit D1 INNSCLED: INN to LED diagnostic flag This bit indicates a short from the INN pin to the LED cable. 0 = No fault (default after reset) 1 = Fault present Bit D0 INPSCLED: INP to LED diagnostic flag This bit indicates a short from the INP pin to the LED cable. 0 = No fault (default after reset) 1 = Fault present 62 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: AFE4400 PACKAGE OPTION ADDENDUM www.ti.com 19-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) AFE4400RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 AFE4400 AFE4400RHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 AFE4400 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant AFE4400RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 AFE4400RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AFE4400RHAR VQFN RHA 40 2500 367.0 367.0 38.0 AFE4400RHAT VQFN RHA 40 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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