MCNIX MX27C4111MC-10 4m-bit [512k x8/256k x16] cmos eprom with page mode Datasheet

PRELIMINARY
MX27C4111
4M-BIT [512K x8/256K x16] CMOS EPROM
WITH PAGE MODE
FEATURES
•
•
•
•
•
•
•
•
•
•
With Page Mode function, 8-word/16-byte page
512K x 8 or 256K x 16 organization
+12.5V programming voltage
Fast access time: 90/100/120/150 ns
Page mode access time 50/60/75 ns
Totally static operation
Completely TTL compatible
Operating current: 60mA
Standby current: 100uA
Package type:
- 40 pin plastic DIP
- 40 pin SOP
GENERAL DESCRIPTION
The MX27C4111 is a 4M-bit, One Time Programmable
Read Only Memory with page mode. It is organized as
512K x 8 or 256K x 16, operates from a single + 5 volt
supply, has a static standby mode, and features fast
single address location programming. All programming
signals are TTL levels, requiring a single pulse. For
programming outside from the system, existing EPROM
programmers may be used. The MX27C4111 supports
a intelligent fast programming algorithm which can result
in programming time of less than two minutes.
MX27C4111 provides Page Read Access Mode which
can greatly reduce the read access time. Normal read
access time and Page Mode read access time is as fast
as 90/50ns. It is designed to be compatible with all
microprocessors and similar applications in which high
perofmrance, large bit storage and simple interfacing
are important design considerations.
PIN CONFIGURATIONS
BLOCK DIAGRAM
This EPROM is packaged in industry standard 40 pin
dual-in-line packages and 40 pin SOP packages.
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MX27C4111
PDIP/SOP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CE
OE
BYTE/VPP
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE/VPP
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
A0~A17
ADDRESS
INPUTS
CONTROL
LOGIC
.
.
.
.
.
.
.
.
Y-DECODER
X-DECODER
OUTPUT
BUFFERS
.
.
.
.
.
.
.
.
Q0~Q14
Q15/A-1
Y-SELECT
4M BIT
CELL
MAXTRIX
VCC
GND
P/N: PM0239
1
REV. 2.7, NOV. 19, 2002
MX27C4111
PIN DESCRIPTION
SYMBOL
PIN NAME
A0~A17
Address Input
Q0~Q14
Data Input/Output
CE
Chip Enable Input
OE
Output Enable Input
BYTE/VPP Word/Byte Selection/Program Supply
Voltage
Q15/A-1
Q15(Word mode)/LSB addr. (Byte
mode)
VCC
Power Supply Pin (+5V)
GND
Ground Pin
TRUTH TABLE OF BYTE FUNCTION
BYTE MODE(BYTE = GND)
CE
OE
Q15/A-1
MODE
Q0-Q7
SUPPLY CURRENT
H
X
X
Non selected
High Z
Standby(ICC2)
L
H
X
Non selected
High Z
Operating(ICC1)
L
L
A-1 input
Selected
DOUT
Operating(ICC1)
WORD MODE(BYTE = VCC)
CE
OE
Q15/A-1
MODE
Q0-Q14
SUPPLY CURRENT
H
X
High Z
Non selected
High Z
Standby(ICC2)
L
H
High Z
Non selected
High Z
Operating(ICC1)
L
L
DOUT
Selected
DOUT
Operating(ICC1)
NOTE : X = H or L
P/N: PM0239
2
REV. 2.7, NOV. 19, 2002
MX27C4111
FUNCTIONAL DESCRIPTION
AUTO IDENTIFY MODE
THE PROGRAMMING OF THE MX27C4111
The auto identify mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and device type. This mode is intended for use by
programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25°C ± 5°C ambient
temperature range that is required when programming
the MX27C4111.
When the MX27C4111 is delivered, or it is erased, the
chip has all 4M bits in the "ONE" or HIGH state. "ZEROs"
are loaded into the MX27C4111 through the procedure
of programming.
For programming, the data to be programmed is applied
with 16 bits in parallel to the data pins.
VCC must be applied simultaneously or before VPP,
and removed simultaneously or after VPP. When
programming an MXIC EPROM, a 0.1uF capacitor is
required across VPP and ground to suppress spurious
voltage transients which may damage the device.
To activate this mode, the programming equipment
must force 12.0 ± 0.5 V on address line A9 of the device.
Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL to
VIH. All other address lines must be held at VIL during
auto identify mode.
FAST PROGRAMMING
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For the
MX27C4111, these two identifier bytes are given in the
Mode Select Table. All identifiers for manufacturer and
device codes will possess odd parity, with the MSB
(Q15) defined as the parity bit.
The device is set up in the fast programming mode when
the programming voltage VPP = 12.75V is applied, with
VCC = 6.25 V and OE = VIH (Algorithm is shown in
Figure 1). The programming is achieved by applying a
single TTL low level 100us pulse to the CE input after
addresses and data line are stable. If the data is not
verified, an additional pulse is applied for a maximum of
25 pulses. This process is repeated while sequencing
through each address of the device. When the
programming mode is completed, the data in all address
is verified at VCC = VPP = 5V ± 10%.
READ MODE
The MX27C4111 provides page mode with 8 words/16
bytes per page. In order to get the benefit of fast page
read, the user should keep chip enable(CE) low and
toggle address A0~A2 in word mode or A-1~A2 in byte
mode. Page Read access time(tPA) is equal to the
delay from address stable to data output. It is twice as
fast as normal tACC and is highly recommended.
PROGRAM INHIBIT MODE
Programming of multiple MX27C4111's in parallel with
different data is also easily accomplished by using the
Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX27C4111 may be common. A
TTL low-level program pulse applied to an MX27C4111
CE input with VPP = 12.5 ± 0.5 V will program the
MX27C4111. A high-level CE input inhibits the other
MX27C4111s from being programmed.
WORD-WIDE MODE
With BYTE/VPP at VCC ± 0.2V outputs Q0-7 present
data Q0-7 and outputs Q8-15 present data Q8-15, after
CE and OE are appropriately enabled.
BYTE-WIDE MODE
PROGRAM VERIFY MODE
With BYTE/VPP at GND ± 0.2V, outputs Q8-15 are tristated. If Q15/A-1 = VIH, outputs Q0-7 present data bits
Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits
Q0-7.
Verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verification should be performed with OE at VIL, CE
at VIH, and VPP at its programming voltage.
P/N: PM0239
3
REV. 2.7, NOV. 19, 2002
MX27C4111
STANDBY MODE
connected to the READ line from the system control
bus. This assures that all deselected memory devices
are in their low-power standby mode and that the output
pins are only active when data is desired from a
particular memory device.
The MX27C4111 has a CMOS standby mode which
reduces the maximum VCC current to 100 uA. It is
placed in CMOS standby when CE is at VCC ± 0.3 V.
The MX27C4111 also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is
placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.
SYSTEM CONSIDERATIONS
During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
Vcc and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be
used between VCC and GND for each eight devices.
The location of the capacitor should be close to where
the power supply is connected to the array.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a twoline control function is provided to allow for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not
occur.
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
MODE SELECT TABLE
BYTE/
MODE
CE
OE
A9
A0
Q15/A-1
VPP(5)
Q8-14
Q0-7
Read (Word)
VIL
VIL
X
X
Q15 Out
VCC
Q8-14 Out
Q0-7 Out
Read (Upper Byte)
VIL
VIL
X
X
VIH
GND
High Z
Q8-15 Out
Read (Lower Byte)
VIL
VIL
X
X
VIL
GND
High Z
Q0-7 Out
Output Disable
VIL
VIH
X
X
High Z
X
High Z
High Z
Standby
VIH
X
X
X
High Z
X
High Z
High Z
Program
VIL
VIH
X
X
Q15 In
VPP
Q8-14 In
Q0-7 In
Program Verify
VIH
VIL
X
X
Q5 Out
VPP
Q8-14 Out
Q0-7 Out
Program Inhibit
VIH
VIH
X
X
High Z
VPP
High Z
High Z
Manufacturer Code(3)
VIL
VIL
VH
VIL
0B
VCC
00H
C2H
Device Code(3)
VIL
VIL
VH
VIH
1B
VCC
38H
00H
NOTES:
1.VH = 12.0V ± 0.5V
2.X = Either VIH or VIL
3.A1 - A8, A10 - A17 = VIL (For auto select)
4.See DC Programming Characteristics for VPP
voltages.
5.BYTE/VPP is intended for operation under DC
Voltage conditions only.
6.Manufacture code = 00C2H
Device code = B800H
P/N: PM0239
4
REV. 2.7, NOV. 19, 2002
MX27C4111
FIGURE 1. FAST PROGRAMMING FLOW CHART
START
ADDRESS = FIRST LOCATION
VCC = 6.25V
VPP = 12.75V
X=0
PROGRAM ONE 50us PULSE
INCREMENT X
INTERACTIVE
SECTION
YES
X = 25?
NO
FAIL
VERIFY BYTE
?
PASS
NO
LAST ADDRESS
INCREMENT ADDRESS
FAIL
YES
VCC = VPP = 5.25V
VERIFY SECTION
VERIFY ALL BYTES
?
FAIL
DEVICE FAILED
PASS
DEVICE PASSED
P/N: PM0239
5
REV. 2.7, NOV. 19, 2002
MX27C4111
SWITCHING TEST CIRCUITS
1.8K ohm
DEVICE
UNDER
TEST
+5V
DIODES = IN3064
OR EQUIVALENT
CL
6.2K ohm
CL = 100 pF including jig capacitance
SWITCHING TEST WAVEFORMS
2.0V
2.0V
TEST POINTS
AC driving levels
0.8V
0.8V
OUTPUT
INPUT
AC TESTING: AC driving levels are 2.4V/0.4V.
Input pulse rise and fall times are < 20ns.
NOTICE:
Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended period may affect reliability.
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
0oC to 70oC
Storage Temperature
-65oC to 125oC
Applied Input Voltage
-0.5V to 7.0V
Applied Output Voltage
-0.5V to VCC + 0.5V
VCC to Ground Potential
-0.5V to 7.0V
A9 & VPP
-0.5V to 13.5V
NOTICE:
Specifications contained within the following tables are subject to change.
P/N: PM0239
6
REV. 2.7, NOV. 19, 2002
MX27C4111
DC/AC Operating Condition for Read Operation
MX27C4111
-90
-10
-12
0°C to 70°C 0°C to 70°C
0°C to 70°C
5V ± 5%
5V ± 10%
5V ± 10%
Operating Temperature Commercial
Vcc POwer Supply
-15
0°C to 70°C
5V ± 10%
DC CHARACTERISTICS
SYMBOL
PARAMETER
VOH
Output High Voltage
VOL
Output Low Voltage
VIH
Input High Voltage
VIL
MIN.
MAX.
UNIT
CONDITIONS
V
IOH = -0.4mA
0.4
V
IOL = 2.1mA
2.0
VCC + 0.5
V
Input Low Voltage
-0.3
0.8
V
ILI
Input Leakage Current
-10
10
uA
VIN = 0 to 5.5V
ILO
Output Leakage Current
-10
10
uA
VOUT = 0 to 5.5V
ICC3
VCC Power-Down Current
100
uA
CE = VCC ± 0.3V
ICC2
VCC Standby Current
1.5
mA
CE = VIH
ICC1
VCC Active Current
60
mA
CE = VIL, f=5MHz, Iout = 0mA
IPP
VPP Supply Current Read
10
uA
CE = OE = VIL, VPP = 5.5V
2.4
CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only)
SYMBOL
PARAMETER
TYP.
MAX.
UNIT
CONDITIONS
CIN
Input Capacitance
8
12
pF
VIN = 0V
COUT
Output Capacitance
8
12
pF
VOUT = 0V
CVPP
VPP Capacitance
18
25
pF
VPP = 0V
AC CHARACTERISTICS
27C4111-90 27C4111-10
Symbol PARAMETER
MIN.
MAX.
MIN.
MAX.
27C4111-12
27C4111-15
MIN. MAX.
MIN.
MAX. UNIT CONDITIONS
tACC
Address to Output Delay
90
100
120
150
ns
CE = OE = VIL
tCE
Chip Enable to Output Delay
90
100
120
150
ns
OE = VIL
tPA
Page Address to Output Delay
50
50
60
75
ns
CE = OE =VIL
tOE
Output Enable to Output Delay
45
45
50
65
ns
CE = VIL
tDF
OE High to Output Float,
50
ns
0
30
0
0
0
0
30
0
35
0
or CE High to Output Float
tOH
Output Hold from Address,
0
0
ns
CE or OE which ever occurred first
tBHA
BYTE Access Time
tOHB
BYTE Output Hold Time
tBHZ
BYTE Output Delay Time
tBLZ
BYTE Output Set Time
90
0
100
0
0
70
10
120
70
10
7
0
70
10
P/N: PM0239
150
ns
70
10
ns
ns
ns
REV. 2.7, NOV. 19, 2002
MX27C4111
DC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5oC
SYMBOL
PARAMETER
VOH
Output High Voltage
VOL
Output Low Voltage
VIH
Input High Voltage
VIL
MIN.
MAX.
UNIT
CONDITIONS
V
IOH = -0.40mA
0.4
V
IOL = 2.1mA
2.0
VCC + 0.5
V
Input Low Voltage
-0.3
0.8
V
ILI
Input Leakage Current
-10
10
uA
VH
A9 Auto Select Voltage
11.5
12.5
V
ICC3
VCC Supply Current (Program & Verify)
50
mA
IPP2
VPP Supply Current(Program)
30
mA
VCC1
Fast Programming Supply Voltage
6.00
6.50
V
VPP1
Fast Programming Voltage
12.5
13.0
V
2.4
VIN = 0 to 5.5V
CE = VIL, OE = VIH
AC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5oC
SYMBOL
PARAMETER
MIN.
MAX.
tAS
Address Setup Time
2.0
us
tOES
OE Setup Time
2.0
us
tDS
Data Setup Time
2.0
us
tAH
Address Hold Time
0
us
tDH
Data Hold Time
2.0
us
tDFP
Chip Enable to Output Float Delay
0
tVPS
BYTE/VPP Setup Time
2.0
tPW
CE initial Program Pulse Width
95
tVCS
VCC Setup Time
2.0
tOE
Data valid from OE
130
8
CONDITIONS
ns
us
105
us
us
150
P/N: PM0239
UNIT
ns
REV. 2.7, NOV. 19, 2002
MX27C4111
WAVEFORMS
NORMAL READ CYCLE(WORD MODE)
ADDRESS
INPUTS
DATA ADDRESS
tACC
CE
tCE
OE
tDF
DATA
OUT
VALID DATA
tOE
tOH
PAGE MODE READ CYCLE
A4-A18
VALID ADDRESS
A0~A2 (Word mode)
A-1~A2 (Byte mode)
tACC
CE
tPA
tPA
tPA
OE
tOH
tDF
tOE
DATA OUT
P/N: PM0239
9
REV. 2.7, NOV. 19, 2002
MX27C4111
WAVEFORMS
NORMAL READ CYCLE(BYTE MODE)
HIGH-Z
A-1
HIGH-Z
tACC
tOH
BYTE/VPP
Q0-Q7
VALID DATA
VALID DATA
tBHA
tOHB
VALID DATA
Q15-Q8
tBHZ
tBLZ
FAST PROGRAMMING ALGORITHM WAVEFORMS
VERIFY
PROGRAM
VIH
Addresses
VALID ADDRESS
VIL
tAH
tAS
DATA OUT VALID
DATA SET
DATA
tDS
tDFP
tDH
VPP1
BYTE/VPP
VCC
tVPS
VCC1
VCC
VCC
tVCS
VIH
CE
VIL
tPW
tOES
tOE
VIH
OE
VIL
P/N: PM0239
10
REV. 2.7, NOV. 19, 2002
MX27C4111
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO.
ACCESS TIME
OPERATING CURRENT
(ns)
MAX.(mA)
STANDBY CURRENT PACKAGE
MAX.(uA)
MX27C4111MC-90
90
60
100
40 Pin SOP(ROM pin out)
MX27C4111MC-10
100
60
100
40 Pin SOP(ROM pin out)
MX27C4111MC-12
120
60
100
40 Pin SOP(ROM pin out)
MX27C4111MC-15
150
60
100
40 Pin SOP(ROM pin out)
MX27C4111PC-90
90
60
100
40 Pin PDIP(ROM pin out)
MX27C4111PC-10
100
60
100
40 Pin PDIP(ROM pin out)
MX27C4111PC-12
120
60
100
40 Pin PDIP(ROM pin out)
MX27C4111PC-15
150
60
100
40 Pin PDIP(ROM pin out)
P/N: PM0239
11
REV. 2.7, NOV. 19, 2002
MX27C4111
PACKAGE INFORMATION
P/N: PM0239
12
REV. 2.7, NOV. 19, 2002
MX27C4111
P/N: PM0239
13
REV. 2.7, NOV. 19, 2002
MX27C4111
REVISION HISTORY
Revision No. Description
2.0
1) Eliminate Interactive Programming Mode
2) 40-CDIP package quartz lens, change to square shape.
2.1
IPP 100uA --> 10uA
2.2
Add 100ns speed grade.
2.3
Add 90ns speed grade.
2.4
90ns speed grade VCC=5V±10% --> VCC=5V±5%
2.5
Cancel ceramic DIP package type
2.6
Cancel "Ultraviolet Erasable" wording in General Description
To modify Package Information
2.7
To modify Package Information
P/N: PM0239
14
Page
P1,3,12,13
P1
P12~13
P12~13
Date
6/14/1997
8/07/1997
1/31/1998
4/07/1998
5/06/1998
MAR/02/2000
AUG/20/2001
NOV/19/2002
REV. 2.7, NOV. 19, 2002
MX27C4111
MACRONIX INTERNATIONAL CO., LTD.
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