MITSUBISHI 〈DIGITAL ASSP〉 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP M66335FP FACSIMILE IMAGE DATA PROCESSOR FACSIMILE IMAGE DATA PROCESSOR DESCRIPTION • Built-in A/D converter of a 7-bit flash type • Built-in image processing memories The M66335 is a facsimile image processing controller to turn into binary signals analog signals which have been output through photoelectric conversion by the image sensor. The image processing functions includes peak value detection, uniformity correction, resolution change, MTF compensation, γ correction, detection of background/character levels, error diffusion, separation of image zones, and designation of regions. This controller contains not only the analog processing circuit, the A/ D converter of a 7-bit flash type and image processing memory, but also the image sensor and the interface circuit to the CODEC (Coder and Decoder). Therefore, this LSI alone is capable of image processing. • • • FEATURES • High speed scan (max. 2 ms/line, typ. 5 ms/line) • Compatibility with up to the B4 (8 pixels/mm, 16 pixels/mm) image • APPLICATION Facsimile, word processor and image scanner 63 64 NC GND VCC 62 61 ↔ D7 60 ↔ D6 59 ↔ D5 58 ↔ D4 MPU 57 ↔ D3 INTERFACE 56 ↔ D2 55 ↔ D1 54 ↔ D0 GND 53 VCC 52 51 ← TEST6 50 ← TEST5 49 ← TEST4 48 ← TEST3 47 ← TEST2 TEST PIN 46 ← TEST1 45 ← TEST0 44 ← TESTI 43 → TESTO VCC 42 41 GND PIN CONFIGURATION (TOP VIEW) NC 65 A0 → 66 A1 → 67 A2 → 68 A3 → 69 MPU INTERFACE A4 → 70 CS → 71 RD → 72 WR → 73 RESET → 74 DAK → 75 DMA DRQ ← 76 INTERFACE INT ← 77 SYSTEM CLOCK SYSCK → 78 GND 79 NC 80 NC DGND DVCC 38 VBL ADC BLACK REFERENCE OUTPUT 37 36 VWL ADC WHITE REFERENCE OUTPUT 35 ← ADIN ADC INPUT 34 AVCC Vri+ ADC WHITE REFERENCE INPUT 33 32 AGND Vri- ADC BLACK REFERENCE INPUT 31 30 → BCMO 29 ← BCMV CONTROL SIGNAL FOR 28 ← BCMI ANALOG SIGNAL 27 ← C2 PROCESSING 26 ← C1 NC 25 40 39 M66335FP CONTROL SIGNAL FOR ANALOG SIGNAL PROCESSING SENSOR INTERFACE CODEC INTERFACE SINGLE-LINE CYCLE CLOCK Outline 80P6N–A SENSOR INTERFACE 1 NC 2 NC 3 VCC ACCK ← 4 SVID ← 5 SCLK ← 6 STIM ← 7 SRDY → 8 PTIM ← 9 GND 10 VCC 11 RS ← 12 CK1 ← 13 CK2 ← 14 SH ← 15 GND 16 VCC 17 AVCC 18 AIN → 19 LEVAJ → 20 AGND 21 GCAO ← 22 NC 23 NC 24 • • sensor Generation of control signals for the image sensor (CCD, CIS) For CCD: SH, CK1, CK2, RS For the contact sensor (CIS): SH, CK1, CK2 Built-in analog processing circuit (equivalent to the M64291) Sample and hold circuit Gain control circuit Black level clamping circuit Reference internal power supply for the A/D converter Uniformity correction memory, Line memory, Error memory, γ correction memory External output interface for converted binary data Serial output (→ M66330) DMA output External output interface for multivalued data DMA transfer of data compensated for uniformity Various image processing functions Uniformity correction Resolution change from 50% to 200% (by the 1% step) MTF compensation (2-dimensional processing, capable of correction for each character/photo) γ correction (capable of correction for each character/photo) Detection of background/character levels Change to pseudo-halftone • Error diffusion (64 tone steps through 6-bit processing) • Organized dither (64 tone steps through the 8 × 8 matrix) Image zone separation (2-dimensional processing) 5V single power supply NC: No Connection 1 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR BLOCK DIAGRAM ADIN VWL VBL Vri+ Vri36 35 37 33 31 19 20 26 27 28 29 22 30 ANALOG SIGNAL PROCESSING CIRCUIT PTIMB RS CK1 CK2 SH 9 12 13 14 15 SENSOR CONTROL DVCC 18 34 38 VCC 3 11 17 42 52 62 78 ANALOG CONTROL AIN LEVAJ C1 C2 BCMI BCMV GCAO BCMO AVCC IMAGE PROCESSING SEQUENCE CONTROL SIGNAL IMAGE ZONE SEPARATION 7-BIT A/D CONVERTER UNIFORMITY CORRECTION 4 DETECTION OF BACKGROUND/ CHARACTER LEVELS RESOLUTION CHANGE MTF COMPENSATION γ CORRECTION TABLE IMAGE BUS INTERFACE ERROR DIFFUSION DMA CONTROL CORRECTION DATA MEMORY CONVERSION TABLE MEMORY LINE MEMORY ERROR MEMORY DITHER MATRIX 5 6 7 SRDYB SVID SCLK STIMB 75 76 77 DAKB DRQ INT 8 SELECTION OF CONVERSIONTO-BINARY PROCESSING SYSCK ACCK ORGANIZED DITHER MPU BUS INTERFACE 2132 39 1016 41 53 63 79 AGND DGND GND 74 RESETB 73 WRB 72 RDB 71 CSB 66 } A0 ~ A4 70 54 } D0 ~ D7 61 Table 1 Image processing functions Image processing functions 2 Specifications Remarks Reading range • A4, B4 Resolution • 8 pixels/mm, 16 pixels/mm (for the horizontal scanning direction) Reading speed • Typ.: 5 ms/line; max.: 2 ms/line • Controlled through the system clock. Uniformity correction • White correction, black correction • Correction range: 50% • Correction memory is built in. • Readable from/writable in MPU γ correction • Logarithmic correction • γ correction memory is built in. • Capable of correction for each character/photo. MTF compensation • Laplacian filter circuit through 2-dimensional processing • Correction memory is built in. • Capable of correction for each character/photo. Simple conversion to binary • Floating slice system through the detection circuit for background/character levels Pseudo-halftone • Error diffusion: 6-bit processing (for 64 tone steps) • Organized dither: 8 × 8 matrix (for 64 tone steps) Image zone separation • 2-dimensional processing through luminance difference Image reduction • Range of the reduction rate: 50% to 100% (by the 1% step) • Capable of outputting the average line of a dropped line and the subsequent line instead of both lines Image enlargement • Range of the enlargement rate: 100% to 200% (by the 1% step) • Capable of outputting the average line of a repeated line and the subsequent line instead of the repeated line Image sensor control signal • CIS image sensor (clock duty: 75%) • CCD image sensor Analog processing • The sample/hold circuit, gain control amplifier, black level clamping circuit, and 7-bit A/D converter are built-in. • Error buffer memory is built in. • 64W × 6 bits dither memory is built in. MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR DESCRIPTION OF DIGITAL PIN FUNCTIONS Item Sensor interface CODEC interface DMA interface Clock MPU interface Others Pin name Input/output Function SH Output Outputs the shift pulse signal to transfer electric charges from the sensor’s photoconductor component to its transferring component for CCD and the start signal to start the sensor reading circuit for CIS. CK1 Output Outputs the clock pulse signal to sequentially transfer out signaling electric charges from the sensor’s transferring component for CCD and the clock pulse signal for the shift register of the sensor reading circuit for CIS. CK2 Output Reversed-phase pulses of CK1 RS Output Outputs the reset pulse to return the voltage at the floating capacitor of the CCD sensor to the initial one. PTIM Output Outputs the pulse motor control signal for the reading roller. SRDY Input STIM Output Defines the data transfer section to CODEC. SCLK Output Clock signal to transfer image data to CODEC SVID Output Outputs image data in serial to CODEC DRQ Output DMA request signal to the external DMA controller to output in parallel image data through the MPU bus DAK Input INT Output SYSCK Transfer start ready signal for data from CODEC DMA acknowledge signal from the external DMA controller in response to the above DRQ signal Single-line termination interrupt Input System clock input pin ACCK Output Single-line cycle clock RESET Input Input of the system reset. The cycle counter, register, F/F, and latch are reset. CS Input Chip select signal for MPU to access the M66335 RD Input Control signal for MPU to read data from the M66335 WR Input Control signal for MPU to write data to the M66335 A0 ~ A4 Input Address signal to access various registers inside the M66335 D0 ~ D7 Input/Output 8 bit two way buffer VCC – Positive power supply pin GND – GND pin TESTI, 0~6 TESTO Input Test input pin. Hold this at “L”. Output Test output pin. Set this open. 3 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR DESCRIPTION OF ANALOG PIN FUNCTIONS (Cont.) Item Power supply GND Input/output Function AVCC – Analog power supply pin (rated supply voltage: 5V) DVCC – Digital power supply pin (rated supply voltage: 5V) AGND – Analog ground pin DGND – Digital ground pin Sensor signal AIN input part Input Pin to input analog signals output from CCD or CIS (Signals from CCD are input through capacity coupling and those from CIS, with no clamping levels, are input directly.) Gain control circuit C1, C2 Input Pin to control the frequency characteristic of the gain control circuit LEVAJ Input Pin to control the DC level of output signals of the gain control circuit. The output voltage, VGCAO, is obtained by the following equation: VGCAO = VLEVAJ + GV × VIN, where, VLEVAJ: voltage at LEVAJ VIN: input signal GV: gain of the gain control circuit VIN is the signal element corresponding to the signal level clamped through the input clamping circuit for CCD·CIS3 input or to the GND level for CIS1·CIS2 input. GCAO Output BCMI Input Signal input pin to the black clamping circuit. Use this with capacity coupling with the GCAO pin. BCMV Input Pin to set the black level clamping voltage. Sets the black level of signals output from the BCMO pin for CCD signal processing. BCMO Output Black level clamping circuit A/D converter 4 Pin name Signal output pin of the gain control circuit Signal output pin of the black level clamping circuit Vri+ Input Output of the circuit to generate the A/D full-scale point reference voltage (3.8V). Connected with VWL through the buffer inside the IC. To change the A/D reference voltage range, input a DC voltage from this pin. Vri– Input Output of the circuit to generate the A/D zero point reference voltage (1.8V). Connected with VBL through the buffer inside the IC. To change the A/D reference voltage range, input a DC voltage from this pin. ADIN Input Signal input pin to the A/D converting circuit. Use this by connecting with the BCMO pin for CCD or with the GCAO pin for CIS. Input signals in the voltage range (1.8V to 3.8V) set through VWL and VBL. VWL Output Output of the circuit generating the A/D full-scale reference voltage (3.8V). Connected inside the IC with the A/D converter. VBL Output Output of the circuit generating the A/D zero point reference voltage (1.8V). Connected inside the IC with the A/D converter. MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR (1) Operation mode The M66335 has three basic operations. Peak value detection: Adjusting the peak value of analog signals output from the analog circuit to the white reference voltage (VWL) of the A/D converter built in the M66335. Generation of data for uniformity correction: Generating data on a white reference original sheet for uniformity correction by the sensor unit and writing them to the memory for correction built in the M66335. Read: Reading original sheets, performing image processing of the read image data, and outputting in serial or parallel the indicated converted binary data. The M66335 is capable of performing the DMA transfer of multivalued data (6-bit data=D7~D2, D1=D0=0) after correction about uniformities. These three basic operations are performed in the following mode sequences for the CCD sensor and CIS sensor. The sensor is set through the register 00 (SENS). • For the CIS sensor AGC mode The peak value of the 16 line cycle is detected by setting the AGC command in the register 00 at “H”. To escape this mode, set the AGC command at “L” after a 20 line cycle (or a cycle of 16 lines or more) passed since the start. UNIF mode (black) When this operation mode is started by the UNIF command after setting UMODE: “L” (black correction) in the register 00 and UNIFM: “H” (black and white correction) in the register 01, the system also generates black data for non-uniformity correction for black correction (for the 8 line cycle). To escape this mode, set the UNIF command at “L” after a 10 line cycle (or a cycle of 8 lines or more) passed since the start. In the case of only white correction, the setting is not necessary. Follow the instruction below. • • For the CCD sensor AGC mode UNIF mode (white) SCAN mode The peak value of the 16 line cycle is detected by setting the AGC command in the register 00 at “H”. To escape this mode, set the AGC command at “L” after a 20 line cycle (or a cycle of 16 lines or more) passed since the start. This operation mode is started by setting the UNIF command in the register 00 at “H” after setting UMODE: “H” (white correction) in the register 00 and UNIFM: “L” (only white correction) in the register 01. Starting by the UNIF command also makes the system generate data for nonuniformity correction for white correction (for the 8 line cycle). To escape this mode, set the UNIF command at “L” after a 10 line cycle (or a cycle of 8 lines or more) passed since the start. The read operation mode is started by setting the SCAN command in the register 00 at “H”. To escape this mode, set the SCAN command at “L”. UNIF mode (white) SCAN mode When this operation mode is started by the UNIF command in the register 00 after setting UMODE: “H” (white correction) in the register 00 and UNIFM: “L” (only white correction) in the register 01, the system also generates white data for nonuniformity correction for white correction (for the 8 line cycle). To escape this mode, set the UNIF command at “L” after a 10 line cycle (or a cycle of 8 lines or more) passed since the start. The reading operation is started by setting the SCAN command in the register 00 at “H”. To escape this mode, set the SCAN mode at “L”. The signal operations and data flow in each basic operation are shown in the page 4-217 and 4-218, and the flowchart is in the page 4-260 and 4-261. 5 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR OPERATIONS OF SIGNALS IN THE PEAK VALUE DETECTION OPERATION BCAO GCAO VWL,VBL ADIN Vri+,Vri- Analog control Image sensor C1 C2 BCMV BCMI LEVAJ AIN SH CK1 CK2 RS PTIMB ACCK SYSCK Image processing sequence control signal STIMB SCLK SVID Image zone separation 7bit A /D converter Detection of background/ character levels Analog signal processing circuit Uniformity correction Resolution change MTF compensation γ correction table Error diffusion Sensor control Correction data memory Conversion table memory Line memory Error memory Dither matrix Selection of processing for conversion to binary Image bus interface DMA control Organized dither MPU bus interface SRDYB CODEC INT DRQ DAKB DMA RESETB CSB WRB RDB A0~A4 MPU D0~D7 FLOW OF DATA IN THE CREATION OF DATA FOR UNIFORMITY CORRECTION BCAO GCAO VWL,VBL ADIN Vri+,Vri- Analog control Image sensor C1 C2 BCMV BCMI LEVAJ AIN SH CK1 CK2 RS PTIMB 6 ACCK SYSCK Image processing sequence control signal STIMB SCLK SVID Image zone separation 7bit A /D converter Detection of background/ character levels Analog signal processing circuit Uniformity correction Resolution change MTF compensation γ correction table Error diffusion Sensor control Correction data memory Conversion table memory Line memory Error memory Dither matrix Selection of processing for conversion to binary Image bus interface DMA control Organized dither MPU bus interface SRDYB CODEC INT DRQ DAKB DMA RESETB CSB WRB RDB A0~A4 MPU D0~D7 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR FLOW OF DATA IN THE READING OPERATION (FOR OUTPUT IN SERIAL: BINARY DATA) BCAO GCAO VWL,VBL ADIN Vri+,Vri- Analog control Image sensor C1 C2 BCMV BCMI LEVAJ AIN SH CK1 CK2 RS PTIMB ACCK SYSCK Image processing sequence control signal STIMB SCLK SVID Image zone separation 7bit A /D converter Detection of background/ character levels Analog signal processing circuit Uniformity correction Resolution change MTF compensation g correction table Error diffusion Sensor control Correction data memory Conversion table memory Line memory Error memory Dither matrix Selection of processing for conversion to binary Image bus interface DMA control Organized dither MPU bus interface SRDYB CODEC INT DRQ DAKB DMA RESETB CSB WRB RDB A0~A4 MPU D0~D7 : image data : correction or compensation data FLOW OF DATA IN THE READING OPERATION (FOR OUTPUT IN PARALLEL: BINARY DATA) BCAO GCAO VWL,VBL ADIN Vri+,Vri- Analog control Image sensor C1 C2 BCMV BCMI LEVAJ AIN SH CK1 CK2 RS PTIMB ACCK SYSCK Image processing sequence control signal STIMB SCLK SVID Image zone separation 7bit A /D converter Detection of background/ character levels Analog signal processing circuit Uniformity correction Resolution change MTF compensation g correction table Error diffusion Sensor control Correction data memory Conversion table memory Line memory Error memory Dither matrix Selection of processing for conversion to binary Image bus interface DMA control Organized dither MPU bus interface SRDYB CODEC INT DRQ DAKB DMA RESETB CSB WRB RDB A0~A4 MPU D0~D7 : image data : correction or compensation data FLOW OF SIGNALS IN THE READING OPERATION (FOR MULTIVATED DATA) BCAO GCAO VWL,VBL ADIN Vri+,Vri- Analog control Image sensor C1 C2 BCMV BCMI LEVAJ AIN SH CK1 CK2 RS PTIMB ACCK SYSCK Image processing sequence control signal STIMB SCLK SVID Image zone separation 7bit A /D converter Detection of background/ character levels Analog signal processing circuit Uniformity correction Resolution change MTF compensation g correction table Error diffusion Sensor control Correction data memory Conversion table memory Line memory Error memory Dither matrix Selection of processing for conversion to binary Image bus interface DMA control Organized dither MPU bus interface SRDYB CODEC INT DRQ DAKB DMA RESETB CSB WRB RDB A0~A4 MPU D0~D7 7 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR (2) Line cycle and reading sequence • Uniformity correction range (UNIFG): The relationship between the line cycle and the reading sequence of the M66335 is shown in Fig. 1. The relationship between the CODEC interface operations and the reading sequence is shown in Fig. 2 and that between the DMA interface operations and the reading sequence is shown in Fig. 3. • • Defines the range where uniformity correction is performed. This range corresponds to the width of the sensor (B4 to A4). For the relationship between the sensor width and the uniformity correction range, see Table 2. • AGC range (AGCG): Single-line cycle (1/ACCK): Defines the processing time per line of the M66335. The single-line cycle is decided by the line cycle counter value registers 03 and 04 (PRE_DATA), and the pixel transfer clock. The pixel transfer clock is 1/16 of SYSCK. 1 line cycle (1/ACCK) [NS] = line cycle counter value × pixel transfer clock cycle [NS] = (PRE_DATA + 1) × pixel transfer clock cycle [NS] = (PRE_DATA + 1) × 16/SYSCK [NS] After loading the PRE_DATA value, the line cycle counter generates the addresses of the following gate signals while counting down with the pixel transfer clock. Sensor start pulse (SH): Image sensor start pulse. The point of the start pulse is decided by the uniformity correction range (UNIFG) and the value of the register 05. [ST_PL] The ST_PL value must be set according to the following formulas for each image sensor type. CCD: ST_PL = dummy pixels of the sensor + 2 CIS: ST_PL = 2 Defines the range where peak value detection is performed. This range corresponds to the sensor width (B4 to A4). Auto gain control is performed for the whole width of the sensor (solid line) in the AGC mode and for the narrower width (dashed line) than the sensor width in the SCAN mode. For the relationship between the sensor width and the AGC range, see Table 2. • Original sheet reading width: Defines the reading width for original sheets. For original sheet widths narrower than the sensor width, the reading range (dashed line) is set, using the sensor center as the base center point. Therefore, the points for the original sheet should be based on the sensor center. For the relationship between the sensor width and the original sheet reading width, see Table 3. • Pulse motor control signal (PTIM): Generates control signals for the pulse motor for the reading roller. PRE_DATA loading 0 Relationship with the registers Countdown Registers 03 and 04 (PRE_DATA) Line cycle (ACCK) Register 00 (SENS_W) Register 05 (ST_PL) Sensor start pulse (SH) ST_PL Uniformity correction range (UNIFG) Register 00 (SENS_W) AGC range (AGCG) Register 00 (SENS_W) Register 01 (SOURCE) Register 00 (SENS_W) Register 11, 12 (OFFSET) Original sheet reading range Pulse motor control (PTIM) 1 line cycle Fig. 1 Line cycle and the reading sequence 8 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ACCK SH SRDYB <SRDYB> (SSCAN) 3 1 4 INT 2 STIMB SCLK SVID PTIMB 5 <INTCLR> <INTCLR> : Register setting (SSCAN) : Internal signal SRDYB : ‘L’ is taken in with a ↑ flow of SH, when scanning is started and PTIMB is output. (SSCAN : ‘H’) During the period that STIMB is ‘L’, converted binary data are output. SRDYB : ‘H’ is taken in with a ↑ flow of ACCK, when the reading of one line ends. (SSCAN : ‘L’) INT is asserted with a ↓ flow of SSCAN. (INT : ‘H’) When CPU is ready for reading the next line, INTCLR is generated and INT is negated, and then SRDYB is set ‘L’. : Output section 1 2 3 4 5 Fig. 2 CODEC interface operations and the reading sequence (Binary data output : sirial output) ACCK SH <SRDYB> (SSCAN) 1 2 INT 4 DRQ DAKB RDB (Counter reset) 3 (DMAFIN) <INTCLR> 5 6 PTIMB <SRDYB>, <INTCLR> : Register setting : Output section (SSCAN), (DMAFIN), (counter reset) : Internal signal SRDYB : ‘L’ is taken in with a ↑ flow of SH, when scanning is started and PTIMB is output. (SSCAN : ‘H’) SRDYB : ‘H’ is taken in with a ↑ flow of ACCK, when the reading of one line ends. (SSCAN : ‘L’) The internal counter reset signal is generated with a ↓ flow of SSCAN, and DRQ is asserted with a ↑ flow of SSCAN. After the internal counter is reset, DMA transfer is started. (The internal counter is counted up by one each time a pixel is transferred.) 5 When the value of the internal counter reaches the output pixel number, DMAFIN shifts to ‘H’, and DRQ is negated with a ↑ flow form DMAFIN and INT is asserted with a ↓ flow of DMAFIN. 6 When CPU is ready for reading the next line, INTCLR is generated and INT is negated, and then SRDYB is set ‘L’. 1 2 3 4 Fig. 3 DMA interface operations and the reading sequence (Multivated data output) 9 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR Table 3 Original sheet reading widths according to the original sheet widths for the sensor widths Table 2 Gate signal ranges for the sensor widths Sensor width Resolution B4 Sensor width A4 Gate signal Uniformity correction range (UNIFG) AGC range (AGCG) AGC mode SCAN mode 200dpi 2103/55 1943/215 400dpi 4207/111 3887/431 200dpi 2103/55 1943/215 400dpi 4207/111 3887/431 200dpi 2018/130 1584/564 400dpi 4037/261 3169/1129 X/Y X : Left end address Y : Right end address 10 Resolution Original sheet width B4 A4 B4 200dpi 2102/54 400dpi 4206/110 A4 200dpi 2102/54 1942/214 400dpi 4206/110 3886/430 When original sheets narrower than the sensor width, cut out the original sheet width with the registers 11 to 14. (OFFSET, OUTLENGTH): (Region designation function) X Y MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR (3) Image processing function ` Peak value detection The M66335 converts image signals input from the image sensor into binary data. This includes the simple conversion of characters and the change of images with various densities into pseudo-halftone. Before the conversion, distortions and characteristic degradations which signals from the image sensor almost always have must be corrected or compensated. Image zone separation must also be performed to realize optimal conversion-to-binary of the image for the possible shortest transmission time. Functions required for image processing are as follows. Peak value detection Uniformity correction Resolution change (enlargement, reduction and averaging) MTF compensation γ correction Background/character level detection (simple conversion to binary) Change to pseudo-halftone Organized dither Error diffusion Image zone separation Designation of regions Because the A/D converter of the M66335 uses the input dynamic range at 2 Vp-p, the reference voltages (VWL, VBL) corresponding to the peak value are fixed. The peak value of analog signals output from the analog processing circuit must be detected before those signals are input to the A/D converter in order to adjust the analog signal peak value to the full-scale value of the converter. The peak value detection is performed by reading white data from the sensor in the AGC mode selected from its three modes (AGC, UNIF and SCAN) of the M66335. As shown in Fig. 4, preprocessing of peak value detection to increase the gain at the gain control is performed for a 8 line cycle and gain control processing to decrease the gain when the A/D converter overflows is performed for another 8 line cycle after the start command (register 00: AGC) in the AGC mode. As a result, the gain changes as shown in Fig. 5. • • • • • • • Peak value detection • • 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Line cycle Preprocessing of peak value detection (increasing the gain) Gain control on the peak value (decreasing the gain) Fig. 4 Peak value detection Preprocessing of peak value detection Gain control on the peak value After the completion of preprocessing of peak value detection VWL After the completion of gain control on the peak value VWL White data The peak value of the sensor output in the line is adjusted to VWL. The output level of the last pixed of the line is adjusted to VWL. VBL VBL One line One line Fig. 5 Changes of the gain in peak value detection 11 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ` Uniformity correction Uniformity correction is to correct shading distortion due to less light at each end of the light source and faded light around the lens, or high frequency distortion due to characteristic variations pixel by pixel in the image sensor. As shown in Fig. 7, the M66335 makes blocks each of two pixels, creates a set of uniformity correction data for each block, and write them to the built-in correction memory (SRAM: 1024 word × 6 bits) in the UNIF mode selected from its three modes (AGC, UNIF and SCAN). The correction data created each for two pixels are read from the built-in correction memory to correct the input image data consecutively in the SCAN mode. With the register 01 (UNIFS) set at “1”, the uniformity is not implemented. With the register 02 (RES) set at “1”, uniformity correction is performed on a block for 4 pixels. For uniformity correction, white correction or the combination of black correction and white correction can be selected according to the types of image sensors as shown in Table 4. This is set in the register 00 (SENS, UMODE) and register 01 (UNIFM). To perform both black correction and white correction, the black correction must be done first. The M66335 implements the correction in the correction range of 50% as shown in Fig. 7. If a set of white correction data is beyond the correction range of 50%, the correction are not exactly performed as shown in Fig. 7. Therefore, ensure that input signals are within the range. Black level High frequency distortion Shading distortion White level 1 line Fig. 6 Waveform of white data output from the image sensor Table 4 Uniformity correction due to the image sensor Register Image Correcsensor tion CCD CIS Creation of uniformity Selection of Type of the sensor correction data correction mode Register 00 (SENS) Register 00 (UMODE) Register 01 (UNIFM) White correction 0 1 0 White correction 1 1 0 1 Period of black correction : 0 Period of white correction : 1 1 Black correction White correction White correction + black correction White correction Analog signal input Analog signal input VWL White data 27–1 VWL 50% 26–1 50% VBL 0 VBL 26–1 0 Black data 1 line 1 line Correction on over-range data (in white correction) VWL Analog signal input White data 27–1 26–1 50% 0 VBL White data over the correction range Section over the correction range 1 line Fig. 7 Uniformity correction 12 White data 27–1 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ● Resolution change ◆ In Resolution change is controlled through H/W in the horizontal scanning direction and through S/W in the vertical scanning direction. The sequence for resolution change is shown in Fig. 8. CNV_D indicates the current line read. “0”: 1 line of data are output. “1”: No line of data are output. the case of reduction ` Horizontal scanning direction ◆ In The scaling factor is written from the register 15 (CNV_D) to the built-in resolution change memory (100W × 1 bit) bit by bit by 100 operations. MSSEL of the register 6 must be set at “0” (which specifies the horizontal scanning direction) before the scaling factor is written in the memory. The procedure to specify CNV_D is as follows. CNV_D indicates the next line read. “0”: 1 line of data are output with PTIM generated (paper driven). “1”: 1 line of data are output with PTIM generated (paper not driven). (Paper not driven: the same line is read again.) ◆ In the case of enlargement the case of reduction Data written in the resolution change memory have the following meaning. “0”: 1 pixel is output. “1”: No pixel is output. (Example of reduction to 75%) 75 0’s and 25 1’s are written in the memory. The intervals of 1’s should be as equal as possible to obtain the image with better quality. ◆ In Resolution change Enlargement/reduction Specifying enlargement/reduction is set in CONVX/CONVY. for horizontal/vertical scanning MSSEL is set at 0. Data setting in CNV_D Setting the scaling factor for resolution change in the (100 bits in quantity) horizontal scanning direction the case of enlargement Data written in the resolution change memory have the following meaning. “0”: 1 pixel is output. “1”: 2 pixels are output. (Example of enlargement to 150%) 50 0’s and 50 1’s are written in the memory. The intervals of 1’s should be as equal as possible to obtain the image with better quality as in the reduction. MSSEL is set at 1. Specifying vertical scanning Setting the scaling factor for Data setting in CNV_D resolution change in the vertical (1 bit in quantity) scanning direction NO ` Vertical scanning direction Processing of lines to implement the scaling factor in the vertical scanning direction is decided for each line through the register. MSSEL of the register 6 must be set at “1” (which specifies the vertical scanning direction), and either “0” or “1” written in the register 15 (CNV_D) before the processing of each line. The timing for this setting is in the period between the first transition of the INT signal (synchronized with that of ACCK) and that of the SH signal (the start of taking the SRDY signal in). The procedure to specify CNV_D is as follows. Specifying horizontal scanning Setting of SRDY Start of reading a single line INT generated? End of reading a single line YES NO Page end? YES END Fig. 8 Sequence of resolution change setting 13 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR Use the PTIMB signal as control signals for the pulse motor for the reading roller. The sequence for reduction is shown in Fig. 9 and that for enlargement in Fig. 10. ACCK SH <SCAN> 1 2 (START) 5 <SRDYB> 3 (SSCAN) 6 INT Reduced line Reduced line 4 STIMB SCLK SVID PTIMB 0 <CNV_D> 1 0 1 0 7 <INTCLR> : Output section <SCAN>, <SRDYB>, <CNV_D>, <INTCLR> : register setting (START), (SSCAN) : internal signals 1 At the initial setting, the enlargement/reduction setting (CNV_D) in horizontal scanning is implemented. Then, after the system is switched into the setting mode for enlargement/reduction in vertical scanning, the first line is set. 2 With a ↓ flow of ACCK, the SCAN command is taken in, when the system comes into the standby mode for SRDYB. (START: ‘H’) 3 With a ↑ flow of SH, SRDYB: ‘L’ is taken in, when scanning starts and PTIMB is output. (SSCAN: ‘H’) 4 During the period that STIMB is at ‘L’, converted binary data are output while the data for reduced lines are not output because STIMB for them are at ‘H’. 5 With a ↑ flow of ACCK, SRDYB: ‘H’ is taken in, when the reading of the single line is completed. (SSCAN: ‘L’) 6 With a ↓ flow of SSCAN, INT is asserted. (INT: ‘H’) 7 With CPU ready for reading the next line, the enlargement/reduction setting (CNV_D) in vertical scanning is implemented; INTCLR is generated; INT is negated; and then SRDYB is set at ‘L’. Fig. 9 Reduction processing sequence ACCK SH <SCAN> (START) 1 2 5 <SRDYB> 3 (SSCAN) 6 INT STIMB Enlarged line Enlarged line 4 SCLK SVID PTIMB <CNV_D> <INTCLR> 0 1 0 1 0 7 : Output section <SCAN>, <SRDYB>, <CNV_D>, <INTCLR> : register setting (START), (SSCAN) : internal signals 1 At the initial setting, the enlargement/reduction setting (CNV_D) in horizontal scanning is implemented. Then, after the system is switched into the setting mode for enlargement/reduction in vertical scanning, the first line is set. 2 With a ↓ flow of ACCK, the SCAN command is taken in, when the system comes into the standby mode for SRDYB. (START: ‘H’) 3 With a ↓ flow of SH, SRDYB: ‘L’ is taken in, when scanning starts and PTIMB is output while it is not output for enlarged lines. (SSCAN: ‘H’) 4 During the period that STIMB is at ‘L’, converted binary data are output. 5 With a ↑ flow of ACCK, SRDYB: ‘H’ is taken in, when the reading of the single line is completed. (SSCAN: ‘L’) 6 With a ↓ flow of SSCAN, INT is asserted. (INT: ‘H’) 7 With CPU ready for reading the next line, the enlargement/reduction setting (CNV_D) in vertical scanning is implemented; INTCLR is generated; INT is negated; and then SRDYB is set at ‘L’. Fig. 10 Enlargement processing sequence 14 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ` MTF compensation As shown in Fig. 11, image data of characters or pictures photoelectrically converted by the sensor unit show degradation in resolution. MTF compensation function of the M66335 restores the resolution of those data and expands the apparent dynamic range by strengthening the high-pass frequency constituent with the Laplacian filter. Photoelectric conversion Photoelectric conversion Original (character) Image signal MTF compensation Data after compensation Photoelectric conversion Original (photo) Image signal MTF compensation Data after compensation Resolution compensation X′ = X + α ((X – A) + (X – B) + (X – C) + (X – D)) where, α : MTF compensation coefficient in the register 08 (MTF_C, MTF_I) In the above equation, α is set according to the register 07 : MODE (selection of conversion-into-binary mode) as follows: MODE : 00 (simple binary) α = MTF_C MODE : 01 (organized dither) α = MTF_I MODE : 10 (image zone separation) separation (character) α = MTF_C for image zone separation (photo) α = MTF_I for image zone MODE : 11 (error diffusion) α = MTF_I Fig. 11 MTF compensation 15 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ` γ correction γ correction according to the sensitivity characteristics (logarithmic characteristics) of human eyes is implemented to approximate the image data to natural images. To do this, the M66335 writes the γ correction table to the built-in SRAM and read the corrected values corresponding to read image data values from the SRAM. γ = 0.45 is considered to be the optimal for γ correction for thermal head printers. Fig. 12 shows a characteristics example at γ = 0.45. γ correction processing is set through the register 06 : GAMMA as follows. 6 Image data A <5,0> DO <5,0> (Address) (Output) γ correction memory 6 Data after γ correction γ=1 γ = conversion table value γ = 1 for image zone separation (character) γ = conversion table value for image zone separation (photo) GAMMA : 11 γ = conversion table value for image zone separation (character) γ = 1 for image zone separation (photo) For the procedures of inputting/outputting of data, refer to the section on writing to/reading from the γ correction memory. GAMMA : 00 GAMMA : 01 GAMMA : 10 1.0 White 63 Image data after γ correction (memory output) 56 DOUT 47 γ = 0.45 34 γ=1 25 0 Dlow Dup DIN IF(DIN < Dlow) DOUT = 0 Black 0 Black : 0 8 16 32 48 Image data (address) Fig. 12 γ correction by means of the conversion table 16 White : 63 IF(Dlow ≤ DIN < Dup) γ DOUT = DIN-Dlow Dup-Dlow ( IF(Dup ≤ DIN) DOUT = 1.0 ) 1.0 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ` Background/character level detection The M66335 uses not the fixed threshold system but the floating threshold system, where the optimal threshold for simple conversionto-binary of objective pixels are continually generated by constantly detecting background/character levels. Accordingly, the threshold value proper for image data is generated without processing the data. The threshold value is used for the areas to be converted to binary when simple conversion-to-binary or image zone separation is selected as the mode of conversion to binary in reading data. : register 07 (MODE) Background level counter When image data greater (lighter in light) than the current value are input, this counter counts up to approximate to the data. When image data smaller (darker in light) than the current value are input, this counter counts down to approximate to the data. Setting of the rate of count-up/count-down following data input : register 0C (MAX_UP, MAX_DOWN) Setting of the lowest limit for background levels : register 0E (LL_MAX) Character level counter When image data greater (lighter in light) than the current value are input, this counter counts up to approximate to the data. When image data smaller (darker in light) than the current value are input, this counter counts down to approximate to the data. Setting of the rate of count-down following data input : register 0C (MIN_UP) Setting of the highest limit for character levels : register 0D (UL_MIN) Background level detection counter Image data Generation of the threshold value Comparison Converted binary data Character level detection counter This slope is decided through MAX_UP. This slope is decided through MAX_DOWN. Fixing of the background level White level Background level Lowest limit of the background level (LL_MAX) Threshold level Input data Highest limit of the character level (UL_MIN) Character level This slope is decided through MIN_UP. Fixing of the character level Black level Threshold level = (background level point – character level) × K + character level K = threshold factor for conversion to binary: register 07 (SLICE) Lowest limit of the background level (LL_MAX) > highest limit of the character level (UL_MIN) Fig. 13 Background/character levels 17 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ` Error diffusion • Organized dither The M66335 has built-in SRAM with a configuration of 64 words × 6 bits for organized dither memory. In the initial setting, write the threshold value proper for the preferred dither pattern to the dither memory after setting the dither matrix size. : register 07 (DITH) : register 10 (DITH_D) An example of dither patterns is shown in Fig. xx. For the procedure of inputting/outputting data, refer to the section on writing to/reading from the dither memory. The error diffusion, which is a conditional determination method, locally diffuses density errors between the original image and the result to obtain the best approximation. This generates images with good compatibility of gradation and resolution. This is operated by selecting the error diffusion in conversion-intobinary mode selection. : register 07 (MODE) In error diffusion, dithers as well as density errors are added to image data. The dithers are data as commonly used for the dither matrix. : register 08 (ERROR) γ correction must be performed in the error diffusion. Dither matrix –32 m 17 9 12 20 25 10 11 8 15 19 2 5 m K2 Fmn Fmn Gmn n n Integrated error ΣαklEm–k, n–1 (Note 2) K1 Weighting of the error filter αkl 1 2 2 4 4 + – 2 1 Fmn > 32 → Gmn = 63 (white) Fmn < 32 → Gmn = 0 (black) Error Emn = Fmn – Gmn (Note 1) Note 1: Characterized by using the difference from the corrected value Fmn rather than that from the original pixel Fmn. Error buffer memory Preceding line 2: Errors before the point of remark are integrated. Current line Fmn = Fmn + K1 (1/Σαkl) ΣαklEm–k, n–1 + K2 (dither –32) k,1 k,1 K1 = register 08 (error) K2 = register 08 (dither addition factor) Fig. 14 Error diffusion method 18 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ` Image zone separation To make data conversion fit for each image zone, a black and white image is separated into the zones to be converted to binary and the gradation zones. The binary zone is processed through simple con- version to binary and the gradation zone through the error diffusion. : register 08 to 0E In the black and white image, each window of the gradation zone (photo) does not have a large difference of luminance in it. With this characteristic of the gradation zone, it is distinguished from the conversion-into-binary zone through the following method. Lmax: maximum illumination in window Lmin : minimum illumination in window Determining inequality 1: Lmax – Lmin>A (because the zone to be converted to binary has a large difference in luminance in it.): register 09 Difference (SEPA_A) Determining inequality 2: Lmin>B (for the wholly white area): register 0A Minimum (SEPA_B) Determining inequality 3: Lmax<C (for the wholly black area): register 0B Maximum (SEPA_C) If the window satisfies determination inequalities 1, 2 or 3, simple conversion to binary is applied. If the window does not satisfy any of determination inequalities 1, 2 and 3, change to pseudo-halftone is applied. White level = 63 Difference Minimum Lm i n Maximum Lmax A Input data B C Lm i n Black level = 0 Lmax–Lm i n Lmax Fig. 15 Image zone separation 19 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ` Region designation function The sensor width is fixed for A4 and B4. The region designation function is to output only the data for a region defined and designated in terms of output data after resolution change (or after uniformity correction for multivalued data). Registers 11 to 14 (OFFSET, OUTLENGTH) Output width Designated region OFFSET Fig. 16 Cut-out function 20 OUTLENGTH MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR (4) CODEC interface (Binary data output) Serial output SRDYB SH A B STIMB 10 4 12 (Equal scale, reduced scale) SCLK 2 2 10 SVID 4 4 4 4 (Enlarged scale) SCLK 2 2 2 SVID Unit : 1/SYSCK Note: A is decided through the registers 05 (ST_PL) 11 and 12 (OFFSET), and B through the registers 13 and 14 (OUTLENGTH). Parallel output Pixel 1 2 3 4 5 N N+1 N+2 N+3 N+4 6 7 8 SCLK SVID N–1 N+5 N+6 N+7 N+8 DRQ DAK RD D0 N–1 D1 N–2 D2 N–3 D3 N–4 D4 N–5 D5 N–6 D6 N–7 D7 N–8 Note: The 3-line handshake of SRDY, SH and STIM, which is the interface with CODEC, is the same as serial output. 21 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR (5) DMA interface (multivalued output) The DMA transfer of data after non-uniformity correction can be performed by setting P_O) of the register 01: at “1” (existence of DMA output) and M_B of that register at “1” (multivalue). With this setting, neither enlargement, nor reduction, nor 400 dpi of resolution can be set. SSCAN DRQ 2 (DMA counter reset signal) 1 4 DAKB RDB 3 (DMA counter signal) (DMAFIN) INT 5 6 D<7 : 2> (XXXX): internal signal On completion of reading one line, with a ↓ flow of SSCAN, the reset signal is entered in the DMA counter. With a ↑ flow of the reset signal, DRQ shifts to ‘H’, when the DMA transfer becomes ready. With DAKB at ‘L’ and a ↓ flow of RDB, DRQ shifts to ‘L’, when multivalued data are output to D <7 : 2> during the period that RDB is at ‘L’. With a ↑ flow of DAKB, the DMA counter counts up and DRQ shifts to ‘H’, when the DMA transfer becomes ready again. The cycle of the above 3 and 4 is repeated until the DMA counter counts up to reach the number of output pixels set in the registers 13 and 14 OUTLENGTH subtracted by one. By that repetitive operation, DMAFIN shifts to ‘H’ to terminate the DMA transfer when it reaches the set number. 6 With a ↓ flow of DMAFIN, INT shifts to ‘H’, when CPU has an interrupt. 7 Reading is resumed from the next line by negating the INT signal through the register 17 (INTCLR). 1 2 3 4 5 22 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR (6) Writing to/reading from the dither memory, γ correction memory, uniformity correction memory, and resolution change memory The sequences of writing a dither pattern to and reading it from SRAM with a configuration of 64 words × 6 bits which is built in the M66335 for organized dither are shown below. Writing to the dither memory (MPU → M66335) Initial setting (1) Initial setting (2) Memory address (0) Memory address (1) 07H 01H 10H 10H CSB A4 ~ A0 ~ WRB D7 ~ D0 (Input) D6,D5 D0=“1” DATA (0) DATA (1) 1 2 3 3 Initial setting (1) Initial setting (2) Memory address (0) Memory address (1) 07H 01H 10H 10H Reading from the dither memory (M66335 → MPU) CSB A4 ~ A0 ~ WRB D7 ~ D0 (Input) D6,D5 D0=“1” RDB D7 ~ D0 (Output) 1 2 DATA (0) DATA (1) 4 4 1 D6 and D5 (DITH) of the register 07 are set to define the dither matrix size. 2 D0 (CNTRST) of the register 01 is set at “1” to reset the address counter of the dither memory. 3 DITH_D is selected in the register 10, and DATA (0) of the MPU bus (D5 to D0) is written in the memory. The address counter of the dither memory is incremented at the edge of the first transition of WR. (For writing) 4 DITH_D is selected in the register 10, and DATA (0) of the dither memory is read into the MPU bus (D5 to D0). The address counter of the dither memory is incremented at the edge of the first transition of RD. (For reading) Dither matrix addresses A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 4 × 4 matrix A0 A4 A8 A12 A16 A20 A24 A28 A1 A2 A3 A5 A6 A7 A9 A10 A11 A13 A14 A15 A17 A18 A19 A21 A22 A23 A25 A26 A27 A29 A30 A31 4 × 8 matrix A0 A8 A16 A24 A32 A40 A48 A56 A1 A9 A17 A25 A33 A41 A49 A57 A2 A3 A4 A5 A10 A11 A12 A13 A18 A19 A20 A21 A26 A27 A28 A29 A34 A35 A36 A37 A42 A43 A44 A45 A50 A51 A52 A53 A58 A59 A60 A61 8 × 8 matrix A6 A14 A22 A33 A38 A46 A54 A62 A7 A15 A23 A31 A39 A47 A55 A63 23 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR The sequences of writing γ correction table to and reading it from SRAM with a configuration of 64 words × 6 bits which is built in the M66335 for γ correction are shown below. Writing to the γ correction memory (MPU → M66335) Initial setting (1) Memory address (0) Memory address (1) 01H 0FH 0FH CSB A4 ~ A0 ~ WRB D7 ~ D0 (Input) D0=“1” DATA (0) DATA (1) 1 2 2 Initial setting (2) Memory address (0) Memory address (1) 01H 0FH 0FH Reading from the γ correction memory (M66335 → MPU) CSB A4 ~ A0 ~ WRB D7 ~ D0 (Input) D0=“1” RDB D7 ~ D0 (Output) 1 DATA (0) DATA (1) 3 3 1 D0 (CNTRST) of the register 01 is set at “1” to reset the address counter of the γ correction memory. 2 GAMMA_D is selected in the register 0F, and DATA (0) of the MPU bus (D5 to D0) is written in the memory. The address counter of the γ correction memory is incremented at the edge of the first transition of WRB. (For writing) 3 GAMMA_D is selected in the register 0F, and DATA (0) of the γ correction memory is read into the MPU bus (D5 to D0). The address counter of the γ correction memory is incremented at the edge of the first transition of RDB. (For reading) 24 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR Uniformity correction data can be written to and read from SRAM for uniformity correction built in the M66335 through the MPU bus. With this operation, the uniformity data can be temporarily saved in the backup memory when the power is off. The sequences of writing and reading uniformity correction data are shown below. Writing to the uniformity correction memory (MPU → M66335) Initial setting (1) Initial setting (2) Memory address (0) Memory address (1) 00H 01H 19H 19H CSB A4 ~ A0 ~ WRB D7 ~ D0 (Input) D1 D0=“1” DATA (0) DATA (1) 1 2 3 3 Reading from the uniformity correction memory (M66335 → MPU) Initial setting (1) Initial setting (2) Memory address (0) Memory address (1) 00H 01H 19H 19H CSB A4 ~ A0 ~ WRB D7 ~ D0 (Input) D1 D0=“1” RDB D7 ~ D0 (Output) 1 2 DATA (0) DATA (1) 4 4 1 “0” (black correction) or “1” (white correction) is set in D1 (Umode) of the register 00. 2 D0 (CNTRST) of the register 01 is set at “1” to reset the address counter of the uniformity correction memory. 3 UNIF_D is selected in the register 19, and DATA (0) of the MPU bus (D5 to D0) is written in the memory. The address counter of the uniformity correction memory is incremented at the edge of the first transition of WRB. (For writing) 4 UNIF_D is selected in the register 19, and DATA (0) of the uniformity correction memory is read into the MPU bus (D5 to D0). The address counter of the uniformity correction memory is incremented at the edge of the first transition of RDB. (For reading) 25 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR The sequences of writing a resolution change table to and reading it from SRAM with a configuration of 100 words × 1 bit which is built in the M66335 for resolution change are shown below. Writing to the resolution change memory (MPU → M66335) Initial setting (1) Initial setting (2) Memory address (0) Memory address (1) 06H 01H 15H 15H CSB A4 ~ A0 ~ WRB D7 ~ D0 (Input) D7=“0” D0=“1” DATA (0) DATA (1) 1 2 3 3 Reading from the resolution change memory (M66335 → MPU) Initial setting (1) Initial setting (2) Memory address (0) Memory address (1) 06H 01H 15H 15H CSB A4 ~ A0 ~ WRB D7 ~ D0 (Input) D7=“0” D0=“1” RDB D7 ~ D0 (Output) 1 2 DATA (0) DATA (1) 4 4 1 “0” (horizontal scan) is set in D7 (MSSEL) of the register 06. 2 D0 (CNTRST) of the register 01 is set at “1” to reset the address counter of the resolution change memory. 3 CNV_D is selected in the register 15, and DATA (0) of the MPU bus (D0) is written in the memory. The address counter of the resolution change memory is incremented at the edge of the first transition of WRB. (For writing) 4 CNV_D is selected in the register 15, and DATA (0) of the resolution change memory is read into the MPU bus (D0). The address counter of the resolution change memory is incremented at the edge of the first transition of RDB. (For reading) 26 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR List of the M66335FP registers R/W A4 ~ A0 Default D7 D6 D5 D4 D3 D2 D1 D0 R/W 00H 00H RESET SENS SENS_W AGC UNIF SCAN UMODE “L” R/W 01H 00H SOURCE S/H_W SH_W UNIFS P_O M_B UNIFM CNTRST W 02H 00H RES LCMPS BLS BLCMPS CCD CIS3 CIS2 CIS1 W 03H 00H W 04H 00H W 05H 00H W 06H 00H MSSEL W 07H 00H POL W 08H 00H W 09H 00H SEPA_A (5 : 0) W 0AH 00H SEPA_B (5 : 0) W 0BH 00H W 0CH 00H W 0DH 1FH UL_MIN <5 : 0> W 0EH 20H LL_MAX <5 : 0> R/W 0FH – GAMMA_D (5 : 0) R/W 10H – DITH_D (5 : 0) W 11H 00H W 12H 00H W 13H 00H W 14H 00H W 15H – R/W 16H 00H PRE_DATA (7 : 0) PRE_DATA (13 : 8) ST_PL (7 : 0) AVE CONVY <1 : 0> CONVX <1 : 0> DITH <1 : 0> MODE <1 : 0> GAMMA <1 : 0> SLICE <2 : 0> MTF_C <1 : 0> ERROR <1 : 0> MTF_I <1 : 0> SEPA_C (5 : 0) MAX_UP <1 : 0> MAX_DOWN <1 : 0> MIN_UP <1 : 0> OFFSET <7 : 0> OFFSET <12 : 8> OUTLENGTH <7 : 0> OUTLENGTH <12 : 8> CNV_D AGCSTP W 17H – INTCLR R/W 18H 00H GAIN <7 : 0> R/W 19H 00H SRDYS SRDYB UNIF_D <5 : 0> 27 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR Register structure Address 00H R/W R/W Description D7 D6 D5 D4 D3 D2 D1 D0 RESET SENS SENS_W AGC UNIF SCAN UMODE “L” D7 RESET : system reset 0 Normal mode 1 Reset mode D6 SENS : sensor type CCD 1 CIS: (75% of clock duty) D5 SENS_W : reading width of the sensor 0 A4 1 B4 D4 AGC : AGC mode 0 Stop 1 Start D3 UNIF : UNIF mode 0 Stop 1 Start D2 SCAN : SCAN mode 0 Stop 1 Start 28 With D7 = 1, the system is reset during the period that the write pulse is “L”. (∗) Write only 0 D1 01H ● (Default value: 00H) ● Controls start/stop of the AGC mode. ● Controls start/stop of the UNIF mode. ● Controls start/stop of the SCAN mode. UMODE : uniformity correction in the UNIF mode Black correction + white correction Only white correction 0 Black correction – 1 White correction White correction R/W D7 D6 D5 D4 D3 D2 D1 D0 SOURCE S/H_W SH_W UNIFS P_O M_B UNIFM CNTRST (Default value : 00H) D7 SOURCE : reading width of the original D6 S/H_W : S/W pulse width 0 A4 0 Normal (quadruple the system clock cycle) 1 B4 1 Normal multiplied by 0.5 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR Address R/W 01H R/W 02H W Description D5 SH_W : SH pulse width 0 Normal (16 times the system clock cycle) 1 Reverse of normal multiplied by 2 D4 UNIFS : uniformity correction 0 Valid 1 Invalid D3 P_O : DMA output 0 Without DMA output 1 With DMA output D2 M_B : processing mode 0 Binary 1 Multivalue D1 UNIF : uniformity correction in SCAN 0 White correction 1 Black correction + white correction D0 CNTRST : address counter reset 0 Normal mode 1 Reset mode ● D0 is output in the form of LSB and D7 in the form of MSB. ● With the multivalue selected, data (6 bit) after nonuniformity correction can be output through the DMA transfer. ● With D0 = 1, the counter is reset during the period that the write pulse is “L”. ● All the built-in RAM addresses are reset. (∗) Write only D7 D6 D5 D4 D3 D2 D1 D0 RES LCMPS BLS BLCMPS CCD CIS3 CIS2 CIS1 (Default value : 00H) D7 RES : resolution D6 LCMPS : line clamping 0 200dpi 0 Invalid 1 400dpi 1 Valid D5 BLS : bit clamping 0 Invalid 1 Valid D4 BLCMPS : black level line clamping 0 Invalid 1 Valid D3 D2 D1 D0 Sensors compatible with image sensor interfaces 0 0 0 1 CIS1 : sensors with the input level of 2V or higher 0 0 1 0 CIS2 : sensors with the input level of under 2V 0 1 0 0 CIS3 : sensors capable of line clamping 1 0 0 0 CCD 29 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR Address R/W 03H W Description D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) PRE_DATA <7 : 0> D7 to D0 : PRE_DATA <7 : 0> the lowest order 8 bits of the single-line cycle counter value 04H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) PRE_DATA <13 : 8> D5 to D0 : PRE_DATA <13 : 8> the highest order 6 bits of the single-line cycle counter value 05H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) ST_PL <7 : 0> D7 to D0 : ST_PL <7 : 0> start pulse position to the sensor ● 06H 30 Set ST_PL = (dummy pixels of the sensor + 2). W D7 D6 MSSEL AVE D5 D4 D3 CONVX D7 MSSEL : horizontal and vertical setting 0 Horizontal 1 Vertical D6 AVE : averaging processing 0 With averaging 1 Without averaging D2 CONVY ● D1 D0 GAMMA (Default value : 00H) When “with averaging” selected : For enlargement : inserted lines are the average of the preceding one and the current one; and For reduction : the subsequent lines from removed lines are the average of the removed one and the current one. D5 D4 CONVX : enlargement/reduction mode in the horizontal scanning direction 0 0 Original scale 0 1 Enlargement 1 0 Reduction 1 1 D3 D2 CONVY : enlargement/reduction mode in the horizontal scanning direction 0 0 Original scale 0 1 Enlargement 1 0 Reduction 1 1 ● RES = 1 With the setting of 400dpi, enlargement cannot be set. MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR Address R/W 06H W Description GAMMA : γ correction processing D1 D0 0 0 0 1 Character, photo : γ = download value 1 0 Character : γ = 1; photo : γ = download value 1 1 Character : γ = download value ; photo : γ = 1 Character, photo : γ = 1 Note: Judgment between character and photo is based on the result of image zone separation. 07H D7 W D6 POL D5 D4 DITH D3 D2 MODE D7 POL : conversion-to-binary output mode 0 White : 1; black : 0 1 White : 0; black : 1 D6 D5 DITH : dither matrix size 0 0 4×4 0 1 4×8 1 0 8×8 1 1 – D4 D3 MODE : selection of the conversion-to-binary mode 0 0 Simple binary 0 1 Organized dither 1 0 Image zone separation (simple binary + error diffusion) 1 1 Error diffusion D2 D1 D0 0 0 0 6/16 0 0 1 7/16 0 1 0 8/16 0 1 1 9/16 1 0 0 10/16 1 0 1 11/16 1 1 0 12/16 1 1 1 13/16 D1 SLICE D0 (Default value : 00H) SLICE : threshold factor for conversion to binary 31 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR Address R/W 08H W Description D7 D6 D5 D4 D3 ERROR D5 D4 0 D2 D1 MTF_C D0 (Default value : 00H) MTF_I ERROR Error (base) Rate of dither addition to errors 0 Strong (7/8) Weak (1/8) 0 1 Strong (7/8) Strong (1/4) 1 0 Weak (3/4) Weak (1/8) 1 1 Weak (3/4) Strong (1/4) D3 D2 MTF_C : MTF compensation factor 0 0 1/4 0 1 1/2 1 0 1 1 1 0 Note: This is valid when MODE is simple binary or image zone separation (character). D1 D0 MTF_I : MTF compensation factor 0 0 1/4 0 1 1/2 1 0 1 1 1 0 Note: This is valid when MODE is organized dither, error diffusion or image zone separation (photo). 09H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) SEPA_A D5 to D0 : SEPA_A Image zone separation parameter (differential) 0AH W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) SEPA_B D5 to D0 : SEPA_B Image zone separation parameter (minimum) 0BH W D7 D6 D5 D4 D3 D2 SEPA_C D5 to D0 : SEPA_C Image zone separation parameter (maximum) 32 D1 D0 (Default value : 00H) MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR Address R/W 0CH W Description D7 D6 D5 D4 D3 MAX_UP 0DH W D2 MAX_DOWN D5 D4 MAX_UP : background level detection Clock for the up counter 0 0 Ordinary (T = (single pixel cycle) × 32) 0 1 Slow (T = (single pixel cycle) × 64) 1 0 Fast (T = (single pixel cycle) × 16) 1 1 Fastest (T = (single pixel cycle) × 8) D3 D2 MAX_DOWN : background level detection Clock for the down counter 0 0 Ordinary (T = (single pixel cycle) × 128) 0 1 Slow (T = (single pixel cycle) × 256) 1 0 Fast (T = (single pixel cycle) × 64) 1 1 Fastest (T = (single pixel cycle) × 32) D1 D0 MIN_UP : character level detection Clock for the up counter 0 0 Ordinary (T = (single pixel cycle) × 128) 0 1 Slow (T = (single pixel cycle) × 256) 1 0 Fast (T = (single pixel cycle) × 64) 1 1 Fastest (T = (single pixel cycle) × 32) D7 D6 D5 D4 D3 D2 D1 D0 MIN_UP D1 (Default value : 00H) D0 (Default value : 1FH) UL_MIN D5 to D0 : UL_MIN Detection of background/character levels Highest limit of character levels 0EH W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 20H) LL_MAX D5 to D0 : LL_MAX Detection of background/character levels Lowest limit of background levels Lowest limit of background levels (LL_MAX) > highest limit of character levels (UL_MIN) 0FH R/W D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 GAMMA_D <5 : 0> D5 to D0 : GAMMA_D Built-in γ memory data 10H R/W D7 D6 D5 D4 D3 D2 DITH_D <5 : 0> D5 to D0 : DITH_D Built-in dither memory data 33 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR Address R/W 11H W Description D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) OFFSET <7 : 0> D7 to D0 : OFFSET <7 : 0> Offset for cut-out Lowest order 8 bits 12H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) OFFSET <12 : 8> D3 to D0 : OFFSET <12 : 8> Offset for cut-out Highest order 5 bits 13H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) OUTLENGTH <7 : 0> D7 to D0 : OUTLENGTH <7 : 0> No. of output pixels Lowest order 8 bits 14H W D7 D6 D5 D4 D3 D2 D1 D0 (Default value : 00H) OUTLENGTH <12 : 8> D3 to D0 : OUTLENGTH <12 : 8> No. of output pixels Highest order 5 bits Note: OUTLENGTH <12 : 8> must be a multiple of 8. If a number of output pixels is not a multiple of 8, the remainder of the division must be omitted. 15H R/W D7 D6 D5 D4 D3 D2 D1 D0 CNV_D D0 : CNV_D Indication of enlargement/reduction 34 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR Address R/W 16H R/W Description D7 D6 D5 D4 D3 D2 D1 AGCSTP SRDYS D2 AGCSTP : gain control counter 0 Gain control counter valid. 1 Gain fixed. D1 17H D0 (Default value : 00H) SRDYB SRDYS : SRDY control 0 SRDY control through the register 1 SRDY control through the external pin D0 SRDYB : data transfer start ready. 0 Transfer allowed. 1 Transfer not allowed. ● In the case of data control through the register, the SDRYB input pin must be always set at “H”. For the control through the register, the SRDY register must be controlled line by line. ( ) Write only ∗ W D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 INTCLR INT signals are negated by accessing to this address. 18H R/W D7 D6 D5 D4 D3 GAIN <7 : 0> In reading : the current gain value of the gain control counter can be read. In writing : the gain value of the gain control counter can be set. However, this is valid only if AGCSTP = 1. 19H R/W D7 D6 D5 D4 D3 D2 D1 D0 ● With UMODE = 0, access to the uniformity correction memory for black correction is available. ● With UMODE = 1, access to the uniformity correction memory for white correction is available. UNIF <5 : 0> D5 to D0 : UNIF_D Built- in uniformity correction memory data 35 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR Description of the Operations of the Analog Circuits The configuration of the analog processing circuits is shown in Fig. 17. (1) Sensor selection circuit The four types of sensors in the table can be connected to the circuit. Register 02H Sensor type CCD CCD sensor CIS1 CIS sensor which outputs light voltages (white voltage) of 3.5V or lower CIS2 CIS sensor which outputs light voltages (white voltage) of 2V or lower CIS3 CIS sensor which output shielding pixels for each line <CCD mode> Black Max.500mVpp. White Blanking element Shielding pixel part Signaling element The amplitudes of sensor signals are multiplied by –4 through the two operating amplifiers directly after the switch to select the CCD mode. (The waveforms of the signals are inverted at the same time.) As a result, the sensor signals input to the sample and hold circuit have a dark voltage of 2.2V. Effective pixel part <CIS1 mode> The amplitude of signals input from the sensor are halved. Then, their reference potential is shifted up to 2.2V. As a result, the sensor signals input to the sample and hold circuit have a dark voltage of 2.2V. White Max.3.5V Black ±200mV Signaling element <CIS2 mode> The reference potential of signals input from the sensor is shifted up to 2.2V. As a result, the sensor signals input to the sample and hold circuit have a dark voltage of 2.2V. White Max.2V Black ±200mV Signaling element <CIS3 mode> Sensor signals with a dark voltage of 2.2V clamped by line clamping input are directly input to the sample and hold circuit. White 2Vpp. Black Clamping level Shielding pixel part 36 Signaling element Effective pixel part MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR (2) Line clamping circuit (6) Black level clamping circuit This circuit is used for CCD (line clamping mode) and CIS3. The reference voltage (dark voltage) output in the shielding pixel part of the sensor is sampled by LCMP (line clamping pulses) and shifted up to the internal reference voltage of 2.2V. This is not used for the CIS1 or CIS2 input sensor (set off constantly). : register 02 (LCMPS) This circuit adjust the level of reference voltage to the A/D converter from analog circuits. The black clamping circuit is used in the CCD or CID3 mode. (See Figs. 18, 19 and 22) The GCAO pin and the BCMI pin are capacitycoupled. The output reference potential in the shielding pixel part of sensor signals are applied to the BCMV pin as the VBL (black level reference voltage of 1.8V) for the A/D converter. BLCMP (black level clamping pulses) are generated concurrently with the shielding pixel part of each line. To turn off this circuit, set BLCMPS invalid and apply the black level reference voltage of the A/D converter to the BCMV pin. : register 02 (BLCMPS) In the CIS1 or CIS2 mode, the LEVAJ pin is used. (See Figs. 20 and 21) Voltage is applied to the LEVAJ pin so that the reference potential of output at the GCAO pin can be adjusted to the VBL (black level reference voltage of 1.8V) of the A/D converter. Set voltage input to the LEVAJ pin as follows. VLEVAJ = VVBL – A × GV + 0.2 [V] VGCAO = VLEVAJ + GV × VIN [V] where, A: the lowest limit of dark voltage of the sensor [V] GV: gain (multiplying factor) of the gain control circuit VIN: signals input from the sensor [V] (3) Sample and hold circuit and bit clamping circuit In the CCD mode, bit clamping, as well as line clamping, can be performed. The blanking elements of each pixel of sensor output is sampled by BTCMP (bit clamping pulses). The differences of signals from the reference potential sampled by the bit clamping circuit are input to the gain control circuit of next step as signaling elements. To turn off bit clamping, set BLS invalid, so that the reference potential will be fixed at the internal reference potential of 2.2V. : register 02 (BLS) (4) Gain control circuit The amplifying factor (gain) must be adjusted so that the amplitudes of sensor signals can come within the dynamic range of the A/D converter. The gain is set through the automatic gain control in the AGC mode (register 00) or directly through the register 18 (GAIN <7 : 0>). The gain changes within the following ranges according to the sensor used. Mode Amplifying factor of signals (gain) CCD 4 to 20 CIS1 0.5 to 2.5 CIS2 1 to 5 CIS3 1 to 5 In the AGC mode, the gain control counter is set at the greatest gain in the initial state and then counted down each time an overflow bit is output from the A/D converter. The count (gain) of the gain control counter is directly read/written through the register 18 (GAIN <7 : 0>). The counting operation of the counter can be controlled through the register 16 (AGCSTP). (5) Internal reference voltage Internal reference voltage source for the analog circuits: this generates the reference voltage (2.2V) for the line clamping circuit, the sample and hold circuit, and the bit clamping circuit. A/D converter reference voltage generation circuit: this generates VWL (white level reference voltage of 3.8V) and VBL (black level reference voltage of 1.8V) for the A/D converter. 37 38 AIN LCMP AIN Fig. 17 Circuit Configuration of the Analog Part of the M66335FP MCCD – + MCIS3 MCIS2 Level shift circuit(2.2V) MCIS1 AGND DGND GND AGND – + MCIS<3:1>,MCCD Input clamping circuit + – AVDD AVCC DVCC VCC + – – + 2.2V Bit clamping circuit – + 8 + – Vri- VBL VWL 3.8V VVBL=1.8 [V] Vri+ 1.8V – + – + Gain control circuit GCA Black level clamping circuit AGCSEL <7:0> – + C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO BCMI BCMO ADIN VriAVCC Vref- Vri+ DVCC + – Vref+ AGND DGND VREFH OF VREFL B <7:1> ADIN A/D converter ADCK RESET + – Reference voltage generating circuit for the A/D converter Internal reference voltage source for the analog circuits – + Sample and hold circuit S/H BTCMPBLS GCAO LEVAJ BCMV C1C2 GND OF DIN<6:0> Digital circuit LCMP MCIS<3:1>,MCCD S/H BTCMP BLS BLCMP RESET ADCK GAIN<7:0> VCC MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ANALOG CIRCUIT TIMING CHART (FOR CCD MODE/BIT CLAMPING) Register Mode CCD (bit clamping) Address 00H Bit D6 D6 D5 D4 D3 D2 D1 D0 Signal SENS LCMPS BLS BLCMPS CCD CIS3 CIS2 CIS1 Setting 1 1 1 1 1 0 0 0 Non-signaling part 02H Shielding pixel part Effective pixel part SH CK1 CCD signal output LCMP BTCMP S/H GCAO signal output BLCMP BCMO signal output A/D clock A/D output Non-signaling part 2 Shielding pixel part Unit : 1/SYSCK Effective pixel part 2 SH 12 16 CK1 CCD signal output N 16 3 4 9 LCMP 16 BTCMP 13 16 S/H 3 4 GCAO signal output BLCMP BCMO signal output 1 2 9 N 8 8 N A/D clock A/D output N 39 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ANALOG CIRCUIT TIMING CHART (FOR CCD MODE/LINE CLAMPING) Address 00H Bit D6 D6 D5 D4 D3 D2 D1 D0 Mode Signal SENS LCMPS BLS BLCMPS CCD CIS3 CIS2 CIS1 CCD (line clamping) Setting 1 1 0 1 1 0 0 0 Register Non-signaling part 02H Shielding pixel part Effective pixel part SH CK1 CCD signal output LCMP BTCMP=“H” S/H GCAO signal output BLCMP BCMO signal output A/D clock A/D output Non-signaling part SH 2 Shielding pixel part Effective pixel part Unit : 1/SYSCK 2 12 16 CK1 CCD signal output N 16 3 4 9 LCMP BTCMP=“H” 16 S/H 3 4 GCAO signal output 9 N 8 8 BLCMP BCMO signal output N A/D clock A/D output 40 N MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ANALOG CIRCUIT TIMING CHART (FOR CIS1 MODE) Address 00H Bit D6 D6 D5 D4 D3 D2 D1 D0 Mode Signal SENS LCMPS BLS BLCMPS CCD CIS3 CIS2 CIS1 CIS1 Setting 0 0 0 0 0 0 0 1 Register 02H SH CK1 CIS signal output LCMP=“H” BTCMP=“H” S/H GCAO signal output A/D clock A/D output Unit : 1/SYSCK SH 16 CK1 10 4 2 CIS signal output 16 N LCMP=“H” BTCMP=“H” 16 7 S/H 4 GCAO signal output 1 N A/D clock A/D output N 41 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ANALOG CIRCUIT TIMING CHART (FOR CIS2 MODE) Address 00H Bit D6 D6 D5 D4 D3 D2 D1 D0 Mode Signal SENS LCMPS BLS BLCMPS CCD CIS3 CIS2 CIS1 CIS2 Setting 0 0 0 0 0 0 1 0 Register 02H SH CK1 CIS signal output LCMP=“H” BTCMP=“H” S/H GCAO signal output A/D clock A/D output Unit : 1/SYSCK SH 16 CK1 10 4 2 CIS signal output 16 N LCMP=“H” BTCMP=“H” 16 7 S/H 4 GCAO signal output 1 N A/D clock A/D output 42 N MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ANALOG CIRCUIT TIMING CHART (FOR CIS3 MODE) Address 00H Bit D6 D6 D5 D4 D3 D2 D1 D0 Mode Signal SENS LCMPS BLS BLCMPS CCD CIS3 CIS2 CIS1 CIS3 Setting 1 1 0 1 0 1 0 0 Register Non-signaling part 02H Shielding pixel part Effective pixel part SH CK1 CIS signal output LCMP BTCMP=“H” S/H GCAO signal output BLCMP BCMO signal output A/D clock A/D output Non-signaling part SH Shielding pixel part Unit : 1/SYSCK Effective pixel part 16 CK1 CIS signal output 10 4 16 2 N LCMP 4 1 BTCMP=“H” 16 7 S/H 4 GCAO signal output 1 N 8 8 BLCMP BCMO signal output N A/D clock A/D output N 43 44 AIN LCMP M a x .500mVpp. – + – + AGND DGND GND AGND Input clamping circuit MCCD MCIS3 MCIS2 Level shift circuit(2.2V) MCIS1 – + + – 8 Vri- Vri+ 3.8V VBL VWL 1.8V GCA – + Gain control circuit – + Black level clamping circuit AGCSEL <7:0> + – C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO BCMI BCMO BCMV=VBL GCAO LEVAJ BCMV C1C2 0.1µF ADIN VriAVCC Vref- Vri+ DVCC + – Vref+ AGND DGND VREFH OF VREFL B <7:1> ADIN A/D converter ADCK RESET + – Reference voltage generating circuit for the A/D converter + – Internal reference voltage source for the analog circuits – + Bit clamping circuit – + Sample and hold circuit S/H BTCMPBLS 2.2V MCIS <3:1>, MCCD H Fig. 18 External pin connections of the analog part (for the CCD mode/bit clamping) Signaling element Blanking element White Black AIN Sensor output 0.1µF – + AVDD 4 AVCC DVCC VCC LEVAJ=VBL OF DIN GND <6:0> Digital circuit LCMP MCIS <3:1>,MCCD S/H BTCMP BLS BLCMP RESET ADCK GAIN <7:0> VCC (dashed line) : clock line (bold line) : signal line MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR AIN White MCCD – + – + + – – + 8 + – Vri+ VBL VWL 3.8V ADIN Vri- Fig. 19 External pin connections of the analog part (for the CCD mode/line clamping) Vri- 1.8V – + Gain control circuit – + Black level clamping circuit AGCSEL <7:0> + – C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO BCMI BCMO BCMV=VBL GCAO LEVAJ BCMV C1C2 0.1µF AVCC Vref- Vri+ DVCC + – Vref+ AGND DGND VREFH OF VREFL B <7:1> ADIN A/D converter ADCK RESET + – Reference voltage generating circuit for the A/D converter GCA Sample and hold circuit Bit clamping circuit 2.2V – + L S/H BTCMPBLS H Internal reference voltage source for the analog circuits AGND DGND GND AGND – + MCIS3 MCIS2 Level shift circuit(2.2V) MCIS1 Input clamping circuit – + MCIS <3:1> ,MCCD 4 AVCC DVCC VCC AVDD LCMP Black AIN Signaling element 0.1µF Blanking element M a x .500mVpp. LEVAJ=VBL OF DIN GND <6:0> Digital circuit LCMP MCIS <3:1>,MCCD S/H BTCMP BLS BLCMP RESET ADCK GAIN <7:0> VCC (dashed line) : clock line (bold line) : signal line MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR 45 46 MCCD AGND – + MCIS2 MCIS3 Level shift circuit(2.2V) MCIS1 – + L + – 8 Vri- Vri+ 3.8V V LEVAJ VBL VWL R1 R2 1.8V – + – + Gain control circuit GCA L BCMI BCMO Black level clamping circuit AGCSEL<7:0> + – C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO C1C2 GCAO LEVAJ BCMV BCMV=VBL ADIN VriAVCC Vref- Vri+ DVCC + – Vref+ AGND DGND VREFH OF VREFL B<7:1> ADIN A/D converter ADCK RESET + – Reference voltage generating circuit for the A/D converter + – Internal reference voltage source for the analog circuits – + Bit clamping circuit – + Sample and hold circuit Fig. 20 External pin connections of the analog part (for the CIS1 mode) AGND DGND GND Gr : gain of the gain control circuit A : minimum limit for dark voltage of the sensor – + H S/H BTCMPBLS 2.2V MCIS<3:1>,MCCD 4 Input clamping circuit – + AVDD LCMP H AVCC DVCC VCC Set R1 and R2 so that the following equation will hold. VLEVAJ = VVBL – A ✕ B + 0.2 [V] (1.8V) where, ±200mV Max.3.5V Sensor output Sensor output AIN Black White Max.5pF GND OF DIN<6:0> Digital circuit LCMP MCIS<3:1>,MCCD S/H BTCMP BLS BLCMP RESET ADCK GAIN<7:0> VCC (dashed line) : clock line (bold line) : signal line MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR AIN LCMP MCCD AGND – + MCIS2 MCIS3 Level shift circuit(2.2V) MCIS1 – + + – 8 GCA Vri- Vri+ 3.8V V LEVAJ VBL VWL R1 R2 1.8V – + Gain control circuit – + Black level clamping circuit AGCSEL<7:0> + – C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO L ADIN VriAVCC Vref- Vri+ DVCC + – Vref+ AGND DGND VREFH OF VREFL B<7:1> ADIN A/D converter ADCK RESET + – Reference voltage generating circuit for the A/D converter + – Internal reference voltage source for the analog circuits – + Bit clamping circuit – + Sample and hold circuit Fig. 21 External pin connections of the analog part (for the CIS2 mode) AGND DGND GND Gr : gain of the gain control circuit A : minimum limit for dark voltage of the sensor L S/H BTCMPBLS H BCMI BCMO BCMV=VBL GCAO LEVAJ BCMV C1C2 (In the case of the pixel clock of 1 MHz) 2.2V – + MCIS<3:1>, MCCD 4 Input clamping circuit – + AVDD AIN H AVCC DVCC VCC Set R1 and R2 so that the following equation will hold. VLEVAJ = VVBL – A ✕ B + 0.2 [V] (1.8V) where, ±200mV M a x .2V Sensor output Black White Max.5pF GND OF DIN<6:0> Digital circuit LCMP MCIS<3:1>,MCCD S/H BTCMP BLS BLCMP RESET ADCK GAIN<7:0> VCC (dashed line) : clock line (bold line) : signal line MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR 47 48 0.1µF Black – + – + AGND DGND GND AGND Input clamping circuit MCCD MCIS3 MCIS2 Level shift circuit(2.2V) MCIS1 – + + – Vri- Vri+ 3.8V VBL VWL 1.8V GCA – + Gain control circuit – + AGCSEL <7:0> Black level clamping circuit + – C1 C2 GCAO LEVAJ BCMV BLCMP BCMI BCMO C1C2 BCMI BCMO BCMV=VBL GCAO LEVAJ BCMV 0.1µF ADIN VriAVCC Vref- Vri+ DVCC + – Vref+ AGND DGND VREFH OF VREFL B <7:1> ADIN A/D converter ADCK RESET + – Reference voltage generating circuit for the A/D converter Internal reference voltage source for the analog circuits – + 8 + – Sample and hold circuit Bit clamping circuit 2.2V – + L S/H BTCMPBLS H Fig. 22 External pin connections of the analog part (for the CIS3 mode) Shielding pixel part AIN – + MCIS <3:1>,MCCD 4 AVCC DVCC VCC AVDD LCMP White AIN Signalding part Sensor output M a x .2Vpp. LEVAJ=VBL OF DIN GND <6:0> Digital circuit LCMP MCIS <3:1>,MCCD S/H BTCMP BLS BLCMP RESET ADCK GAIN <7:0> VCC (dashed line) : clock line (bold line) : signal line MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR FLOWCHART: READING OPERATIONS (FOR THE CCD SENSOR) Start Power on Software reset Register 00 S/H: SH pulse width Register 01 Cycle counter Start pulse Writing the dither pattern Register 02 Register 08 to 0E Register 10 SRDY setting Register 16 INT generated? Register 17 N Y N Page end? Y Reading the original sheet ends. Register 0F Y 1 line cycle ×20 (or 16 or more) wait AGC ends. Register 00 AGC: 16 times Uniformity correction ends. Register 00 White correction : 8 times Register 00 Specifying the vertical scanning resolution Register 06 Specifying the horizontal scanning resolution Register 15 White correction Uniformity correction starts. Register 00 Peak value detection AGC starts. Register 00 Transfer to be continued? 1 line cycle × 2 wait The light source is turned off. Y The light source is turned on. (white reference) Becomes stable. N Y Power off? N Next original sheet Y Next original sheet? N Power off End Completed? Y Specifying the vertical scanning resolution Register 06 Original sheet width and output width Registers 01 and 11 to 14 Setting for the original sheet N Register 15 Register 05 Completed? Next original sheet 1 line cycle ×10 (or 8 or more) wait Specifying the scaling factor for vertical scanning Register 03 and 04 Y N Register 00 Completed? writing γ correction table Register 06 and 07 Reading an original sheet starts. Initial setting Image processing parameters Image processing function Reading a single page Sensor control N A A 49 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR READING OPERATIONS (FOR THE CIS SENSOR) Start Power on Software reset S/H: SH pulse width A Register 00 Register 06 and 07 Register 01 Register 02 Cycle counter Registers 03 and 04 Image processing parameters Registers 08 to 0E Writing the dither pattern Register 10 Register 00 Specifying the scaling factor for vertical scanning Register 15 SRDY setting Register 16 INT generated? Register 17 Initial setting Register 05 Reading an original sheet starts. N Y N Page end? Y N Reading the original sheet ends. Completed? Y writing γ correction table N Y Register 0F N Completed? Next original sheet Y AGC starts. Register 00 AGC: 16 times 1 line cycle × 20 (or 16 or more) wait AGC ends. Peak value detection The light source is turned on. (white reference) Becomes stable. Transfer to be continued? Register 00 1 line cycle × 2 wait The light source is turned off. Power off? N Next original sheet Y Next original sheet? N The light source is turned off. Uniformity correction mode (black) Uniformity correction starts. Registers 00 and 01 Register 00 Black correction: 8 times 1 line cycle ×10 (or 8 or more) wait Uniformity correction mode (white) Uniformity correction starts. Register 00 Registers 00 and 01 Register 00 White correction: 8 times 1 line cycle ×10 (or 8 or more) wait Register 00 Specifying the horizontal scanning resolution Register 06 Writing the resolution change table Register 15 N Completed? Y Specifying the vertical scanning resolution Original sheet width and output width A 50 Register 06 Registers 01 and 11 to 14 Setting for the original sheet Uniformity correction ends. White correction The light source is turned on. (white reference) Becomes stable. Uniformity correction ends. Black correction Becomes stable. Power off End Y Register 00 Reading a single page Sensor control Start pulse Image processing function MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ABSOLUTE MAXIMUM RATINGS (Ta = –20 ~ 75°C unless otherwise noted) Symbol Parameter Ratings Unit –0.3 ~ +6.5 V –0.3 ~ VCC+0.3 V 0 ~ VCC V Analog supply voltage VCC –0.3 ~ VCC +0.3 V Supply voltage VCC –0.3 ~ VCC +0.3 V Reference voltage (white) –0.3 ~ AVCC +0.3 V Reference voltage (black) –0.3 ~ AVCC +0.3 V VAIN Analog input voltage –0.3 ~ AVCC +0.3 V Tstg Storage temperature –55 ~ +150 °C VCC Supply voltage VI Input voltage VO Output voltage AVCC DVCC VWL VBL Conditions RECOMMENDED OPERATIONAL CONDITIONS Symbol Parameter Limits Min. Typ. Max. 4.75 5.0 5.25 VCC Supply voltage (for the digital system component) GND GND voltage VI Input voltage AVCC Analog supply voltage AGND Analog GND voltage DVCC Supply voltage (for the digital system component) DGND GND voltage VAIN Input range: VWL ≤ AVcc; VBL ≥ AGND 1.8 Topr Operating temperature –20 0.0 0 4.75 5.0 5.0 VCC V 5.25 V V 5.25 V 2.2 VP–P +75 °C 0.0 2.0 V V 0.0 4.75 Unit V Note: Connect the analog system component and the digital system component separately to power supply on the evaluation board for noise prevention. 51 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR ELECTRICAL CHARACTERISTICS (Ta = –20 ~ 75°C, VCC = 5V±5% unless otherwise noted) Symbol Parameter Test conditions Ratings Min. Typ. Max. Unit VIH “H” input voltage VIL “L” input voltage 0.8 V VT+ Positive direction input threshold 2.4 V VT– Negative direction input threshold VH Hysteresis value VOH “H” output voltage IOH = –12mA VOL “L” output voltage IOL = 12mA VOH “H” output voltage IOH = –4mA VOL “L” output voltage IOL = 4mA IIH “H” input current IIL 2.0 V 0.6 V 0.2 V VCC–0.8 V 0.55 VCC–0.8 V V 0.55 V VCC = 5.25V VI = 5.25V 1.0 mA “L” input current VCC = 5.25V VI = 0V –1.0 mA IOZH “H” input current in the off state VCC = 5.25V VO = 5.25V 5.0 mA IOZL “L” input current in the off state VCC = 5.25V VO = 0V –5.0 mA IAIN Analog input current 1.0 mA RL Reference resistance Ed Differential non-linear error ICCS Static current dissipation (during standby) 52 VCC = 5.25V VI = VCC, GND 120 Ω ±1.0 LSB 21 35 mA MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR TIMING CONDITIONS (Ta = –20 ~ 75°C, VCC = 5V±5% unless otherwise noted) Symbol Test conditions Parameter Ratings Min. Typ. Max. Unit tc (SYS) System clock cycle 50 ns tw+ (SYS) System clock “H” pulse width 25 ns tw– (SYS) System clock “L” pulse width 25 ns tr (SYS) System clock rise time 20 ns tf (SYS) System clock fall time 20 ns tw (RD) Read pulse width 100 ns tsu (CS-RD) Set-up time before read CS 20 ns tsu (A-RD) Set-up time before read A0 ~ A4 20 ns tsu (DAK-RD) Set-up time before read DAK 20 ns th (RD-CS) Hold time after read CS 10 ns th (RD-A) Hold time after read A0 ~ A4 10 ns th (RD-DAK) Hold time after read DAK tw (WR) Write pulse width tsu (CS-WR) Set-up time before write tsu (A-WR) Set-up time before write tsu (D-WR) Set-up time before write th (WR-CS) Hold time after write th (WR-A) th (WR-D) th (STIM-SRDY) 10 ns 100 ns CS 20 ns A0 ~ A4 20 ns D0 ~ D7 50 ns CS 20 ns Hold time after write A0 ~ A4 10 ns Hold time after write D0 ~ D7 0 ns Hold time after STIM SRDY 0 ns 53 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR SWITCHING CHARACTERISTICS (Ta = –20 ~ 75°C, VCC = 5V±5% unless otherwise noted) Parameter Symbol Ratings Test conditions Min. Typ. Unit Max. __ tPZL (RD-D) Enable time for data output after read __ tPZH (RD-D) ns 75 ns CL = 150pF __ tPLZ (RD-D) Disable time for data output after read __ tPHZ (RD-D) __ tPHL (RD-DRO) 10 Propagation time of DRO output after read ns 50 CL = 50pF ns 50 ns TEST CIRCUIT Parameter Input VCC Output VCC tPLH, tPHL RL=1kΩ SW1 Tested device P.G SW2 CL 50Ω GND SW1 SW2 Open Open tPLZ Closed Open tPHZ Closed Closed tPZL Closed Open tPZH Open Closed (1) Characteristics (10% to 90%) of the pulse generator (PG): t r = 3ns; t f = 3ns (2) Capacitance CL (= 150pF) includes the stray capacitance of connections and input capacitance of the probe. RL=1kΩ SYSTEM CLOCK tc(SYS) tf(SYS) tW+(SYS) tr(SYS) tW-(SYS) 3V 90% SYSCK 1.3V 1.3V 90% 1.3V 10% 10% 0V 54 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR MPU INTERFACE 1) Timing for read operation (M66335 → MPU) 3V CS 1.3V 1.3V tSU(CS-RD) 0V th(RD-CS) 3V A0~A4 1.3V 1.3V tSU(A-RD) tW(RD) 0V th(RD-A) 3V 1.3V 1.3V RD 0V tPZL(RD-D) D0~D7 tPLZ(RD-D) 50% 10% tPZH(RD-D) D0~D7 VOL tPHZ(RD-D) VOH 90% 50% 2) Timing for write operation (MPU → M66335) 3V CS 1.3V 1.3V tSU(CS-WR) 0V th(WR-CS) 3V A0~A4 1.3V 1.3V tSU(A-WR) tW(WR) 0V th(WR-A) 3V WR 1.3V 1.3V 0V tSU(D-WR) tSU(WR-D) 3V D0~D7 1.3V Effective data 1.3V 0V 55 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR DMA TIMING Timing for read operation (M66335 → system bus) VOH DRQ 50% 50% VOL 120/SYSCK tPHL(RD-DRQ) 3V DAK 1.3V 1.3V tSU(DAK-RD) 0V tW(RD) th(RD-DAK) 3V 1.3V 1.3V RD 0V tPZL(RD-D) D0~D7 tPLZ(RD-D) 50% 10% tPZH(RD-D) D0~D7 50% VOL tPHZ(RD-D) 90% VOH Timing of CODEC th(STIM-SRDY) 3V SRDY 1.3V 0V VOH STIM 50% VOL VOH SCLK VOL VOH SVID VOL 56 MITSUBISHI 〈DIGITAL ASSP〉 M66335FP FACSIMILE IMAGE DATA PROCESSOR Cautions for Use (1) Access to Address 00h To gain access to address 00h, the value of built-in GCC (gain control counter) may be set to FFh. This requires to read GAIN value at address 18h before access to address 00h and write the GAIN value at address 18h after the access (see Flowchart A). Start Read GAIN value at address 18h Access address 00h Write GAIN value at address 18h End Flowchart A. Address 00h Access Flow (2) Reset The M66335FP adopts the two types of reset. These reset functions are provided in Table A. Table A. Reset functions Function Reset type Register initialization Internal F/F initialization GCC initialization Hardware reset (RESET) Software reset register 0 (RESET) 57