Microchip HCS362 Memory programming specification Datasheet

HCSXXX
HCSXXX Memory Programming Specification
This document includes the
programming specifications for the
following devices:
• HCS200
• HCS360
• HCS500
• HCS201
• HCS361
• HCS512
• HCS300
• HCS362
• HCS515
• HCS301
• HCS410
• HCS320
• HCS412
1.0
1.2
Program/Verify Mode
The Program/Verify mode for the KEELOQ devices
allows programming for all memory locations within the
device being programmed. With the exception of the
decoders, these pins are also used to verify the memory
arrays.
PROGRAMMING THE HCSXXX
All of the KEELOQ® devices are programmed using a
serial method. This Serial mode allows KEELOQ
devices to be programmed while in users' systems,
which increases the flexibility of designing
cryptographic encoders, decoders and transponders
into electronic systems. While some of the devices are
capable of being programmed through wireless
communications, the subject of this document is
focused on wired programmers that make contact with
the KEELOQ products while the components are incircuit or in a programmer socket. Additionally, this
programming specification only applies to all KEELOQ
devices listed above in all packages.
Note:
1.1
For the purpose of this document,
“KEELOQ devices” and “KEELOQ products”
refers to all of the components listed
above.
Programming Algorithm
Requirements
Depending on the device being programmed, the
method for entering Programming mode can be
achieved through the use of a combination of logic level
signals applied to the programming pins. One or two
pins are capable of accepting clock signals, while
another pin is dedicated to bidirectional data. These
pins are detailed in Table 1-1.
Additionally, the programming voltage range for VDD is
+5V ± 10% for all the KEELOQ devices. There is not a
requirement to apply high voltages to any of the pins
beyond the level of VDD in order to enter the
Programming mode. For more details about pin
configurations during programming, refer to Table 1-1.
 2004 Microchip Technology Inc.
Preliminary
DS41256A-page 1
HCSXXX
Pin Diagrams
PDIP, SOIC
VDD
7
NC
S1
2
7
STEP
6
PWM
S2
3
6
DATA
4
5
VSS
VDDB
4
5
VSS
S0
1
8
VDD
S0
1
8
VDD
S1
2
7
LED
S1
2
7
LED
S2
3
6
PWM
S2
3
6
PWM
S3
4
5
VSS
SHIFT
4
5
VSS
S0
1
8
VDD
S0
1
8
VDD
S1
2
7
LED/SHIFT
S1
2
7
LED
S2
3
6
DATA
S2
3
6
DATA
S3/RFEN
4
5
VSS
S3
4
5
VSS
S0
1
8
VDD
S0
1
S1
2
7
LC0
S1
2
S2/LED
3
6
PWM
S2/RFEN/LC1
3
LC1
4
5
GND
LC0
4
VDD
1
8
VSS
EE_CLK
2
7
RFIN
EE_DAT
3
6
S_CLK
MCLR
4
5
S_DAT
NC
DS41256A-page 2
HCS300/301
3
HCS362
S2
HCS410
2
HCS500
S1
Preliminary
HCS201
8
HCS320
1
HCS360/361
S0
HCS412
VDD
1
HCS200
8
S0
8
VDD
7
LED
6
DATA
5
GND
 2004 Microchip Technology Inc.
HCSXXX
Pin Diagrams (Continued)
PDIP, SOIC
18
RFIN
LRNOUT
2
17
NC
NC
1
14
NC
NC
3
16
OSCIN
NC
2
13
NC
MCLR
4
15
OSCOUT
VDD
3
12
VSS
GND
5
14
VDD
S1
4
11
RF_IN
S0
6
13
DATA
S0
5
10
S_CLK
S1
7
12
CLK
MCLR
6
9
S_DAT
S2
8
11
SLEEP
NC
7
8
NC
S3
9
10
VLOW
S2
1
2
HCS515
1
HCS512
LRNIN
TSSOP
S3/RFEN
VSS
DATA
3
4
8
HCS362
 2004 Microchip Technology Inc.
7
6
5
S1
S0
VDD
LED/SHIFT
Preliminary
S2/LED
LC1
GND
PWM
1
2
3
4
8
HCS410
7
6
5
S1
S0
VDD
LC0
DS41256A-page 3
HCSXXX
TABLE 1-1:
PIN DESCRIPTIONS (DURING PROGRAMMING)
Pin Number
Device
Comments
Power Supply
Ground
Clock
Data
Other
HCS200
8
5
3
6
—
HCS201
8
5
3
6
—
(Notes 1)
HCS300
8
5
3, 4
6
—
(Notes 2)
HCS301
8
5
3, 4
6
—
(Notes 2)
HCS320
8
5
3
6
—
(Notes 2)
HCS360
8
5
3, 4
6
2
(Notes 2)
HCS361
8
5
3, 4
6
2
(Notes 2)
HCS362
8
5
3, 4
6
—
(Notes 2)
HCS410
8
5
3
6
—
HCS412
8
5
3
6
—
(Note 1)
HCS500
1
8
6
5
—
(Notes 2, 3, 4, 7, 8)
HCS512
14
5
12
13
4
(Notes 5, 6, 8, 9)
3
12
10
9
—
(Notes 7, 8)
HCS515
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
Sends calibration pulse during ACK periods.
VDD pin must be driven low after a Program/Verify cycle.
In-circuit programming recommended.
Used in conjunction with a Microchip Technology 24LC02B device.
MCLR, pin 4, is used to enter Program mode.
Must apply external clock source to OSCIN while programming.
Requires command byte preceding data packet.
Verify function not available.
Uses checksum in data packet.
DS41256A-page 4
Preliminary
 2004 Microchip Technology Inc.
HCSXXX
2.0
MEMORY MAPPING
The program memory maps for KEELOQ products begin
at 0x000 and extend as shown in the tables that follow.
As a device is being programmed, the address counter
automatically increments to the next word location after
receiving a data word. The memory maps for all
KEELOQ encoders and transponders were designed so
that each word is 16 bits wide. Decoder memory maps
are 8 bits wide.
2.1
Encoder Memory Maps
TABLE 2-1:
HCS200 12 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
0x00
KEY_0
Word 0 (LSb's) of 64-bit crypt key
0x01
KEY_1
Word 1 of 64-bit crypt key
0x02
KEY_2
Word 2 of 64-bit crypt key
0x03
KEY_3
Word 3 (MSb's) of 64-bit crypt key
0x04
SYNC
0x05
Reserved
Description
16-bit synchronization value
Set to 0x0000
0x06
SER_0
Word 0 (LSb's) of 32-bit serial number
0x07
SER_1
Word 1 (MSb's) of 32-bit serial number
0x08
SEED_0
Word 0 (LSb's) of 32-bit seed value
0x09
SEED_1
Word 1 (MSb's) of 32-bit seed value
0x0A
Reserved
Set to 0x0000
0x0B
CONFIG
Configuration Word
TABLE 2-2:
HCS201 12 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
0x00
KEY_0
Word 0 (LSb's) of 64-bit crypt key
0x01
KEY_1
Word 1 of 64-bit crypt key
0x02
KEY_2
Word 2 of 64-bit crypt key
0x03
KEY_3
Word 3 (MSb's) of 64-bit crypt key
0x04
SYNC
16-bit synchronization value
0x05
Reserved
0x06
SER_0
Word 0 (LSb's) of 32-bit serial number
0x07
SER_1
Word 1 (MSb's) of 32-bit serial number
0x08
SEED_0
Set to 0x0000
Word 0 (LSb's) of 32-bit seed value
0x09
SEED_1
0x0A
DISC
Discrimination Word
0x0B
CONFIG
Configuration Word
 2004 Microchip Technology Inc.
Word 1 (MSb's) of 32-bit seed value
Preliminary
DS41256A-page 5
HCSXXX
TABLE 2-3:
HCS300 12 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
0x00
KEY_0
Word 0 (LSb's) of 64-bit crypt key
0x01
KEY_1
Word 1 of 64-bit crypt key
0x02
KEY_2
Word 2 of 64-bit crypt key
0x03
KEY_3
Word 3 (MSb's) of 64-bit crypt key
0x04
SYNC
16-bit synchronization value
0x05
Reserved
0x06
SER_0
Note 1:
(1)
0x07
SER_1
0x08
SEED_0
Description
Set to 0x0000
Word 0 (LSb's) of 32-bit serial number
Word 1 (MSb's) of 32-bit serial number
Word 0 (LSb's) of 32-bit seed value
0x09
SEED_1
Word 1 (MSb's) of 32-bit seed value
0x0A
Reserved
Set to 0x0000
0x0B
CONFIG
Configuration Word
MSb of this word is used for auto-shutoff timer.
TABLE 2-4:
HCS301 12 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
0x00
KEY_0
Word 0 (LSb's) of 64-bit crypt key
0x01
KEY_1
Word 1 of 64-bit crypt key
0x02
KEY_2
Word 2 of 64-bit crypt key
0x03
KEY_3
Word 3 (MSb's) of 64-bit crypt key
0x04
SYNC
16-bit synchronization value
0x05
Reserved
0x06
SER_0
Note 1:
(1)
0x07
SER_1
0x08
SEED_0
Description
Set to 0x0000
Word 0 (LSb's) of 32-bit serial number
Word 1 (MSb's) of 32-bit serial number
Word 0 (LSb's) of 32-bit seed value
0x09
SEED_1
Word 1 (MSb's) of 32-bit seed value
0x0A
Reserved
Set to 0x0000
0x0B
CONFIG
Configuration Word
MSb of this word is used for auto-shutoff timer.
TABLE 2-5:
HCS320 12 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
0x00
KEY_0
Word 0 (LSb's) of 64-bit crypt key
0x01
KEY_1
Word 1 of 64-bit crypt key
0x02
KEY_2
Word 2 of 64-bit crypt key
0x03
KEY_3
Word 3 (MSb's) of 64-bit crypt key
Note 1:
0x04
SYNC
0x05
Reserved
Description
16-bit synchronization value
Set to 0x0000
0x06
SER_0
Word 0 (LSb's) of 32-bit serial number
0x07
SER_1(1)
Word 1 (MSb's) of 32-bit serial number
0x08
—
Not used
0x09
—
Not used
0x0A
Reserved
Set to 0x0000
0x0B
CONFIG
Configuration Word
MSb of this word is used for auto-shutoff timer.
DS41256A-page 6
Preliminary
 2004 Microchip Technology Inc.
HCSXXX
TABLE 2-6:
HCS360 12 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
0x00
KEY_0
Word 0 (LSb's) of 64-bit crypt key
0x01
KEY_1
Word 1 of 64-bit crypt key
0x02
KEY_2
Word 2 of 64-bit crypt key
0x03
KEY_3
Word 3 (MSb's) of 64-bit crypt key
0x04
SYNC_A
16-bit synchronization value A
0x05
SYNC_B
16-bit synchronization value B or Seed Value (Word 2)
0x06
Reserved
Set to 0x0000
0x07
SEED_0
Word 0 (LSb's) of 32-bit seed value
0x08
SEED_1
Word 1 (MSb's) of 32-bit seed value
0x09
SER_0
Word 0 (LSb's) of 32-bit serial number
0x0A
SER_1
Word 1 (MSb's) of 32-bit serial number
0x0B
CONFIG
TABLE 2-7:
Configuration Word
HCS361 12 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
0x00
KEY_0
Word 0 (LSb's) of 64-bit crypt key
0x01
KEY_1
Word 1 of 64-bit crypt key
0x02
KEY_2
Word 2 of 64-bit crypt key
0x03
KEY_3
Word 3 (MSb's) of 64-bit crypt key
0x04
SYNC_A
0x05
SYNC_B/SEED_2
0x06
Reserved
16-bit synchronization value A
16-bit synchronization value B or Seed Value (Word 2)
Set to 0x0000
0x07
SEED_0
Word 0 (LSb's) of 32-bit seed value
0x08
SEED_1
Word 1 (MSb's) of 32-bit seed value
0x09
SER_0
Word 0 (LSb's) of 32-bit serial number
0x0A
SER_1
Word 1 (MSb's) of 32-bit serial number
0x0B
CONFIG
 2004 Microchip Technology Inc.
Configuration Word
Preliminary
DS41256A-page 7
HCSXXX
TABLE 2-8:
HCS362 18 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
0x00
KEY1_0
Word 0 (LSb's) of 64-bit crypt key 1
0x01
KEY1_1
Word 1 of 64-bit crypt key 1
0x02
KEY1_2
Word 2 of 64-bit crypt key 1
0x03
KEY1_3
Word 3 (MSb's) of 64-bit crypt key 1
0x04
KEY2_0
Word 0 (LSb's) of 64-bit crypt key 2
0x05
KEY2_1
Word 1 of 64-bit crypt key 2
0x06
KEY2_2
Word 2 of 64-bit crypt key 2
0x07
KEY2_3
Word 3 (MSb's) of 64-bit crypt key 2
0x08
SEED_0
Word 0 (LSb's) of 64-bit seed value
0x09
SEED_1
Word 1 of 64-bit seed value
0x0A
SEED_2
Word 2 of 64-bit seed value
0x0B
SEED_3
0x0C
CONFIG_0
Configuration Word (LSb's)
0x0D
CONFIG_1
Configuration Word (MSb's)
0x0E
SERIAL_0
Word 0 (LSb's) of 32-bit serial number
0x0F
SERIAL_0
0x10
SYNC
0x11
Reserved
TABLE 2-9:
Word 3 (MSb's) of 64-bit seed value
Word 1 (MSb's) of 32-bit serial number
16-bit synchronization value
Set to 0x0000
HCS500 9 X 8-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
0x00
CONFIG
0x01
KEY0
Byte 0 (LSb’s) of 64-bit manufacturer key
0x02
KEY1
Byte 1 of 64-bit manufacturer key
0x03
KEY2
Byte 2 of 64-bit manufacturer key
0x04
KEY3
Byte 3 of 64-bit manufacturer key
0x05
KEY4
Byte 4 of 64-bit manufacturer key
0x06
KEY5
Byte 5 of 64-bit manufacturer key
0x07
KEY6
Byte 6 of 64-bit manufacturer key
0x08
KEY7
Byte 7 (MSb’s) of 64-bit manufacturer key
TABLE 2-10:
Description
Configuration Word
HCS512 10 X 8-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
0x00
KEY0
Byte 0 (LSb’s) of 64-bit manufacturer key
0x01
KEY1
Byte 1 of 64-bit manufacturer key
0x02
KEY2
Byte 2 of 64-bit manufacturer key
0x03
KEY3
Byte 3 of 64-bit manufacturer key
0x04
KEY4
Byte 4 of 64-bit manufacturer key
0x05
KEY5
Byte 5 of 64-bit manufacturer key
0x06
KEY6
Byte 6 of 64-bit manufacturer key
0x07
KEY7
0x08
CONFIG
0x09
Checksum
DS41256A-page 8
Description
Byte 7 (MSb’s) of 64-bit manufacturer key
Configuration byte
Checksum byte
Preliminary
 2004 Microchip Technology Inc.
HCSXXX
TABLE 2-11:
2.2
HCS515 9 X 8-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
0x00
CONFIG
Description
Configuration byte
0x01
KEY0
Byte 0 (LSb’s) of 64-bit manufacturer key
0x02
KEY1
Byte 1 of 64-bit manufacturer key
0x03
KEY2
Byte 2 of 64-bit manufacturer key
0x04
KEY3
Byte 3 of 64-bit manufacturer key
0x05
KEY4
Byte 4 of 64-bit manufacturer key
0x06
KEY5
Byte 5 of 64-bit manufacturer key
0x07
KEY6
Byte 6 of 64-bit manufacturer key
0x08
KEY7
Byte 7 (MSb’s) of 64-bit manufacturer key
Transponder Memory Maps
TABLE 2-12:
HCS410 16 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
0x00
KEY_0
Word 0 (LSb's) of 64-bit crypt key
0x01
KEY_1
Word 1 of 64-bit crypt key
0x02
KEY_2
Word 2 of 64-bit crypt key
0x03
KEY_3
Word 3 (MSb's) of 64-bit crypt key
0x04
DISC
0x05
CONFIG
Description
Ext. Config. Word/10-bit Discriminator
16-bit Configuration Word
0x06
SER_0
Word 0 (LSb's) of 32-bit serial number
0x07
SER_1
Word 1 (MSb's) of 32-bit serial number
0x08
SEED_0
Word 0 (LSb's) of 64-bit seed value
0x09
SEED_1
Word 1 of 64-bit seed value
0x0A
SEED_2
Word 2 of 64-bit seed value
0x0B
SEED_3
Word 3 (MSb's) of 64-bit seed value
0x0C
USR_0
Word 0 (LSb's) of 64-bit user area
0x0D
USR_1
Word 1 of 64-bit user area
0x0E
USR_2
Word 2 of 64-bit user area
0x0F
USR_3
Word 3 (MSb's) of 64-bit user area SYNC
 2004 Microchip Technology Inc.
Preliminary
DS41256A-page 9
HCSXXX
TABLE 2-13:
2.3
HCS412 18 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
0x00
KEY0
Word 0 (LSb’s) of 64-bit crypt key 1
0x01
KEY1
Word 1 of 64-bit crypt key 1
0x02
KEY2
Word 2 of 64-bit crypt key 1
0x03
KEY3
Word 3 (MSb’s) of 64-bit crypt key 1
0x04
SEED0
Word 0 (LSb’s) of 60-bit seed value
0x05
SEED1
Word 1 of 60-bit seed value
0x06
SEED2
Word 2 of 60-bit seed value
0x07
CFG/SEED3
0x08
CONFIG1
0x09
CONFIG2
0x0A
SER0
Word 3 of 60-bit seed value/Configuration in top nibble
Configuration Word 1 (security options)
Configuration Word 2
Word 0 (LSb’s) of 32-bit serial number
0x0B
SER1
Word 1 (MSb’s) of 32-bit serial number
0x0C
USR0
Word 0 (LSb’s) of 64-bit user area
0x0D
USR1
Word 1 of 64-bit user area
0x0E
USR2
Word 2 of 64-bit user area
0x0F
USR3
Word 3 (MSb’s) of 64-bit user area
Entering Program Mode
Entering the Program/Verify mode will be dependent
upon the type of device in use. Most KEELOQ devices
use a serial clock and bidirectional data line to access
the chips' memory maps. In order to enter the
Programming mode, a Start condition is sent to the
target device, where the clock and data lines must be
held high and low for specified periods of time. That is,
all lines are held low while the clock line is driven high.
After a short delay, the data line is driven high. At this
point, both lines must remain high for another delay
period prior to dropping back to ground. After dropping
both lines low and providing another delay, the state
machine for the KEELOQ device will enter the
Programming mode and begin to wait for data, or
depending on the component, a bulk erase is
performed on the memory array.
The HCS512 is another device that does not conform to
the 2-wire protocol described above. For this device, the
MCLR pin is driven high while data is held low. After the
minimum setup time has been realized, the clock pin is
driven high and then low for a minimum amount of time
in order to send the HCS512 a Start condition and
complete the Entry mode for the next programming
sequence. The associated waveform is detailed in
Section 5.0 “Program/Verify Mode Electrical
Characteristics”. The HCS512 is also the only device
that requires a checksum be sent to the target device
while it is being programmed. See the Checksum
Section in the HCS512 Data Sheet, “KEELOQ® Code
Hopping Decoder“ (DS40151), for details on calculating
the checksum.
Note:
For the HCS360 and HCS361 devices, the Programming
mode is entered by providing a clock source on the clock
line and a Start pulse on the data line, as described in the
previous paragraph. However, the difference is with
driving the S1 pin, as shown in Figure 5-5. Bit 0 of the
data packet must be driven on the S1 pin and kept at that
level throughout the programming cycles and through
verification.
DS41256A-page 10
Preliminary
The HCS512 requires an external clock
signal for the OSCIN pin. This signal is
necessary throughout the Programming
mode.
 2004 Microchip Technology Inc.
HCSXXX
2.4
Bulk Write Device
2.7
All transponders and encoders are bulk erased and
programmed with zeros following the Start condition.
The bulk erase/write time frame is specified as TPBW,
which is minimally 4.0 ms. After the bulk function is
complete, the programming state machine continues
into the Program mode where it begins to wait for data
and clock signals.
2.5
Serial Program/Verify Operation
For all of the encoders and transponders, the memory
maps have been designed to be in 16-bit format, which
means that each address location contains 16 bits of
information including “don't care” bits that are read as
zeros. Details relating to the designated pins for clock
and data signals are outlined in Table 1-1. The
decoders, on the other hand, were designed with
memory maps in 8-bit format, so they are discussed
separately in the next couple of paragraphs.
For specific information relating to the size of the
memory maps for a given family of devices, be sure to
review the tables in Section 2.1 “Encoder Memory
Maps”.
The following paragraphs were written with the
assumption that the target device has been placed into
the Programming mode and is now waiting for data or
a command byte to continue programming the memory
array.
2.5.1
ENCODERS/TRANSPONDERS
To input data to the target KEELOQ encoder or
transponder, 16 clock cycles are applied to the clock pin
of the target device while data is driven into the data pin.
Data is clocked into the target device on the falling edge
of the clock signal. Also, the minimum high time and low
time for the clock signals are 50 µs. During verification,
data must be sampled on the rising edge of the clock.
2.5.2
DECODERS
2.7.1
Polling Write Cycle
HCS201 AND HCS412
Once the 16th clock cycle for the data word has been
generated and the next minimum low time for the clock
passes, the clock pin can be driven high to poll the
completion of the write cycle. Before the write cycle is
complete, the data pin for the target KEELOQ device will
be low. After the write cycle is complete, the data pin on
the HCS201 and the HCS412 will begin to provide
pulses to the programmer in order to signal the
completion of the write cycle. As a result, the
programmer data pin should be set to high-impedance
(input) so that it can read the pulses. After reading the
pulses on the data pin, the programmer should drive
the clock pin low and make the data pin an output so
that data can continue to be driven into the target
device. These pulses can be used for calibration
sequences for the HCS201 and the HCS412. For
information relating to oscillator calibration refer to
Section 5.0 “Program/Verify Mode Electrical
Characteristics”, which discusses oscillator tuning. If
the programmer polls the target device for the end of a
write cycle, these two devices will continue to emit
calibration pulses until their clock lines are driven low.
In order to measure the calibration pulses, the clock pin
must be driven high prior to the end of the write cycle,
otherwise the calibration pulses will not appear.
2.7.2
ALL OTHER KEELOQ DEVICES
Once the 16th clock cycle for the data word has been
generated for any of the encoders or transponders or
the last clock cycle for a decoder data packet is
generated, the clock pin can be driven high to poll for
the completion of the write cycle. Before the write cycle
is complete, the data pin for the target KEELOQ device
will be low. As a result, the programmer data pin should
be set to high-impedance (input) so that it can sense
the rising edge of data. After the write cycle is
complete, the data pin will be driven high until the clock
line is driven low again.
To input data to the target KEELOQ decoder, 8 clock
cycles are applied to the clock pin of the target device
while data is driven into the data pin. Data is clocked
into the target device on the falling edge of the clock
signals. Also, the minimum high time and minimum low
time for the clock signals are 50 µs. For the decoder
family, there are no verification functions.
2.6
Begin Programming
Write cycles are performed a bit-at-a-time throughout
the entire programming sequence for KEELOQ
products. The total write cycle, which includes internal
processing and programming time, is specified to take
a minimum of 50 ms. As a result, programmers can
include a delay for the minimum write cycle time or they
can poll the target device as discussed in Section 2.7
“Polling Write Cycle”.
 2004 Microchip Technology Inc.
Preliminary
DS41256A-page 11
HCSXXX
2.8
4.0
Verify Mode
In terms of verify operations, all KEELOQ encoders and
transponders incorporate a security feature that only
allows one verify operation to be completed, and it
must be completed at the end of the programming
sequence before exiting the Programming mode.
When implementing polling routines to sense the end
of the last write cycle and after driving the clock line low,
the programmer can begin to read data by continuing
to provide clock cycles to the target device. Note that
there is not an Acknowledge bit from KEELOQ devices
during the Verify mode.
In the case where the programmer provides a time delay
to allow for write cycle completion, the programmer can
provide clock cycles after the delay to begin reading
data.
Note:
3.0
Decoders do not incorporate a verify
function.
OSCILLATOR TUNING
Calibrating the oscillator of select devices can be
completed a number of ways. For the purpose of this
document, calibration will be completed using the TwoPoint Calibration Algorithm, which is described in
Application Note AN824, “KEELOQ® Encoders
Oscillator Calibration” (DS00824). The algorithm is as
follows:
•
•
•
•
•
•
•
OSCCAL = -8
Program target device
Measure oscillator frequency FHIGH
OSCCAL = +7
Program target device
Measure oscillator frequency FLOW
Interpolate:
- OSCCAL = 16*(FIDEAL - FLOW)/(FHIGH - FLOW)
• Program target device
For a better understanding of how to implement this
algorithm, the following flow charts are being provided:
CONFIGURATION WORD
For detailed descriptions of bit functions for the
configuration words of the KEELOQ devices, be sure to
download the latest Data Sheet for the respective device
from
the
Microchip
Technology
web
site
(www.microchip.com). Configuration word architectures
are also shown earlier in Section 2.0 “Memory
Mapping”.
DS41256A-page 12
Preliminary
 2004 Microchip Technology Inc.
HCSXXX
FIGURE 4-1:
HCS201 AND HCS412 OSCILLATOR TUNING
Preload Datastream
with 0x7 for OSCCAL(1)
Store Average Value
as FLOW
Preload Datastream
with 400 µs Time Element
Measure Calibration Pulses
as Time Elements
Program Target
Reset Target(2)
Preload Datastream
with 0x8 for OSCCAL(1)
Preload Datastream
with 400 µs Time Element
Program First Word
of Target
Poll Target for End
of Write Cycle
Interpolate
OSCCAL
Reset Target(2)
Preload Datastream
with Interpolated OSCCAL
Program First Word
of Target
Preload Desired
Baud Rate
Reset Target(2)
Program Target
Program Remaining
Target
Store Average Value
as FHIGH
Poll Target for End
of Write Cycle
Measure Calibration Pulses
as Time Elements
Note 1: -8d = 0x7, and +7d = 0x8
2: Cycle Power
 2004 Microchip Technology Inc.
Preliminary
DS41256A-page 13
HCSXXX
FIGURE 4-2:
HCS362 AND HCS410 OSCILLATOR TUNING
Preload Datastream
with 0x7 for OSCCAL(1)
Preload Datastream
with 400 µs Time Element
Store Average Value
as FLOW
Measure Preamble
Time Elements
Program Target
Device
Activate Button
Input on Target
Reset Target(2)
Reset Target(2)
Interpolate
OSCCAL
Preload Datastream
with Interpolated OSCCAL
Preload Desired
Baud Rate
Program Target
Activate Button
Input on Target
Measure Preamble
Time Elements
Store Average
Value as FHIGH
Program Target
Device
Preload Datastream
With 400 µs Time Element
Preload Datastream
With 0x8 for OSCCAL
Reset Target(2)
Note 1: -8d = 0x7, and +7d = 0x8
2: Cycle Power
DS41256A-page 14
Preliminary
 2004 Microchip Technology Inc.
HCSXXX
KEELOQ devices that are capable of oscillator tuning
include the HCS201, HCS362, HCS410 and the
HCS412. Though, only the HCS201 and HCS412
transmit calibration pulses when polling the chips at the
end of write cycles.
The other two devices must be tuned according to the
preamble pulses that they transmit at the beginning of
a data packet. For the best accuracy, use multiple time
elements to achieve an average time element value.
Typically, a number that is a power of 2n is used in order
to simplify the resultant quotient (i.e., 4 or 8). In order to
obtain the most accurate time element measurement,
the widest possible baud rate should be chosen. For
simplifying the two flow diagrams below, a common
time element was chosen to the devices that share
algorithms.
FIGURE 4-3:
The HCS362 and the HCS410 oscillator tuning register
can also be tuned as shown in the algorithm above, but
with the caveat that after the device is programmed, the
programmer must activate the target device in order to
measure the time element in the communication
preamble. A typical preamble is shown in Figure 4-3.
PWM CODE WORD TRANSMISSION TIMINGS
TE TE
TE TE TE
Preamble = 23 TE
 2004 Microchip Technology Inc.
Header = 10 TE
Preliminary
bit 0
bit 1
DS41256A-page 15
HCSXXX
4.1
Programming Flow Charts
FIGURE 4-4:
PROGRAMMING FLOW
CHART 1
FIGURE 4-5:
Start
Start
Set VDD =
5.0V ± 10%
Set VDD =
5.0V ± 10%
Send Start
Sequence
Send Start
Sequence
If Data Bit 0 = 0
Then S1 = 0
Else S1 = 1
Device
Bulk Erase
Load 16 Bits
of Data
(LSb first)
Load 16-Bits
of Data
Load 16 Bits of
Complemented
Data
(LSb first)
Wait TWC or
Poll Rising
Pulse
No
PROGRAMMING FLOW
CHART 2
Wait TWC or
Poll Calibration
Pulse
All Locations
Programmed?
Yes
No
All Locations
Programmed?
Begin Verify
Yes
Begin Verify
Read 16-Bits
of Data
Read 16-Bits
of Data
All Locations
Verified?
No
All Locations
Verified?
Yes
Program/Verify
Complete
Note:
Yes
Applies to HCS200, HCS201, HCS300,
HCS301, HCS320, HCS362, HCS410
and HCS412 only.
DS41256A-page 16
No
Program/Verify
Complete
Note:
Preliminary
Applies to HCS360 and HCS361 only.
 2004 Microchip Technology Inc.
HCSXXX
FIGURE 4-6:
PROGRAMMING FLOW
CHART 3
FIGURE 4-7:
PROGRAMMING FLOW
CHART 4
Start
Start
Set VDD =
5.0V ± 10%
Set VDD =
5.0V ± 10%
Raise
NMCLR
Send Start
Sequence
Send Start
Sequence
Load 8-Bits
of Data
Load 8-Bits
of Data
No
All Locations
Loaded?
Yes
No
All Locations
Loaded?
Wait TWC or
Poll Rising
Pulse
Yes
Program
Complete
Load
Checksum
Wait TWC or
Poll Rising
Pulse
Note:
Applies to HCS500 and HCS515 only.
Program
Complete
Note:
Applies to HCS512 only.
 2004 Microchip Technology Inc.
Preliminary
DS41256A-page 17
HCSXXX
5.0
PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
5.1
Timing Requirements for Program/Verify Mode – Encoders
Standard Operating Conditions (unless otherwise
stated)
Operating Temperature +25°C ± 5°C
Operating Voltage
4.5V ≤ VDD ≤ 5.5V
AC/DC CHARACTERISTICS
Sym
Characteristics
Min
Max
Units
Conditions/Comments
HCS200, HCS300, HCS301, HCS320 and HCS362
TCLKH
Clock high time
50
—
µs
TCLKL
Clock low time
50
—
µs
TDH
Data hold time
30
—
µs
TDS
Data setup time
0
—
µs
TDV
Data out valid time
—
30
µs
TPBW
Bulk Write time
4.0
—
ms
TPH1
Hold Time 1
3.5
—
ms
TPH2
Hold Time 2
50
—
µs
TPROG
Program delay time
4.0
—
ms
TPS
Program mode setup time
3.5
4.5
ms
TWC
Program cycle time
50
—
ms
TACKH
Data out valid time
800
—
µs
TACKL
Data hold time
800
—
µs
TCLKH
Clock high time
50
—
µs
TCLKL
Clock low time
50
—
µs
TDH
Data hold time
18
—
µs
TDS
Data setup time
0
—
µs
TDV
Data out valid time
—
30
µs
TPBW
Bulk Write time
4.0
—
ms
TPH1
Hold Time 1
4.0
—
ms
HCS201
TPH2
Hold Time 2
50
—
µs
TPHOLD
Hold time
100
—
µs
TPROG
Program delay time
4.0
—
ms
TPS
Program mode setup time
2.0
5.0
ms
TWC
Program cycle time
50
—
ms
HCS360, HCS361
T1
Hold Time 1
9.0
—
ms
T2
Program mode setup time
0
4.0
ms
TCLKH
Clock high time
50
—
µs
TCLKL
Clock low time
50
—
µs
TDH
Data hold time
30
—
µs
TDS
Data setup time
0
—
µs
TDV
Data out valid time
—
30
µs
TWC
Program cycle time
50
—
ms
DS41256A-page 18
Preliminary
 2004 Microchip Technology Inc.
HCSXXX
5.2
Timing Requirements for Program/Verify Mode – Transponders
AC/DC CHARACTERISTICS
Sym
Characteristics
Standard Operating Conditions (unless otherwise
stated)
Operating Temperature +25°C ± 5°C
Operating Voltage
4.5V ≤ VDD ≤ 5.5V
Min
Max
Units
Conditions/Comments
HCS410, HCS412
TAS
ACK start time
100
—
µs
TCLKH
Clock high time
50
—
µs
TCLKL
Clock low time
50
—
µs
TDH
Data hold time
20
—
µs
TDS
Data stable time
20
—
µs
TDV
Data valid time
—
20
µs
TPH1
Program Hold Time 1
4
—
ms
TPH2
Program Hold Time 2
100
—
µs
TPROG
Bulk write time
2.2
—
ms
TPS
Program mode setup time
3
5
ms
TWC
EEPROM write time
36
—
ms
 2004 Microchip Technology Inc.
Preliminary
DS41256A-page 19
HCSXXX
5.3
Timing Requirements for Program/Verify Mode – Decoders
AC/DC CHARACTERISTICS
Sym
Characteristics
Standard Operating Conditions (unless otherwise
stated)
Operating Temperature +25°C ± 5°C
Operating Voltage
4.5V ≤ VDD ≤ 5.5V
Sugg.
Value
Min
Max
Units
500
25000
Hz
30
µs
Conditions/Comments
HCS500
FCLK
Clock frequency
—
TACK
Decoder acknowledge time
—
TADDR
Address validate time
—
—
10
µs
TCLKH
Clock high time
—
20
1000
µs
TCLKL
Clock low time
—
20
1000
µs
TCMD
Command validate time
—
—
10
µs
TDATA
Command last bit to data first bit
—
—
10
µs
TDS
Data hold time
—
14
—
µs
TREQ
Command request time
—
0.015
500
ms
TRESP
Acknowledge time
—
—
1
ms
TSTART
Command request to first command bit
—
20
1000
µs
TACK
Acknowledge time
—
—
80
ms
FOSC = 4 MHZ
TACKH
Acknowledge duration
—
1
—
µs
FOSC = 4 MHZ
TCLKH
Clock high time
—
0.05
320
µs
FOSC = 4 MHZ
TCLKL
Clock low time
—
0.05
320
µs
FOSC = 4 MHZ
TPH1
Hold Time 1
—
8
128
ms
FOSC = 4 MHZ
TPH2
Hold Time 2
—
0.05
320
µs
FOSC = 4 MHZ
TPS
Program mode setup time
—
1
64
ms
FOSC = 4 MHZ
HCS512
HCS515
TACK
Command acknowledge time
*
30
240
ms
TCLKH
Clock high time
100
20
1000
µs
TCLKL
Clock low time
100
20
1000
µs
TDATA
Command last bit to data first bit
100
10
1000
µs
TDS
Data hold time
50
14
1000
µs
TREQ
Command request time
*
0.005
500
ms
TRESP
Acknowledge time
100
10
1000
µs
TSTART
Command request to first command bit
100
20
1000
µs
TWTH
Acknowledge respond time
100
20
1000
µs
TWTL
Clock low to next command
100
10
—
µs
*
Depends on decoder status.
DS41256A-page 20
Preliminary
 2004 Microchip Technology Inc.
HCSXXX
5.4
Programming Waveforms (HCS200, HCS300, HCS301, HCS320, HCS362)
FIGURE 5-1:
PROGRAMMING WAVEFORMS
Enter Program
Mode
TPBW
TAS
TDS
TCLKH
S2
(Clock)
TPS
TWC
TDH
TPH1
TCLKL
PWM
(Data)
bit 0
bit 1
bit 2
bit 3
bit 14 bit 15
bit 16 bit 17
Ack
Pulse
Note 1: Unused button inputs to be held to ground during the entire programming sequence.
FIGURE 5-2:
Data for Word 1 (KEY_1)
Data for Word 0 (KEY_0)
Repeat for each word (12 times)
TPH2
VERIFY WAVEFORMS
End of Programming Cycle
Beginning of Verify Cycle
Data from Word 0
TWC
S2 (S3)
(Clock)
PWM
(Data)
bit 190 bit 191
bit 0
bit 1 bit 2 bit 3
bit 14
bit 15
bit 16 bit 17
bit 190 bit 191
TDV
Note: If a Verify operation is to be done, then it must immediately follow the Program cycle.
 2004 Microchip Technology Inc.
Preliminary
DS41256A-page 21
HCSXXX
5.5
Programming Waveforms (HCS201)
FIGURE 5-3:
PROGRAMMING WAVEFORMS (HCS201)
Enter Program
Mode
TPBW
Initiate Data
Polling Here
TCLKH
TPHOLD
TCLKL
TDS
S2
(Clock)
TPS TPH1
TCLKL
DATA
(Data)
bit 0 bit 1 bit 2 bit 3
TACKL TACKH
TWC
TDH
TPH2
Ack
Ack
bit 14 bit 15
Ack
Calibration Pulses
Write Cycle
Complete Here
bit 16 bit 17
Data for Word 1
Repeat for each word (12 times)
Note:
S0 and S1 button inputs to be held to ground during the entire programming sequence.
FIGURE 5-4:
VERIFY WAVEFORMS
End of Programming Cycle
Beginning of Verify Cycle
Data from Word 0
DATA
(Data)
Ack
bit 190 bit 191
TWC
bit 0
bit 1 bit 2 bit 3
bit 14
bit 15
bit 16 bit 17
bit 190bit 191
TDV
S2
(Clock)
Note:
If a Verify operation is to be done, then it must immediately follow the Program cycle.
DS41256A-page 22
Preliminary
 2004 Microchip Technology Inc.
HCSXXX
5.6
Programming Waveforms (HCS360, HCS361)
FIGURE 5-5:
PROGRAMMING WAVEFORMS
Enter Program
Mode
DATA
(Data)
Acknowledge Pulse
TWC
bit 0 bit 1 bit 2 bit 3
T2
TCLKL
TDH
bit 14 bit 15 bit 0 bit 1 bit 2 bit 3
bit 16 bit 17
bit 14 bit 15
TCLKH
S2/S3
(Clock)
T1
TDS
bit 0 of Word 0
S1
Data for Word 1
Data for Word 0 (KEY_0)
Repeat for each word
Note 1: Unused button inputs to be held to ground during the entire programming sequence.
The VDD2:pin The
mustVbe
to ground
after
program/verify
cycle.
DDtaken
pin must
be taken
to a
ground
after a Program/Verify
cycle.
FIGURE 5-6:
VERIFY WAVEFORMS
End of Programming Cycle
Beginning of Verify Cycle
Data from Word0
DATA
Ack
bit 190 bit 191
(Data)
TWC
bit 0
bit 1 bit 2 bit 3
bit 14
bit 15
bit 16 bit 17
bit 190 bit 191
TDV
S2/S3
(Clock)
S1
Note
1:
A Verify sequence is performed only once immediately after the Program cycle.
 2004 Microchip Technology Inc.
Preliminary
DS41256A-page 23
HCSXXX
5.7
Programming Waveforms (HCS410, HCS412)
FIGURE 5-7:
PROGRAMMING WAVEFORMS
Enter Program
Mode
TPBW
TAS
TDS
TCLKH
S2
(Clock)
TPS
TCLKL
PWM
(Data)
bit 0
bit 1
bit 2
1:
2:
bit 3
bit 14 bit 15
bit 16 bit 17
Data for Word 0 (KEY_0)
Repeat for each word (18 times)
TPH2
Note
TWC
TDH
TPH1
Unused button inputs to be held to ground during the entire programming sequence.
The VDD pin must be taken to ground after a Program/Verify cycle.
FIGURE 5-8:
Data for Word 1 (KEY_1)
Ack
Pulse
VERIFY WAVEFORMS
End of Programming Cycle
Beginning of Verify Cycle
Data from Word 0
TWC
S2 (S3)
(Clock)
PWM
(Data)
bit 206 bit 207
bit 0
bit 1 bit 2 bit 3
bit 14
bit 15
bit 16 bit 17
bit 206 bit 207
TDV
Note: If a Verify operation is to be done, then it must immediately follow the Program cycle.
DS41256A-page 24
Preliminary
 2004 Microchip Technology Inc.
HCSXXX
5.8
Programming Waveforms (HCS500)
FIGURE 5-9:
PROGRAMMING WAVEFORMS
TCMD
TCLKL
TPP1
TPP3
TADDR
TDATA
TDATA
TACK
TWT2
TCLKH
TDS
CLK
µC Data
LSb
MSb
LSb
MSb
MSb
MSb
LSb
TPP2 TPP4
TAW
Decoder
Data
Start Command
A
5.9
Command Byte
B
Configuration Byte Least Significant Byte
C
D
Most Significant Byte
E
F
Acknowledge
G
H
Programming Waveforms (HCS512)
FIGURE 5-10:
PROGRAMMING WAVEFORMS
MCLR
TCLKL
TPS
TPH1
TPH2
TACK
TCLKH
TACKH
CLK
(Clock)
DAT
bit 0
(Data)
Enter Program Mode
 2004 Microchip Technology Inc.
bit 1
bit 78
80-bit Data Package
Preliminary
bit 79
Ack
Acknowledge
pulse
DS41256A-page 25
HCSXXX
5.10
Programming Waveforms (HCS515)
FIGURE 5-11:
PROGRAMMING WAVEFORMS
TCLKL
TSTART
TREQ
TDATA
TDATA
TDATA
TDATA
TCLKH
TACK
TWTH
TDS
CLK
µC Data
LSb
MSb
LSb
LSb
MSb
LSb
MSb
MSb
TRESP
TWTL
HCS515
Data
Start Command
B
A
Note:
Command Byte
Configuration Byte
D
C
Acknowledge
MSb
LSb
E
F
G
H
The programming command consists of the following:
•
•
•
•
•
DS41256A-page 26
Command Request Sequence (A to B)
Command Byte (B to C)
Configuration Byte (C to D)
Manufacturer’s Code Eight Data Bytes (D to G)
Activation and Acknowledge Sequence (G to H)
Preliminary
 2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel and Total
Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2004 Microchip Technology Inc.
Preliminary
DS41256A-page 27
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Boston
Westford, MA
Tel: 978-692-3848
Fax: 978-692-3821
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
England - Berkshire
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Taiwan - Hsinchu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Qingdao
Tel: 86-532-502-7355
Fax: 86-532-502-7205
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
San Jose
Mountain View, CA
Tel: 650-215-1444
Fax: 650-961-0286
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
10/20/04
DS41256A-page 28
Preliminary
 2004 Microchip Technology Inc.
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