Freescale MC34712 3.0 a 1.0 mhz fully integrated ddr switch-mode power supply Datasheet

Freescale Semiconductor
Advance Information
Document number: MC34712
Rev. 5.0, 12/2008
3.0 A 1.0 MHz Fully Integrated
DDR Switch-Mode Power
Supply
34712
The 34712 is a highly integrated, space efficient, low cost, single
synchronous buck switching regulator with integrated N-channel
power MOSFETs. It is a high performance point-of-load (PoL) power
supply with the ability to track an external reference voltage.
Its high efficient 3.0 A sink and source capability combined with its
voltage tracking/sequencing ability and tight output regulation, makes
it ideal to provide the termination voltage (VTT) for modern data buses
such as Double-Data-Rate (DDR) memory buses. It also provides a
buffered output reference voltage (VREF) to the memory chipset
The 34712 offers the designer the flexibility of many control,
supervisory, and protection functions to allow for easy implementation
of complex designs. It is housed in a Pb-free, thermally enhanced,
and space efficient 24 Pin Exposed Pad QFN.
Features
• 50 mΩ integrated N-channel power MOSFETs
• Input voltage operating range from 3.0 to 6.0 V
• ±1% Accurate output voltage, ranging from 0.7 to 1.35 V
• ±1% Accurate buffered reference output voltage
• Programmable switching frequency range from 200 kHz to
1.0 MHz with a default of 1.0 MHz
• Over-current limit and short-circuit protection
• Thermal shutdown
• Output over-voltage and under-voltage detection
• Active low power good output signal
• Active low standby and shutdown inputs
• Pb-free packaging designated by suffix code EP.
VIN
(3.0 TO 6.0 V)
SWITCH-MODE POWER SUPPLY
EP SUFFIX
98ARL10577D
24-PIN QFN
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC34712EP/R2
-40 to 85°C
24 QFN
34712
PVIN
VDDQ
BOOT
VREFIN
VTT
SW
VIN
VDDI
FREQ
GND
SD
VOUT
VDDQ
INV
VREFOUT
PGND
VREF
VIN
DDR MEMORY
CONTROLER
PG
Figure 1. 34712 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007-8. All rights reserved.
MEMORY
BUS
DDR MEMORY
CHIPSET
COMP
MCU
STBY
TERMINATING
RESISTORS
VDDQ
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
STBY
SD
Thermal
Monitoring
Internal
Voltage
Regulator
PG
System
Reset
M1
System
Control
M2
VDDI
Ilimit
BOOT
Current
Monitoring
Isense
FREQ
VIN
Discharge
VIN
VBOOT
PVIN
Oscillator
Prog.
Frequency
Buck
Control
Logic
M3
FSW
Gate
Driver
SW
Isense
PGND
M4
VDDI
Bandgap
Regulator
VBG
Ramp
Generator
COMP
PWM
Comparitor
+
–
VDDI
COMP
Error
Amplifier
VREFIN
+
–
RREF1
INV
–
+
RREF2
Buffer
M5
Discharge
M6
VOUT
Discharge
GND
VREFOUT
Figure 2. 34712 Simplified Internal Block Diagram
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PIN CONNECTIONS
VDDI
VIN
VIN
BOOT
PVIN
PVIN
PIN CONNECTIONS
24
23
22
21
20
19
GND
1
18 PVIN
FREQ
2
17
SW
NC
3
16
SW
15
SW
Transparent
Top View
PG
4
STBY
5
14 PGND
SD
6
13
7
8
9
10
11
12
VREFIN
VREFOUT
COMP
INV
VOUT
PGND
PIN 25
PGND
Figure 3. 34712 Pin Connections
Table 1. 34712 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Pin Number
Pin Name
Pin Function
Formal Name
Definition
1
GND
Ground
Signal Ground
2
FREQ
Passive
3
NC
None
No Connect
No internal connections to this pin
4
PG
Output
Power Good
Active-low (open drain) power-good status reporting pin
5
STBY
Input
Standby
6
SD
Input
Shutdown
7
VREFIN
Input
Voltage Tracking
Reference Input
8
VREFOUT
Output
Reference Voltage
Output
9
COMP
Passive
Compensation
Buck converter external compensation network pin
10
INV
Input
Error Amplifier
Inverting Input
Buck converter error amplifier inverting input pin
11
VOUT
Output
Output Voltage
Discharge FET
Discharge FET drain connection (connect to buck converter output
capacitors)
12,13,14
PGND
Ground
Power Ground
Ground return for buck converter and discharge FET
15,16,17
SW
Output
Switching Node
Buck converter power switching node
18,19,20
PVIN
Supply
Power-circuit Supply
Input
21
BOOT
Passive
Bootstrap
Analog signal ground of IC
Frequency Adjustment Buck converter switching frequency adjustment pin
Standby mode input control pin
Shutdown mode input control pin
Voltage tracking reference voltage input
Buffered output equal to 1/2 of voltage-tracking reference
Buck converter main supply voltage input
Bootstrap switching node (connect to bootstrap capacitor)
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PIN CONNECTIONS
Table 1. 34712 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Pin Number
Pin Name
Pin Function
Formal Name
22,23
VIN
Supply
Logic-circuit Supply
Input
24
VDDI
Passive
Internal Voltage
Regulator
25
GND
Ground
Thermal Pad
Definition
Logic circuits supply voltage input
Internal VDD Regulator (connect filter capacitor to this pin)
Thermal pad for heat transfer. Connect the thermal pad to the analog
ground and the ground plane for heat sinking.
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ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
VIN
-0.3 to 7.0
V
High Side MOSFET Drain Voltage (PVIN) Pin
PVIN
-0.3 to 7.0
V
Switching Node (SW) Pin
VSW
-0.3 to 7.0
V
VBOOT - VSW
-0.3 to 7.0
V
PG, VOUT, SD, and STBY Pins
-
-0.3 to 7.0
V
VDDI, FREQ, INV, COMP, VREFIN, and VREFOUT Pins
-
-0.3 to 3.0
V
IOUT
±3.0
A
Human Body Model
VESD1
±2000
Machine Model (MM)
VESD2
±200
Device Charge Model (CDM)
VESD3
±750
TA
-40 to 85
°C
Storage Temperature
TSTG
-65 to +150
°C
Peak Package Reflow Temperature During Reflow(4),(5)
TPPRT
Note 5
°C
Maximum Junction Temperature
TJ(MAX)
+150
°C
Power Dissipation (TA = 85 °C)(6)
PD
2.9
W
ELECTRICAL RATINGS
Input Supply Voltage (VIN) Pin
BOOT Pin (Referenced to SW Pin)
Continuous Output Current(1)
ESD Voltage(2)
V
THERMAL RATINGS
Operating Ambient Temperature(3)
Notes
1. Continuous output current capability so long as TJ is ≤ TJ(MAX).
2.
ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (MM)
(CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).
3.
4.
The limiting factor is junction temperature, taking into account power dissipation, thermal resistance, and heatsinking.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
Maximum power dissipation at indicated ambient temperature.
5.
6.
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ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
RθJA
139
°C/W
RθJMA
43
°C/W
RθJB
22
°C/W
THERMAL RESISTANCE (7)
Thermal Resistance, Junction to Ambient, Single-layer Board (1s)(8)
(9)
Thermal Resistance, Junction to Ambient, Four-layer Board (2s2p)
Thermal Resistance, Junction to Board
(10)
Notes
7. The PVIN, SW, and GND pins comprise the main heat conduction paths.
8. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
9. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. There are no thermal vias connecting the package to the two planes in the
board.
10. Thermal resistance between the device and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 3.0 V ≤ VIN ≤ 6.0 V, - 40°C ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VIN
3.0
-
6.0
V
IIN
-
-
25
mA
IINQ
-
-
15
mA
IINOFF
-
-
100
µA
VDDI
2.35
2.5
2.65
V
PVIN
2.5
-
6.0
V
VOUT
0.7
-
1.35
V
-
-1.0
-
1.0
%
REGLN
-1.0
-
1.0
%
REGLD
-1.0
-
1.0
%
Error Amplifier Common Mode Voltage Range(12),(15)
VREF
0.0
-
1.35
V
Output Under-voltage Threshold
VUVR
-8.0
-
-1.5
%
Output Over-voltage Threshold
VOVR
1.5
-
8.0
%
Continuous Output Current
IOUT
-3.0
-
3.0
A
Over-current Limit, Sinking and Sourcing
ILIM
-
4.0
-
A
ISHORT
-
6.5
-
A
RDS(ON)HS
10
-
50
mΩ
RDS(ON)LS
10
-
50
mΩ
IC INPUT SUPPLY VOLTAGE (VIN)
Input Supply Voltage Operating Range
Input DC Supply Current(11)
Normal Mode: SD = 1 & STBY = 1, Unloaded Outputs
Input DC Supply Current(11)
Standby Mode, SD = 1 & STBY = 0
Input DC Supply Current(11)
Shutdown Mode, SD = 0 & STBY = X
INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI)
Internal Supply Voltage Range
BUCK CONVERTER (PVIN, SW, GND, BOOT, INV, COMP)
High Side MOSFET Drain Voltage Range
Output Voltage Adjustment Range
Output Voltage
Line
(12)
Accuracy(12),(13),(14)
Regulation(12)
Normal Operation, VIN = 3.0 to 6.0 V, IOUT = ±3.0 A
Load Regulation(12)
Normal Operation, IOUT = -3.0 to 3.0 A
Short-circuit Current Limit
(Sourcing and Sinking)
High Side N-CH Power MOSFET (M3) RDS(ON)(12)
IOUT = 1.0 A, VBOOT - VSW = 3.3 V
Low Side N-CH Power MOSFET (M4) RDS(ON)(12)
IOUT = 1.0 A, VIN = 3.3 V
Notes
11.
12.
13.
14.
15.
See section “MODES OF OPERATION”, page 14 has a detailed description of the different operating modes of the 34712
Design information only, this parameter is not production tested.
±1% is assured at room temperature.
Overall output accuracy is directly affected by the accuracy of the external feedback network, 1% feedback resistors are recommended.
The 1% output voltage regulation is only guaranteed for a common mode voltage range greater than or equal to 0.7 V at room
temperature.
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 3.0 V ≤ VIN ≤ 6.0 V, - 40°C ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
RDS(ON)M2
1.5
-
4.0
Ω
ISW
-10
-
10
µA
(Standby and Shutdown Modes)
IPVIN
-10
-
10
µA
INV Pin Leakage Current
IINV
-1.0
-
1.0
µA
AEA
-
150
-
dB
UGBWEA
-
3.0
-
MHz
SREA
-
7.0
-
V/µs
OFFSETEA
-3.0
0
3.0
mV
TSDFET
-
170
-
°C
TSDHYFET
-
25
-
°C
VFREQ
0.0
-
VDDI
V
VREFIN External Reference Voltage Range(16)
VREFIN
0.0
-
2.7
V
VREFOUT Buffered Reference Voltage Range
VREFOUT
0.0
-
1.35
V
-
-1.0
-
1.0
%
VREFOUT Buffered Reference Voltage Current Capability
IREFOUT
0.0
-
8.0
mA
VREFOUT Buffered Reference Voltage Over-current Limit
IREFOUTLIM
-
11
-
mA
RTDR(M6)
-
50
-
Ω
RTDR(M5)
-
50
-
Ω
IVOUTLKG
-1.0
-
1.0
µA
STBY High Level Input Voltage
VSTBYHI
2.0
-
-
V
STBY Low Level Input Voltage
VSTBYLO
-
-
0.4
V
STBY Pin Internal Pull-up Resistor
M2 RDS(ON)
(VIN = 3.3 V, M2 is on)
SW Leakage Current (Standby and Shutdown modes)
PVIN Pin Leakage Current
Error Amplifier DC Gain
(16)
Error Amplifier Unit Gain
Bandwidth(16)
Error Amplifier Slew Rate
(16)
Error Amplifier Input Offset
Thermal Shutdown
(16)
Threshold(16)
Thermal Shutdown Hysteresis
(16)
OSCILLATOR (FREQ)
Oscillator Frequency Adjusting Reference Voltage Range
TRACKING (VREFIN, VREFOUT, VOUT)
VREFOUT Buffered Reference Voltage
VREFOUT Total Discharge
Accuracy(17)
Resistance(16)
(16)
VOUT Total Discharge Resistance
VOUT Pin Leakage Current
(Standby Mode, VOUT = 3.6 V)
CONTROL AND SUPERVISORY (STBY, SD, PG)
RSTBYUP
1.0
-
2.0
MΩ
SD High Level Input Voltage
VSDHI
2.0
-
-
V
SD Low Level Input Voltage
VSDLO
-
-
0.4
V
SD Pin Internal Pull-up Resistor
RSDUP
1.0
-
2.0
MΩ
VPGLO
-
-
0.4
V
IPGLKG
-1.0
-
1.0
µA
PG Low Level Output Voltage
(IPG = 3.0 mA)
PG Pin Leakage Current
(M1 is off, Pulled up to VIN)
Notes
16. Design information only, this parameter is not production tested.
17. The 1 % accuracy is only guaranteed for VREFOUT greater than or equal to 0.7 V at room temperature.
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0 V ≤ VIN ≤ 6.0 V, - 40°C ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
tRISE
-
14
-
ns
tFALL
-
20
-
ns
Minimum OFF Time
tOFFMIN
-
150
-
ns
Minimum ON Time
tONMIN
-
100
-
ns
(Normal Mode)
tSS
1.3
-
2.6
ms
Over-current Limit Timer
tLIM
-
10
-
ms
tTIMEOUT
80
-
120
ms
tFILTER
5.0
-
25
µs
(FREQ = GND)
FSW
-
1.0
-
MHz
Oscillator Switching Frequency Range
FSW
200
-
1000
kHz
PG Reset Delay
tPGRESET
8.0
-
12
ms
Thermal Shutdown Retry Time-out Period(19)
tTIMEOUT
80
-
120
ms
BUCK CONVERTER (PVIN, SW, GND, BOOT)
Switching Node (SW) Rise Time(19)
(PVIN = 3.3 V, IOUT = ±3.0 A)
Switching Node (SW) Fall Time(19)
(PVIN = 3.3 V, IOUT = ±3.0 A)
Soft Start Duration
Over-current Limit Retry Timeout Period
Output Under-voltage/Over-voltage Filter Delay Timer
OSCILLATOR (FREQ)
Oscillator Default Switching Frequency(18)
CONTROL AND SUPERVISORY (STBY, SD, PG)
Notes
18. Oscillator Frequency tolerance is ±10%.
19. Design information only, this parameter is not production tested.
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Freescale Semiconductor
9
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
In modern microprocessor/memory applications, address
commands and control lines require system level termination
to a voltage (VTT) equal to 1/2 the memory supply voltage
(VDDQ). Having the termination voltage at midpoint, the power
supply insures symmetry for switching times. Also, a
reference voltage (VREF) that is free of any noise or voltage
variations is needed for the DDR SDRAM input receiver,
VREF is also equal to 1/2 VDDQ. Varying the VREF voltage will
effect the setup and hold time of the memory. To comply with
DDR requirements and to obtain best performance, VTT and
VREF need to be tightly regulated to track 1/2 VDDQ across
voltage, temperature, and noise margins. VTT should track
any variations in the DC VREF value (VTT = VREF +/- 40mV),
(See Figure 4) for a DDR system level diagram.
The 34712 supplies the VTT and a buffered VREF output.
To ensure compliance with DDR specifications, the VDDQ line
is applied to the VREFIN pin and divided by 2 internally
through a precision resistor divider. This internal voltage is
then used as the reference voltage for the VTT output. The
same internal voltage is also buffered to give the VREF
voltage at the VREFOUT pin for the application to use without
the need for an external resistor divider. The 34712 provides
the tight voltage regulation and power sequencing/tracking
required along with handling the DDR peak transient current
requirements. Buffering the VREF output helps its immunity
against noise and load changes.
The 34712 utilizes a voltage mode synchronous buck
switching converter topology with integrated low RDS(ON)
(50 mΩ) N-channel power MOSFETs to provide a VTT voltage
with an accuracy of less than ±2.0%. It has a programmable
switching frequency that allows for flexibility and optimization
over the operating conditions and can operate at up to
1.0 MHz to significantly reduce the external components size
and cost. The 34712 can sink and source up to 3.0 A of
continuous current. It provides protection against output
over-current, over-voltage, under-voltage, and overtemperature conditions. It also protects the system from short
circuit events. It incorporates a power-good output signal to
alert the host when a fault occurs.
For boards that support the Suspend-To-RAM (S3) and
the Suspend-To-Disk (S5) states, the 34712 offers the STBY
and the SD pins respectively. Pulling any of these pins low,
puts the IC in the corresponding state.
By integrating the control/supervisory circuitry along with
the Power MOSFET switches for the buck converter into a
space-efficient package, the 34712 offers a complete, smallsize, cost-effective, and simple solution to satisfy the needs
of DDR memory applications.
Besides DDR memory termination, the 34712 can be used
to supply termination for other active buses and graphics card
memory. It can be used in Netcom/Telecom applications like
servers. It can also be used in desktop motherboards, game
consoles, set top boxes, and high end high definition TVs.
VDDQ
VTT
VDDQ
RT
RS
VREF
BUS
DDR Memory Input Receiver
DDR Memory Controller
Figure 4. DDR System Level Diagram
FUNCTIONAL PIN DESCRIPTION
REFERENCE VOLTAGE INPUT (VREFIN)
The 34712 will track 1/2 the voltage applied at this pin.
REFERENCE VOLTAGE OUTPUT (VREFOUT)
This is a buffered reference voltage output that is equal to
1/2 VREFIN. It has a 10 mA current drive capability. This
output is used as the VREF voltage rail and should be filtered
against any noise. Connect a 0.1 µF, 6.0 V low ESR ceramic
filter capacitor between this pin and the GND pin and
between this pin and VDDQ rail. VREFOUT is also used as the
reference voltage for the buck converter error amplifier.
FREQUENCY ADJUSTMENT INPUT (FREQ)
The buck converter switching frequency can be adjusted
by connecting this pin to an external resistor divider between
VDDI and GND pins. The default switching frequency (FREQ
pin connected to ground, GND) is set at 1.0 MHz.
SIGNAL GROUND (GND)
Analog ground of the IC. Internal analog signals are
referenced to this pin voltage.
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FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI)
POWER INPUT VOLTAGE (PVIN)
This is the output of the internal bias voltage regulator.
Connect a 1.0 µF, 6.0 V low ESR ceramic filter capacitor
between this pin and the GND pin. Filtering any spikes on this
output is essential to the internal circuitry stable operation.
Buck converter power input voltage. This is the drain of the
buck converter high side power MOSFET.
OUTPUT VOLTAGE DISCHARGE PATH (VOUT)
Output voltage of the Buck Converter is connected to this
pin. it only serves as the output discharge path once the SD
signal is asserted.
BOOTSTRAP INPUT (BOOT)
Bootstrap capacitor input pin. Connect a capacitor (as
discussed on page 19) between this pin and the SW pin to
enhance the gate of the high side Power MOSFET during
switching.
SHUTDOWN INPUT (SD)
ERROR AMPLIFIER INVERTING INPUT (INV)
COMPENSATION INPUT (COMP)
If this pin is tied to the GND pin, the device will be in
Shutdown mode. If left unconnected or tied to the VIN pin, the
device will be in Normal mode. The pin has an internal pullup of 1.5 MΩ. This input accepts the S5 (Suspend-To-Disk)
control signal.
Buck converter external compensation network connects
to this pin. Use a type III compensation network.
STANDBY INPUT (STBY)
Buck converter error amplifier inverting input. Connect the
VTT voltage directly to this pin.
INPUT SUPPLY VOLTAGE (VIN)
IC power supply input voltage. Input filtering is required for
the device to operate properly.
POWER GROUND (PGND)
Buck converter and discharge MOSFETs power ground. It
is the source of the buck converter low side power MOSFET.
SWITCHING NODE (SW)
Buck converter switching node. This pin is connected to
the output inductor.
If this pin is tied to the GND pin, the device will be in
Standby mode. If left unconnected or tied to the VIN pin, the
device will be in Normal mode. The pin has an internal pullup of 1.5 MΩ. This input accepts the S3 (Suspend-To-RAM)
control signal.
POWER GOOD OUTPUT SIGNAL (PG)
This is an active low open drain output that is used to
report the status of the device to a host. This output activates
after a successful power up sequence and stays active as
long as the device is in normal operation and is not
experiencing any faults. This output activates after a 10 ms
delay and must be pulled up by an external resistor to a
supply voltage (e.g.,VIN.).
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Freescale Semiconductor
11
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34712 - Functional Block Diagram
Internal Bias Circuits
System Control and Logic
Oscillator
Protection Functions
Control and
Supervisory Functions
Tracking and Sequencing
Buck Converter
Figure 5. 34712 Internal Block Diagram
INTERNAL BIAS CIRCUITS
This block contains all circuits that provide the necessary
supply voltages and bias currents for the internal circuitry. It
consists of:
• Internal voltage supply regulator: This regulator
supplies the VDDI voltage that is used to drive the digital/
analog internal circuits. It is equipped with a Power-OnReset (POR) circuit that watches for the right regulation
levels. External filtering is needed on the VDDI pin. This
block will turn off during the shutdown mode.
• Internal bandgap reference voltage: This supplies the
reference voltage to some of the internal circuitry.
• Bias circuit: This block generates the bias currents
necessary to run all of the blocks in the IC.
SYSTEM CONTROL AND LOGIC
This block is the brain of the IC where the device
processes data and reacts to it. Based on the status of the
STBY and SD pins, the system control reacts accordingly and
orders the device into the right status. It also takes inputs
from all of the monitoring/protection circuits and initiates
power up or power down commands. It communicates with
the buck converter to manage the switching operation and
protects it against any faults.
OSCILLATOR
This block generates the clock cycles necessary to run the
IC digital blocks. It also generates the buck converter
switching frequency. The switching frequency has a default
value of 1.0 MHz and can be programmed by connecting a
resistor divider to the FREQ pin, between VDDI and GND
pins (See Figure 1).
PROTECTION FUNCTIONS
This block contains the following circuits:
• Over-current limit and short-circuit detection: This block
monitors the output of the buck converter for over
current conditions and short circuit events and alerts the
system control for further command.
• Thermal limit detection: This block monitors the
temperature of the device for overheating events. If the
temperature rises above the thermal shutdown
threshold, this block will alert the system control for
further commands.
• Output over-voltage and under-voltage monitoring: This
block monitors the buck converter output voltage to
ensure it is within regulation boundaries. If not, this
block alerts the system control for further commands.
CONTROL AND SUPERVISORY FUNCTIONS
This block is used to interface with an outside host. It
contains the following circuits:
• Standby control input: An outside host can put the
34712 device into standby mode (S3 or Suspend-ToRAM mode) by sending a logic “0” to the STBY pin.
• Shutdown control input: An outside host can put the
34712 device into shutdown mode (S5 or Suspend-ToDisk mode) by sending a logic “0” to the SD pin.
• Power good output signal PG: The 34712 can
communicate to an external host that a fault has
34712
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
occurred by releasing the drive on the PG pin high,
allowing the signal/pin to be pulled high by the external
pull-up resistor.
TRACKING AND SEQUENCING
This block allows the output of the 34712 to track 1/2 the
voltage applied at the VREFIN pin. This allows the VREF and
VTT voltages to track 1/2 VDDQ and assures that none of them
will be higher than VDDQ at any point during normal operating
conditions. For power down during a shutdown (S5) mode,
the 34712 uses internal discharge MOSFETs (M5 and M6 on
Figure 2) to discharge VTT and VREF respectively. These
discharge MOSFETs are only active during shutdown mode.
Using this block along with controlling the SD and STBY pins
can offer the user power sequencing capabilities by
controlling when to turn the 34712 outputs on or off.
BUCK CONVERTER
This block provides the main function of the 34712: DC to
DC conversion from an un-regulated input voltage to a
regulated output voltage used by the loads for reliable
operation. The buck converter is a high performance, fixed
frequency (externally adjustable), synchronous buck PWM
voltage-mode control. It drives integrated 50 mΩ N-channel
power MOSFETs saving board space and enhancing
efficiency. The switching regulator output voltage is
adjustable with an accuracy of less than ±2.0% to meet DDR
requirements. Its output has the ability to track 1/2 the voltage
applied at the VREFIN pin. The regulator's voltage control
loop is compensated using a type III compensation network,
with external components to allow for optimizing the loop
compensation, for a wide range of operating conditions. A
typical Bootstrap circuit with an internal PMOS switch is used
to provide the voltage necessary to properly enhance the
high-side MOSFET gate.
The 34712 is designed to address DDR memory power
supplies. The integrated converter has the ability to both sink
and source up to 3.0 A of continuous current, making it
suitable for bus termination power supplies.
34712
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SD = 1 &
STBY=0
VIN < 3.0 V
SD = 0 &
STBY=x
Shutdown
VTT = Discharge
VREF = Discharge
PG = 1
Power Off
VTT=OFF
VREF=OFF
PG = 1
Standby
VTT = OFF
VREF = ON
PG = 1
3.0 V<=VIN<=6.0 V
SD = 1 &
STBY=1
SD = 1 &
STBY=1
IOUT>=ISHORT
VTT>VOV
Over-voltage
VTT=ON
VREF=ON
Normal
VTT = ON
VREF=ON
VTT<VOV
VTT=OFF
VREF=OFF
PG = 1
PG = 0
PG = 1
TJ<=145°C
TIMEOUT Expired
VTT>VUV
TIMEOUT
Expired
Over-current
Under-voltage
VTT<VUV
Short-circuit
TIMEOUT
Expired
VTT=ON
VREF=ON
Thermal Shutdown
VTT=OFF
VREF=OFF
PG = 1
PG = 1
VTT=OFF
VREF=ON
PG = 1
IOUT1>=ILIM1
For>=10 ms
TJ >= 170°C
Figure 6. Operation Modes Diagram
MODES OF OPERATION
The 34712 has three primary modes of operation:
Normal Mode
In normal mode, all functions and outputs are fully
operational. To be in this mode, the VIN needs to be within its
operating range, both Shutdown and Standby inputs are
high, and no faults are present. This mode consumes the
most amount of power.
Standby Mode
This mode is predominantly used in Desktop memory
solutions where the DDR supply is desired to be ACPI
compliant (Advanced Configuration and Power Interface).
When this mode is activated by pulling the STBY pin low, VTT
is put in High Z state, IOUT = 0 A, and VREF stays active. This
is the S3 state Suspend-To-Ram or Self Refresh mode and it
is the lowest DRAM power state. In this mode, the DRAM will
preserve the data. While in this mode, the 34712 consumes
less power than in the normal mode, because the buck
converter and most of the internal blocks are disabled.
Shutdown Mode
In this mode, activated by pulling the SD pin low, the chip
is in a shutdown state and the outputs are all disabled and
discharged. This is the S4/S5 power state or Suspend-ToDisk state, where the DRAM will loose all of its data content
(no power supplied to the DRAM). The reason to discharge
the VTT and VREF lines is to ensure upon exiting, the
Shutdown Mode that VTT and VREF are lower than VDDQ,
otherwise VTT can remain floating high, and be higher than
VDDQ upon powering up. In this mode, the 34712 consumes
the least amount of power since almost all of the internal
blocks are disabled.
START-UP SEQUENCE
When power is first applied, the 34712 checks the status
of the SD and STBY pins. If the device is in a shutdown mode,
no block will power up and the output will not attempt to ramp.
If the device is in a standby mode, only the VDDI internal
supply voltage and the bias currents are established and no
further activities will occur. Once the SD and STBY pins are
released to enable the device, the internal VDDI POR signal is
also released. The rest of the internal blocks will be enabled
34712
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
and the buck converter switching frequency value is
determined by reading the FREQ pin. A soft start cycle is then
initiated to ramp up the output of the buck converter (VTT).
The buck converter error amplifier uses the voltage on the
VREFOUT pin (VREF) as its reference voltage. VREF is equal
to 1/2 VDDQ, where VDDQ is applied to the VREFIN pin. This
way, the 34712 assures that VREF and VTT voltages track 1/2
VDDQ to meet DDR requirements.
Soft start is used to prevent the output voltage from
overshooting during startup. At initial startup, the output
capacitor is at zero volts; VOUT = 0 V. Therefore, the voltage
across the inductor will be PVIN during the capacitor charge
phase which will create a very sharp di/dt ramp. Allowing the
inductor current to rise too high can result in a large
difference between the charging current and the actual load
current that can result in an undesired voltage spike once the
capacitor is fully charged. The soft start is active each time
the IC goes out of standby or shutdown mode, power is
recycled, or after a fault retry.
To fully take advantage of soft starting, it is recommended
not to enable the 34712 output before introducing VDDQ on
the VREFIN pin. If this happens after a soft start cycle expires
and the VREFIN voltage has a high dv/dt, the output will
naturally track it immediately and ramp up with a fast dv/dt
itself and that will defeat the purpose of soft starting. For
reliable operation, it is best to have the VDDQ voltage
available before enabling the output of the 34712.
After a successful start-up cycle where the device is
enabled, no faults have occurred, and the output voltage has
reached its regulation point, the 34712 pulls the power good
output signal low after a 10ms reset delay, to indicate to the
host that the device is in normal operation.
PROTECTION AND DIAGNOSTIC FEATURES
The 34712 monitors the application for several fault
conditions to protect the load from overstress. The reaction of
the IC to these faults ranges from turning off the outputs to
just alerting the host that something is wrong. In the following
paragraphs, each fault condition is explained:
Output Over-voltage
An over-voltage condition occurs once the output voltage
goes higher than the rising over-voltage threshold (VOVR). In
this case, the power good output signal is pulled high, alerting
the host that a fault is present, but the VTT and VREF outputs
will stay active. To avoid erroneous over-voltage conditions,
a 20 µs filter is implemented. The buck converter will use its
feedback loop to attempt to correct the fault. Once the output
voltage falls below the falling over-voltage threshold (VOVF),
the fault is cleared and the power good output signal is pulled
low, the device is back in normal operation.
Output Under-voltage
An under-voltage condition occurs once the output voltage
falls below the falling under-voltage threshold (VUVF). In this
case, the power good output signal is pulled high, alerting the
host that a fault is present, but the VTT and VREF outputs will
stay active. To avoid erroneous under-voltage conditions, a
20 µs filter is implemented. The buck converter will use its
feedback loop to attempt to correct the fault. Once the output
voltage rises above the rising under-voltage threshold
(VUVR), the fault is cleared and the power good output signal
is pulled low, the device is back in normal operation.
Output Over-current
This block detects over-current in the Power MOSFETs of
the buck converter. It is comprised of a sense MOSFET and
a comparator. The sense MOSFET acts as a current
detecting device by sampling a ratio of the load current. That
sample is compared via the comparator with an internal
reference to determine if the output is in over-current or not.
If the peak current in the output inductor reaches the over
current limit (ILIM), the converter will start a cycle-by-cycle
operation to limit the current, and a 10 ms over-current limit
timer (tLIM) starts. The converter will stay in this mode of
operation until one of the following occurs:
• The current is reduced back to the normal level before
tLIM expires, and in this case normal operation is
regained.
• tLIM expires without regaining normal operation, at
which point the device turns off the output and the
power good output signal is pulled high. At the end of a
timeout period of 100 ms (tTIMEOUT), the device will
attempt another soft start cycle.
• The device reaches the thermal shutdown limit (TSDFET)
and turns off the output. The power good output signal
is pulled high.
Short-circuit Current Limit
This block uses the same current detection mechanism as
the over-current limit detection block. If the load current
reaches the ISHORT value, the device reacts by shutting down
the output immediately. This is necessary to prevent damage
in case of a permanent short circuit. Then, at the end of a
timeout period of 100 ms (tTIMEOUT), the device will attempt
another soft start cycle.
Thermal Shutdown
Thermal limit detection block monitors the temperature of
the device and protects against excessive heating. If the
temperature reaches the thermal shutdown threshold
(TSDFET), the converter output switches off and the power
good output signal indicates a fault by pulling high. The
device will stay in this state until the temperature has
decreased by the hysteresis value and then After a timeout
period (TTIMEOUT) of 100 ms, the device will retry
automatically and the output will go through a soft start cycle.
If successful normal operation is regained, the power good
output signal is asserted low to indicate that.
34712
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
TYPICAL APPLICATIONS
PROTECTION AND DIAGNOSTIC FEATURES
TYPICAL APPLICATIONS
BOOT
VIN
Compensation Network
C15
0.1 μF
VDDI
PVIN
VOUT
SW
x
4
PG
PGOOD LED
VMASTER
VMASTER
R8
10 k_nopop
5
STBY
VIN
3
6
SD
R7
1k
PVIN
NC
SW
MC34712
PG
SW
STBY
SD
GND
8
9
10
11
18
17
16
SW
SW
15
14
GND
13
GND
12
VREFIN
C13
0.1 μF
D1
LED
R9
10 k_nopop
INV
C11
0.1 μF
COMP
C12
0.1 μF
LED
VREFOUT
VOUT
I/O Signals
VIN Capacitors
Jumpers
4.7_nopop
VIN
C17
10 μF
PVIN
VIN
VIN
SW
FREQ
7
VREFIN
PVIN
GND
R2
12.7 k_nopop
SGND
19
VOUT
2
20
BOOT
1
R11
10 k
21
INV
C19
1.9 nF
R1
20 k
22
COMP
R14
300
23
VREFOUT
R15
15 k
C20
1.0 nF
24
VDDI
COMP
FREQ
C18
0.02 pF
PVIN
C14
0.1 μF
VREFIN
R12
10 k_nopop
INV
R16
PVIN
VIN
GND
C16
0.1 μF
GND
VMASTER
VOUT
Optional nopop
J2
3
2
1
3
2
1
J3
PVIN
VMASTER
STBY_nopop
LED
1
2
1
1
3
5
7
9
J1
2
4
6
8
10
VREFIN
PG
STBY
SD
2
CON10A
SD
VDDI
Buck Converter
FREQ
R6
POT_50 k_nopop
SW
PVIN Capacitors
D3
PMEG2010EA
_nopop
L1
1.5 μH
VOUT2
VOUT1
VOUT
R3
4.7_nopop
C7
C6
C8
C9
100 μF 100 μF
100 μF
1 nF_nopop
PVIN
C1
0.1 μF
C2
1.0 μF
C3
C4
C5
100 μF 100 μF 100 μF
34712
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
PROTECTION AND DIAGNOSTIC FEATURES
COMPONENT SELECTION
SELECTION OF THE INDUCTOR
Inductor calculation is straight forward, being
SWITCHING FREQUENCY SELECTION
The switching frequency defaults to a value of 1.0 MHz
when the FREQ pin is grounded, and 200 kHz when the
FREQ pin is connected to VDDI. Intermediate switching
frequencies can be obtained by connecting an external
resistor divider to the FREQ pin. The table below shows the
resulting switching frequency versus FREQ pin voltage.
where,
Table 5. Switching Frequency Adjustment
FREQUENCY
VOLTAGE APPLIED TO PIN FREQ
200
2.341 – 2.500
253
2.185 - 2.340
307
2.029 - 2.184
360
1.873 - 2.028
413
1.717 – 1.872
466
1.561 – 1.716
520
1.405 - 1.560
573
1.249 - 1.404
627
1.093 - 1.248
680
0.936 - 1.092
733
0.781 - 0.936
787
0.625 - 0.780
840
0.469 - 0.624
893
0.313 - 0.468
947
0.157 - 0.312
1000
0.000 - 0.156
RFQH
Maximum OFF time percentage
Switching period.
Drain – to – source resistance of FET
Winding resistance of Inductor
Output current ripple.
OUTPUT FILTER CAPACITOR
For the output capacitor, the following considerations are
more important than the actual capacitance value, the
physical size, the ESR and the voltage rating:
Transient Response percentage, TR_%
(Use a recommended value of 2 to 4% to assure a good
transient response.)
Maximum Transient Voltage, TR_v_dip = Vo*TR_%
Maximum current step,
VDDI
FREQ
RFQL
Inductor Current rise time,
GND
Figure 7. Resistor Divider for Frequency Adjustment
where,
D_max = Maximum ON time percentage.
IO = Rated output current.
Vin_min = Minimum input voltage at PVIN
34712
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
TYPICAL APPLICATIONS
PROTECTION AND DIAGNOSTIC FEATURES
As a result, it is possible to calculate
Gate
Driver
FSW
SW
PWM
Comparitor
L
+
–
In order to find the maximum allowed ESR,
VOUT
Ramp
Generator
RS
Error
Amplifier
–
+
VREFOUT
RO CO
CS
INV
RF
CX
CF
COMP
The effects of the ESR is often neglected by the designers
and may present a hidden danger to the ultimate supply
stability. Poor quality capacitors have widely disparate ESR
value, which can make the closed loop response
inconsistent.
34712
Figure 9. Type III Compensation Network
Consider the crossover frequency, FCROSS, of the open loop
gain at one-tenth of the switching frequency, FSW.
Io
Then,
10
F CROSS = ---------------------------2π • R O C F
Io_step
Current
response
dt_I_rise
Worst case
assumption
⇒
10
C F = --------------------------------------2π • R O F CROSS
where RO is a user selected resistor. Knowing the LC
frequency, it can be obtained the values of RF and CS:
Figure 8. Transient Parameters
TYPE III COMPENSATION NETWORK
Power supplies are desired to offer accurate and tight
regulation output voltages. To accomplish this requires a high
DC gain. But with high gain comes the possibility of instability.
The purpose of adding compensation to the internal error
amplifier is to counteract some of the gains and phases
contained in the control-to-output transfer function that could
jeopardized the stability of the power supply. The Type III
compensation network used for 34712 comprises two poles
(one integrator and one high frequency pole to cancel the
zero generated from the ESR of the output capacitor) and two
zeros to cancel the two poles generated from the LC filter as
shown in Figure 9.
This gives as a result,
&
Calculate Rs by placing the Pole 1 at the ESR zero
frequency:
34712
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
PROTECTION AND DIAGNOSTIC FEATURES
stay enhanced. A 0.1 μF capacitor is a good value for this
bootstrap element.
LAYOUT GUIDELINES
⇒
Equating the Pole 2 to 5 times the Crossover Frequency to
achieve a faster response and a proper phase margin,
5 • F CROSS = F
1
---------------------------------------P2 =
CF CX
2π • R F --------------------CF + CX
⇒
BOOTSTRAP CAPACITOR
The bootstrap capacitor is needed to supply the gate
voltage for the high side MOSFET. This N-Channel MOSFET
needs a voltage difference between its gate and source to be
able to turn on. The high side MOSFET source is the SW
node, so it is not ground and it is floating and moving in
voltage, so we cannot just apply a voltage directly to the gate
of the high side that is referenced to ground, we need a
voltage referenced to the SW node. That is why the bootstrap
capacitor is needed for. This capacitor charges during the
high side off time, since the low side will be on during that
time, so the SW node and the bottom of the bootstrap
capacitor will be connected to ground and the top of the
capacitor will be connected to a voltage source, so the
capacitor will charge up to that voltage source (say 5.0 V).
Now when the low side MOSFET switches off and the high
side MOSFET switches on, the SW nodes rises up to Vin,
and the voltage on the boot pin will be Vcap + Vin. So the gate
of the high side will have Vcap across it and it will be able to
The layout of any switching regulator requires careful
consideration. First, there are high di/dt signals present, and
the traces carrying these signals need to be kept as short and
as wide as possible to minimize the trace inductance, and
therefore reduce the voltage spikes they can create. To do
this, an understanding of the major current carrying loops is
important. See Figure 10. These loops, and their associated
components, should be placed in such a way as to minimize
the loop size to prevent coupling to other parts of the circuit.
Also, the current carrying power traces and their associated
return traces should run adjacent to one another, to minimize
the amount of noise coupling. If sensitive traces must cross
the current carrying traces, they should be made
perpendicular to one another to reduce field interaction.
Second, small signal components which connect to
sensitive nodes need consideration. The critical small signal
components are the ones associated with the feedback
circuit. The high impedance input of the error amp is
especially sensitive to noise, and the feedback and
compensation components should be placed as far from the
switch node, and as close to the input of the error amplifier as
possible. Other critical small signal components include the
bypass capacitors for VIN, VREFIN, and VDDI. Locate the
bypass capacitors as close to the pin as possible.
The use of a multi-layer printed circuit board is
recommended. Dedicate one layer, usually the layer under
the top layer, as a ground plane. Make all critical component
ground connections with vias to this layer. Make sure that the
power ground, PGND, is connected directly to the ground
plane and not routed through the thermal pad or analog
ground. Dedicate another layer as a power plane and split
this plane into local areas for common voltage nets.
The IC input supply (VIN) should be connected with a
dedicated trace to the input supply. This will help prevent
noise from the Buck Regulator's power input (PVIN) from
injecting switching noise into the IC’s analog circuitry.
In order to effectively transfer heat from the top layer to the
ground plane and other layers of the printed circuit board,
thermal vias need to be used in the thermal pad design. It is
recommended that 5 to 9 vias be spaced evenly and have a
finished diameter of 0.3 mm.
34712
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
TYPICAL APPLICATIONS
PROTECTION AND DIAGNOSTIC FEATURES
VIN1
VIN2PVIN
and 3
Loop Curr ent
HS ON
HS
SW3
SW2 and
SW1
SD
Loop Curr ent
HS ON
HS
Loop
Current
SD ON
Loop
Current
LS ON
LS
GND2
and 3
PGND
BUCK
CONVERTER 1
BuckCONVERTER
Converter
BUCK
2 and 3
Figure 10. Current Loops
34712
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
EP SUFFIX
24 -PIN
98ARL10577D
ISSUE B
34712
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
PACKAGING
PACKAGING DIMENSIONS
EP SUFFIX
24 -PIN
98ARL10577D
ISSUE B
34712
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
1.0
2/2006
•
•
Pre-release version
Implemented Revision History page
2.0
11/2006
•
•
•
Initial release
Converted format from Market Assessment to Product Preview
Major updates to the data, form, and style
3.0
2/2007
•
•
•
Replaced all electrolytic capacitors with ceramic ones in Figure 1
Deleted Deadtime in Dynamic Electrical Characteristics
Moved Figures 8 ahead of TYPE III COMPENSATION NETWORK
4.0
5/2007
•
•
•
•
Changed Features fom 2% to 1%
Changed 34712 Simplified Application Diagram
Removed Machine Model in Maximum Ratings
Added minimum limits to Input DC Supply Current(11) Normal mode, Input DC Supply Current(11)
Standby mode, and Input DC Supply Current(11) Shutdown mode
Added High Side MOSFET Drain Voltage Range
Changed Output Voltage Accuracy(12),(13),(14)
Changed Short-circuit Current Limit
Changed High Side N-CH Power MOSFET (M3) RDS(ON)(12) and Low Side N-CH Power MOSFET
(M4) RDS(ON)(12)
Changed M2 RDS(ON)
Changed PVIN Pin Leakage Current
Changed VREFOUT Buffered Reference Voltage Accuracy(17), VREFOUT Buffered Reference
Voltage Current Capability, and VREFOUT Buffered Reference Voltage Over-current Limit
Changed STBY Pin Internal Pull-up Resistor and SD Pin Internal Pull-up Resistor
Changed Soft Start Duration, Over-current Limit Retry Timeout Period, and Output Under-voltage/
Over-voltage Filter Delay Timer
Changed Oscillator Default Switching Frequency(18)
Changed PG Reset Delay and Thermal Shutdown Retry Time-out Period(19)
Changed drawings in Typical Applications
Changed drawing in Type III Compensation Network
Removed PC34712EP/R2 from the ordering information and added MC34712EP/R2
Changed the data sheet status to Advance Information
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
5.0
12/2007
•
•
•
•
Made changes to Switching Node (SW) Pin, BOOT Pin (Referenced to SW Pin), Output Undervoltage Threshold, Output Over-voltage Threshold, High Side N-CH Power MOSFET (M3)
RDS(ON)(12), Low Side N-CH Power MOSFET (M4) RDS(ON)(12), Device Charge Model (CDM)
Added Machine Model (MM), SW Leakage Current (Standby and Shutdown modes), Error Amplifier
DC Gain(16), Error Amplifier Unit Gain Bandwidth(16), Error Amplifier Slew Rate(16), Error Amplifier
Input Offset(16)
Added pin 25 to Figure 3 and the 34712 Pin Definitions
Added the section Layout Guidelines
34712
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
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MC34712
Rev. 5.0
12/2008
Information in this document is provided solely to enable system and software
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Freescale Semiconductor reserves the right to make changes without further notice to
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