TI CD74FCT646EN Bicmos fct interface logic, octal bus transceiver/register, three-state Datasheet

CD74FCT646
Data sheet acquired from Harris Semiconductor
SCHS261
January 1997
Features
BiCMOS FCT Interface Logic,
Octal Bus Transceiver/Register, Three-State
D
ENDE
M
M
O
S
EC
IGN
NOT R NEW DES ology
n
FOR OS Tech
M
Use C
Description
The CD74FCT646 three-state octal bus transceiver/register
uses a small geometry BiCMOS technology. The output
stage is a combination of bipolar and CMOS transistors that
limits the output HIGH level to two diode drops below VCC.
This resultant lowering of output swing (0V to 3.7V)
reduces power bus ringing (a source of EMI) and minimizes
VCC bounce and ground bounce and their effects during
simultaneous output switching. The output configuration
also enhances switching speed and is capable of sinking
64 milliamperes.
• Buffered Inputs
• Typical Propagation Delay: 6.8ns at VCC = 5V,
TA = 25oC, CL = 50pF
• Noninverting
• SCR Latchup Resistant BiCMOS Process and
Circuit Design
• Speed of Bipolar FAST™/AS/S
• 64mA Output Sink Current
• Output Voltage Swing Limited to 3.7V at VCC = 5V
• Controlled Output Edge Rates
• Input/Output Isolation to VCC
• BiCMOS Technology with Low Quiescent Power
Ordering Information
PART NUMBER
TEMP.
RANGE (oC)
PKG.
NO.
PACKAGE
CD74FCT646EN
0 to 70
24 Ld PDIP
E24.3
CD74FCT646M
0 to 70
24 Ld SOIC
M24.3
CD74FCT646SM
0 to 70
24 Ld SSOP
M24.209
NOTE: When ordering the suffix M and SM packages, use the entire
part number. Add the suffix 96 to obtain the variant in the tape and reel.
This device is a bus transceiver with D-Type flip-flops which
act as internal storage registers on the LOW to HIGH transition of either CAB or CBA clock inputs. Output Enable (OE)
and Direction (DIR) inputs control the transceiver functions.
Data present at the high impedance output can be stored in
either register or both but only one of the two buses can be
enabled as outputs at any one time. The Select controls
(SAB and SBA) can multiplex stored and transparent (real
time) data. The Direction control determines which data bus
will receive data when the Output Enable (OE) is LOW. In the
high impedance mode (Output Enable HIGH), A data can be
stored in one register and B data can be stored in the other
register. The clocks are not gated with the Direction (DIR)
and Output Enable (OE) terminals; data at the A or B terminals can be clocked into the storage flip-flops at any time.
Pinout
CD74FCT646
(PDIP, SOIC, SSOP)
TOP VIEW
CAB
1
24 VCC
SAB
2
23 CBA
DIR
3
22 SBA
A0
4
21 OE
A1
5
20 B0
A2
6
19 B1
A3
7
18 B2
A4
8
17 B3
A5
9
16 B4
A6 10
15 B5
A7 11
14 B6
GND 12
13 B7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1997
8-67
File Number
2393.2
CD74FCT646
Functional Diagram
A0
A1
A2
A3
A DATA PORT
A4
A5
A6
A7
FLIP-FLOP
CLOCKS
4
20
5
19
6
18
7
17
8
16
9
15
10
14
11
13
21
3
1
23
OE
DIR
CAB CLOCK
CBA CLOCK
2
22
B0
B1
B2
B3
B DATA PORT
B4
B5
B6
B7
SAB SOURCE
SBA SOURCE
DATA SOURCE
SELECTION
INPUTS
GND = PIN 12
VCC = PIN 24
TRUTH TABLE (Note 1)
INPUTS
DATA I/O (Note 2)
A0 THRU A7
B0 THRU B7
OPERATION OR FUNCTION
OE
DIR
CAB
CBA
SAB
SBA
CD74FCT646
X
X
X
X
↑
X
X
↑
X
X
X
X
Input
Not Specified
Not Specified
Input
Store A, B Unspecified
Store B, A Unspecified
H
H
X
X
↑
H or L
↑
H or L
X
X
X
X
Input
Input
Store A and B Data
Isolation, Hold Storage
L
L
L
L
X
X
X
H or L
X
X
L
H
Output
Input
Real Time B Data to A Bus
Stored B Data to A Bus
L
L
H
H
X
H or L
X
X
L
H
X
X
Input
Output
Real Time A Data to B Bus
Stored A Data to B Bus
NOTES:
1. H= HIGH Voltage Level
L = LOW Voltage Level
↑ = Transition from Low to High
X = Immaterial
2. The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every low to high transition of the clock inputs. To prevent excess currents in the high Z
modes, all I/O terminals should be terminated with 10kΩ resistors.
8-68
CD74FCT646
IEC Logic Symbol
CD74FCT646
21
3
22
2
23
1
4
G3
3EN1
3EN2
G6
G7
>C4
>C5
4D
1 ≥1 6
6
5D
7 ≥1
2
7
20
5
19
6
18
7
17
8
16
9
15
10
14
11
13
8-69
CD74FCT646
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Diode Current, IIK (For VI < -0.5V) . . . . . . . . . . . . . . . . . . -20mA
DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA
DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . . 70mA
DC Output Source Current per Output Pin, IO . . . . . . . . . . . . -30mA
DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140mA
DC Ground Current (IGND). . . . . . . . . . . . . . . . . . . . . . . . . . . 528mA
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC and SSOP-Lead Tips Only)
Operating Conditions
Operating Temperature Range, TA . . . . . . . . . . . . . . . . .0oC to 70oC
Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . .4.75V to 5.25V
DC Input Voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC
DC Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ VCC
Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Commercial Temperature Range 0oC to 70oC, VCC Max = 5.25V, VCC Min = 4.75V (Note 6)
AMBIENT TEMPERATURE (TA)
25oC
TEST CONDITIONS
PARAMETER
SYMBOL
VI (V)
IO (mA)
0oC TO 70oC
VCC (V)
MIN
MAX
MIN
MAX
UNITS
High Level Input Voltage
VIH
4.75 to 5.25
2
-
2
-
V
Low Level Input Voltage
VIL
4.75 to 5.25
-
0.8
-
0.8
V
High Level Output Voltage
VOH
VIH or VIL
-15
Min
2.4
-
2.4
-
V
Low Level Output Voltage
VOL
VIH or VIL
64
Min
-
0.55
-
0.55
V
High Level Input Current
IIH
VCC
Max
-
0.1
-
1
µA
Low Level Input Current
IIL
GND
Max
-
-0.1
-
-1
µA
IOZH
VCC
Max
-
0.5
-
10
µA
IOZL
GND
Max
-
-0.5
-
-10
µA
Input Clamp Voltage
VIK
VCC or
GND
Min
-
-1.2
-
-1.2
V
Short Circuit Output Current
(Note 4)
IOS
VO = 0
VCC or
GND
Max
-60
-
-60
-
mA
Quiescent Supply Current,
MSI
ICC
VCC or
GND
Max
-
8
-
80
µA
∆ICC
3.4V
(Note 5)
Max
-
1.6
-
1.6
mA
Three-State Leakage Current
Additional Quiescent Supply
Current per Input Pin
TTL Inputs High, 1 Unit Load
-18
0
NOTES:
4. Not more than one output should be shorted at one time. Test duration should not exceed 100ms.
5. Inputs that are not measured are at VCC or GND.
6. FCT Input Loading: All inputs are 1 unit load. Unit load is ∆ICC limit specified in Electrical Specifications table, e.g., 1.6mA Max. at 70oC.
8-70
CD74FCT646
Switching Specifications Over Operating Range FCT Series tr, tf = 2.5ns, CL = 50pF, RL (Figure 1) (Note 7)
25oC
PARAMETER
SYMBOL
Propagation Delays
VCC (V)
0oC TO 70oC
TYP
MIN
MAX
UNITS
(Note 8)
Store An → Bn, Store Bn → An, An → Bn, Bn → An
tPLH, tPHL
5
6.8
2
9
ns
Select to Data
tPLH, tPHL
5
8.3
2
11
ns
Output Enable to Output
tPZL, tPZH
5
10.5
2
14
ns
Output Disable to Output
tPLZ, tPHZ
5
6.8
2
9
ns
CPD
(Note 8)
-
-
-
-
pF
Minimum (Valley) VOHV During Switching of
Other Outputs (Output Under Test Not Switching)
VOHV
5
0.5
-
-
V
Maximum (Peak) VOLP During Switching of
Other Outputs (Output Under Test Not Switching)
VOLP
5
1
-
-
V
CI
-
-
-
10
pF
CI/O
-
-
-
15
pF
Power Dissipation Capacitance
Input Capacitance
Input/Output Capacitance
NOTES:
7. 5V: Minimum is at 5.25V for 0oC to 70oC, Maximum is at 4.75V for 0oC to 70oC, Typical is at 5V.
8. CPD, measured per flip-flop, is used to determine the dynamic power consumption.
PD (per package) = VCC ICC + Σ(VCC2 fI CPD + VO2 fOCL + VCC ∆ICC D) where:
VCC = supply voltage
∆ICC = flow through current x unit load
CL = output load capacitance
D = duty cycle of input high
fO = output frequency
fI = input frequency
Prerequisite For Switching
25oC
PARAMETER
0oC TO 70oC
SYMBOL
VCC (V)
TYP
MIN
MAX
UNITS
fMAX
5
(Note 9)
-
85
-
ns
Data to Clock Setup Time
tSU
5
-
4
-
ns
Data to Clock Hold Time
tH
5
-
2
-
ns
Clock Pulse Width
tW
5
-
6
-
ns
Maximum Frequency
NOTE:
9. 5V: Minimum is at 4.75V for 0oC to 70oC, Typical is at 5V.
8-71
Test Circuits and Waveforms
VCC
tr, tf = 2.5ns
(NOTE 10)
VI
3V
0
PULSE ZO
GEN
SWITCH POSITION
7V
500Ω
RL
V0
DUT
CL
50pF
RT
RT = ZO
500Ω
RL
10. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; ZOUT ≤ 50Ω;
tf, tr ≤ 2.5ns.
FIGURE 1. TEST CIRCUIT
tPLZ, tPZL, Open Drain
Closed
tPHZ, tPZH, tPLH, tPHL
Open
3V
1.5V
0V
DATA
INPUT
tH
3V
1.5V
0V
TIMING
INPUT
tREM
ASYNCHRONOUS CONTROL
SWITCH
DEFINITIONS:
CL = Load capacitance, includes jig and probe
capacitance.
RT = Termination resistance, should be equal to ZOUT of
the Pulse Generator.
VIN = 0V to 3V.
Input: tr = tf = 2.5ns (10% to 90%), unless otherwise specified
NOTE:
tSH
TEST
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
SYNCHRONOUS CONTROL
PRESET CLEAR
CLOCK ENABLE
ETC.
tSH
3V
1.5V
0V
tH
FIGURE 2. SETUP, HOLD, AND RELEASE TIMING
ENABLE
HIGH-LOW-HIGH
PULSE
1.5V
FIGURE 3. PULSE WIDTH
DISABLE
3V
3V
SAME PHASE
INPUT TRANSITION
1.5V
CONTROL INPUT
0V
3.5V
OUTPUT
NORMALLY LOW
SWITCH
CLOSED
SWITCH
OPEN
tPHL
3.5V
VOH
1.5V
1.5V
VOL
OUTPUT
0.3V
tPZH
OUTPUT
NORMALLY HIGH
tPLH
tPLZ
tPZL
1.5V
tPHZ
0.3V
VOL
tPLH
tPHL
VOH
3V
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
0V
0V
1.5V
0V
FIGURE 4. ENABLE AND DISABLE TIMING
FIGURE 5. PROPAGATION DELAY
8-72
Test Circuits and Waveforms
(Continued)
VOH
OTHER
OUTPUTS
VOL
VOH
OUTPUT
UNDER
TEST
VOHV
VOLP
VOL
NOTES:
11. VOLP is measured with respect to a ground reference near the output under test. VOHV is measured with respect to VOH.
12. Input pulses have the following characteristics:
PRR ≤ 1MHz, tr = 2.5ns, tf = 2.5ns, skew 1ns.
13. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and
probes require 700MHz bandwidth.
FIGURE 6. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS
8-73
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