Revised January 1999 MM74C89 64-Bit 3-STATE Random Access Read/Write Memory General Description The MM74C89 is a 16-word by 4-bit random access read/ write memory. Inputs to the memory consist of four address lines, four data input lines, a write enable line and a memory enable line. The four binary address inputs are decoded internally to select each of the 16 possible word locations. An internal address register latches the address information on the positive to negative transition of the memory enable input. The four 3-STATE data output lines working in conjunction with the memory enable input provide for easy memory expansion. Read Operation: The complement of the information which was written into the memory is non-destructively read out at the four outputs. This is accomplished by selecting the desired address and bringing memory enable LOW and write enable HIGH. When the device is writing or disabled the output assumes a 3-STATE (Hi-z) condition. Features ■ Wide supply voltage range: ■ Guaranteed noise margin: 3.0V to 15V 1.0V Address Operation: Address inputs must be stable tSA prior to the positive to negative transition of memory enable. It is thus not necessary to hold address information stable for more than tHA after the memory is enabled (positive to negative transition of memory enable). ■ Low power TTL compatibility: Write Operation: Information present at the data inputs is written into the memory at the selected address by bringing write enable and memory enable LOW. ■ 3-STATE output ■ High noise immunity: 0.45 VCC (typ.) fan out of 2 driving 74L ■ Low power consumption: 100 nW/package (typ.) ■ Fast access time: 130 ns (typ.) at VCC = 10V Note: The timing is different than the DM7489 in that a positive to negative transition of the memory enable must occur for the memory to be selected. Ordering Code: Order Number MM74C89N Package Number Package Description N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Truth Table Connection Diagram ME WE Pin Assignments for DIP Operation Condition of Outputs L L Write 3-STATE Complement of Selected Word L H Read H L Inhibit, Storage 3-STATE H H Inhibit, Storage 3-STATE Top View © 1999 Fairchild Semiconductor Corporation DS005888.prf www.fairchildsemi.com MM74C89 64-Bit 3-STATE Random Access Read/Write Memory October 1987 MM74C89 Logic Diagram www.fairchildsemi.com 2 Absolute Maximum VCC −0.3V to VCC +0.3V Voltage at any Pin Operating Temperature Range Storage Temperature Range (TS) (Soldering, 10 seconds) −40°C to +85°C −65°C to +150°C 700 mW Small Outline 500 mW Operating VCC Range 260°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Power Dissipation (PD) Dual-In-Line 18V Lead Temperature (TL) 3.0V to 15V DC Electrical Characteristics Min/Max limits apply across temperature range, unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage VCC = 5.0V 3.5 V VCC = 10V 8.0 V VCC = 5.0V 1.5 V VCC = 10V 2.0 V VCC = 5.0V, IO = −10 µA 4.5 V VCC = 10V, IO = −10 µA 9.0 V VCC = 5.0V, IO = +10 µA 0.5 VCC = 10V, IO = +10 µA 1.0 V 1.0 µA IIN(1) Logical “1” Input Current VCC = 15V, VIN = 15V IIN(0) Logical “0” Input Current VCC = 15V, VIN = 0V IOZ Output Current in High VCC = 15V, V = 15V Impedance State VCC = 15V, VO = 0V Supply Current VCC = 15V ICC −0.005 −1.0 −0.005 0.005 −1.0 µA 1.0 −0.005 0.05 V µA µA 300 µA 0.8 V CMOS/LPTTL INTERFACE VIN(1) Logical “1” Input Voltage VCC = 4.75V VIN(0) Logical “0” Input Voltage VCC = 4.75V VCC − 1.5 VOUT(1) Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA VOUT(0) Logical “0” Output Voltage VCC = 4.75V, IO = +360 µA V 2.4 V 0.4 V OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE ISOURCE ISINK ISINK Output Source Current VCC = 5.0V, VOUT = 0V (P-Channel) TA = 25°C Output Source Current VCC = 10V, VOUT = 0V (P-Channel) TA = 25°C Output Sink Current VCC = 5.0V, VOUT = VCC (N-Channel) TA = 25°C Output Sink Current VCC = 10V, VOUT = VCC (N-Channel) TA = 25°C 3 −1.75 −3.3 mA −8.0 −15 mA 1.75 3.6 mA 8.0 16 mA www.fairchildsemi.com MM74C89 Absolute Maximum Ratings(Note 1) MM74C89 AC Electrical Characteristics (Note 2) TA = 25°C, CL = 50 pF, unless otherwise noted Symbol Typ Max Units Propagation Delay from VCC = 5V 270 500 ns Memory Enable VCC = 10V 100 220 ns Access Time from VCC = 5V 350 650 ns Address Input VCC = 10V 130 280 tSA Address Setup Time VCC = 5V 150 ns VCC = 10V 60 ns tHA Address Hold Time VCC = 5V 60 ns VCC = 10V 40 ns VCC = 5V 400 250 VCC = 10V 150 90 VCC = 5V 0 Time for a Read VCC = 10V 0 Write Enable Setup VCC = 5V Time for a Write VCC = 10V Write Enable Pulse Width VCC = 5V, tWS = 0 300 160 ns VCC = 10V, tWS = 0 100 60 ns VCC = 5V 50 ns VCC = 10V 25 ns tpd tACC tME tSR tWS tWE tHD tSD t1H, t0H Parameter Memory Enable Pulse Width Write Enable Setup Data Input Hold Time Data Input Setup Conditions Min ns ns ns ns ns tME ns tME ns VCC = 5V 50 ns VCC = 10V 25 ns Propagation Delay from a Logical VCC = 5V, CL = 5 pF, RL = 10k 180 300 ns “1” or Logical “0” to the High VCC = 10V, CL = 5 pF, RL = 10k −85 120 ns Propagation Delay from a Logical VCC = 50V, CL = 5 pF, RL = 10k 180 300 ns “1” or Logical “0” to the High VCC = 10V, CL = 5 pF, RL = 10k 85 120 ns Impedance State from Memory Enable t1H, t0H Impedance State from Write Enable CIN Input Capacity Any Input (Note 3) COUT Output Capacity Any Output (Note 3) 6.5 5 pF pF CPD Power Dissipation Capacity (Note 4) 230 pF Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note, AN-90. www.fairchildsemi.com 4 MM74C89 AC Test Circuits t0H t1H Switching Time Waveforms t0H t1H Read Cycle Write Cycle Read Modify Write Cycle tf = 10 ns tr = 60 ns 5 www.fairchildsemi.com MM74C89 64-Bit 3-STATE Random Access Read/Write Memory Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.