MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM DESCRIPTION PIN CONFIGURATION The MH16V645BWJ is 16777216-word x 64-bit dynamic ram module. This consist of sixteen industry standard 16M x 4 dynamic RAMs in SOJ and one industry standard EEPROM in TSSOP. The mounting of SOJs and TSSOP on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module ,suitable for easy interchange or addition of module. 85pin 1pin 94pin 10pin 95pin 11pin 124pin 40pin 125pin 41pin 168pin 84pin FEATURES Type name /RAS /CAS Address /OE access access access access time time time time Cycle Power time dissipation (max.ns) (max.ns) (max.ns) (max.ns) (min.ns) MH16V645BWJ-5 50 13 25 MH16V645BWJ-6 60 15 30 (typ.W) 13 84 4.80 15 104 4.00 Utilizes industry standard 16M x 4 RAMs in SOJ and industry standard EEPROM in TSSOP 168-pin (84-pin dual dual in-line package) Single +3.3V(±0.3V) supply operation Low stand-by power dissipation 28.8mW(Max) . . . . . . . . . . . . . . . . . . . LVCMOS input level Low operation power dissipation MH16V645BWJ -5 . . . . . . . . . . . . . . . . . . 5.76W(Max) MH16V645BWJ -6 . . . . . . . . . . . . . . . . . . 5.19W(Max) All input are directly LVTTL compatible All output are three-state and directly LVTTL compatible Includes(0.22uF x 16) decoupling capacitors 4096 refresh cycle every 64ms Hyper-page mode,Read-modify-write, /CAS before /RAS refresh,Hidden refresh capabilities Gold plating contact pads FRONT SIDE BACK SIDE Row Address A0 ~ A12 Column Address A0 ~ A10 APPLICATION Main memory unit for computers , Microcomputer memory MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 1 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM PIN CONFIGURATION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Name Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 NC NC Vss NC NC Vcc /WE0 /CAS0 /CAS1 /RAS0 /OE0 Vss A0 A2 A4 A6 A8 A10 A12 Vcc Vcc DU Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Vss /OE2 /RAS2 /CAS2 /CAS3 /WE2 Vcc NC NC NC NC Vss DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC DU NC Vss DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss NC NC NC SDA SCL Vcc 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 NC NC Vss NC NC Vcc DU /CAS4 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Vss DU NC /CAS6 /CAS5 NC DU Vss A1 A3 A5 A7 A9 A11 NC Vcc DU DU /CAS7 DU Vcc NC NC NC NC Vss DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC DU NC Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss NC NC SA0 SA1 SA2 Vcc NC: No Connect DU: Don't Use MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 2 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM BLOCK DIAGRAM /RAS0 /RAS2 /WE0 /WE2 /OE0 /OE2 /OE /W /RAS M5M467405BJ /CAS0 D1 /OE /W /RAS M5M467405BJ D2 /OE /W /RAS M5M467405BJ D3 /CAS1 /OE /CAS4 /RAS DQ32 DQ33 DQ34 DQ35 /W /RAS M5M467405BJ DQ36 DQ37 DQ38 DQ39 /W M5M467405BJ D9 DQ4 DQ5 DQ6 DQ7 /OE DQ8 DQ9 DQ10 DQ11 /OE D10 /RAS DQ40 DQ41 DQ42 DQ43 /W /RAS M5M467405BJ DQ44 DQ45 DQ46 DQ47 /W M5M467405BJ D11 /CAS5 DQ12 DQ13 DQ14 DQ15 /OE /W /RAS M5M467405BJ D5 DQ16 DQ17 DQ18 DQ19 /OE /W /RAS M5M467405BJ D13 DQ48 DQ49 DQ50 DQ51 /OE /W /RAS M5M467405BJ M5M4V17405CJ DQ20 DQ21 DQ22 DQ23 /OE /W /RAS M5M467405BJ DQ52 DQ53 DQ54 DQ55 /W /RAS M5M467405BJ D7 DQ24 DQ25 DQ26 DQ27 /OE /W /RAS M5M467405BJ DQ28 DQ29 DQ30 DQ31 /OE /W /RAS M5M467405BJ D4 /OE /CAS2 D1 D6 /OE /CAS3 /OE D8 A0 ~ A12 DQ0 DQ1 DQ2 DQ3 D12 /CAS6 D14 /RAS DQ56 DQ57 DQ58 DQ59 /W /RAS M5M467405BJ DQ60 DQ61 DQ62 DQ63 /W M5M467405BJ D15 /CAS7 /OE D16 D1 ~ D16 SCL Vcc C1. .~.C16 SDA A0 A1 A2 D1 ~ D16 SA0 SA1 SA2 Vss MIT-DS-0240-0.0 EEPROM MITSUBISHI ELECTRIC ( 3 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM FUNCTION The MH16V645BWJ provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., Hyper page mode, /CAS before /RAS refresh, and delayed-write. The input conditions for each are shown in Table 1. Table 1 Input conditions for each mode Operation Read Write (Early write) Write (Delayed write) Read-modify-write Hidden refresh /CAS before /RAS refresh Standby /RAS ACT ACT ACT ACT ACT ACT NAC /CAS ACT ACT ACT ACT ACT ACT DNC Inputs /W /OE NAC ACT ACT DNC ACT DNC ACT ACT DNC ACT NAC DNC DNC DNC Row address APD APD APD APD DNC DNC DNC Column address APD APD APD APD DNC DNC DNC Input/Output Refresh Input Output OPN VLD YES VLD OPN YES VLD IVD YES VLD VLD YES OPN VLD YES DNC OPN YES DNC OPN NO Remark Hyper page mode identical Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 4 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI Parameter Supply voltage Input voltage VO IO Pd Topr Tstg Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect to Vss Ta=25°C Vcc Vss VIH VIL Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage Unit -0.5~ 4.6 -0.5~ 4.6 50 16 0~70 -40~125 V V mA W °C °C V (Ta=0~70°C, unless otherwise noted) (Note 1) RECOMMENDED OPERATING CONDITIONS Symbol Ratings -0.5~ 4.6 Min 3.0 0 2.0 -0.3 Limits Nom Max 3.3 3.6 0 0 Unit Vcc+0.3 V V V 0.8 V Note 1 : All voltage values are with respect to Vss ELECTRICAL CHARACTERISTICS Symbol (Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2) Parameter Test conditions VOH VOL IOZ II I I (CAS) High-level output voltage Low-level output voltage Off-state output current Input current (except /CAS) Input current (/CAS) Average supply ICC1 (AV) current from Vcc operating (Note 3,4,5) IOH=-2.0mA IOL=2.0mA Q floating 0V ≤VOUT≤ Vcc 0V≤VIN≤Vcc+0.3, Other input pins=0V 0V≤VIN≤Vcc+0.3, Other input pins=0V -5 -6 ICC2 Supply current from Vcc , stand-by -5 ICC4(AV) Average supply current from Vcc Hyper-Page-Mode (Note 3,4,5) -6 Average supply current from Vcc /CAS before /RAS refresh (Note 3,5) mode -5 ICC6(AV) -6 Min 2.4 0 -10 -160 -20 Limits Max Typ Vcc 0.4 10 160 20 /RAS, /CAS cycling tRC=tWC=min. output open 1600 Unit V V uA uA uA mA 1440 /RAS=/CAS =VIH, output open 16 8 /RAS=/CAS=WE≥Vcc -0.2, output open /RAS=VIL,/CAS cycling tPC=min. output open 1600 /CAS before /RAS refresh cycling tRC=min. output open 2080 mA mA 1440 mA 1920 Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column address can be changed once or less while /RAS=VIL and /CAS=VIH CAPACITANCE Symbol CI (/CAS) CI C(DQ) C(SCL) C(SDA) C(SA0~3) (Ta = 0~70°C, Vcc = 3.3V±0.3V, Vss = 0V, unless otherwise noted) Parameter Input capacitance, /CAS input Input capacitance, except /CAS input Input/Output capacitance,DATA Input capacitance, SPD clock Input/Output capacitance,SPD DATA Input capacitance, SPD address MIT-DS-0240-0.0 Test conditions VI=Vss f=1MHZ Vi=25mVrms MITSUBISHI ELECTRIC ( 5 / 22 ) Min Limits Typ Max 20 130 15 9 9 7 Unit pF pF pF pF pF pF 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM SWITCHING CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15) Limits Symbol Parameter -5 Min tCAC tRAC tAA tCPA tOEA tOHC tOHR tCLZ tOEZ tWEZ tOFF tREZ Access time from /CAS Access time from /RAS Column address access time Access time from /CAS precharge Access time from /OE Output hold time from /CAS Output hold time from /RAS Output low impedance time /CAS low Output disable time after /OE high Output disable time after /WE high Output disable time after /CAS high Output disable time after /RAS high (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) (Note 13) 5 5 (Note 7) 5 Unit -6 Min Max 13 50 25 28 13 Max 15 60 30 33 15 5 5 5 13 13 13 13 (Note 12) (Note 12) (Note 12,13) (Note 12,13) 15 15 15 15 ns ns ns ns ns ns ns ns ns ns ns ns Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing /CAS before /RAS refresh). Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods (greater than 64 ms) of /RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 1 TTL load and 100pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA). The reference levels for measuring of output signals are 2.0V(VOH)and 0.8V(VOL). 8: Assumes that tRCD ≥ tRCD(max), tASC ≥ tASC(max) and tCP ≥ tCP(max). 9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max). 11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max). 12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT ≤ I ± 10uA I ) and is not reference to VOH(min) or VOL(max). 13: Output is disabled after both /RAS and /CAS go to high. TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles) (Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 14,15) Limits Symbol -5 Parameter Min tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tRDD tCDD tODD tT Refresh cycle time /RAS high pulse width Delay time, /RAS low to /CAS low (Note16) Delay time, /CAS high to /RAS low Delay time, /RAS high to /CAS low /CAS high pulse width Column address delay time from /RAS low (Note17) Row address setup time before /RAS low Column address setup time before /CAS low(Note18) Row address hold time after /RAS low Column address hold time after /CAS low Delay time, data to /CAS low (Note19) Delay time, data to /OE low (Note19) Delay time, /RAS high to data (Note20) Delay time, /CAS high to data (Note20) Delay time, /OE high to data (Note20) Transition time (Note21) -6 Max Min 64 30 14 5 0 8 10 0 0 8 8 0 0 13 13 13 1 37 25 10 50 Unit Max 64 40 14 5 0 10 12 0 0 10 10 0 0 15 15 15 1 45 30 13 50 ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 14: The timing requirements are assumed tT =2ns. 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. . 17: tRAD(max) is specified as a reference point only. If tRAD≥tRAD(max) and tASC≤tASC(max), access time is controlled exclusively by tAA. 18: tASC(max) is specified as a reference point only. If tRCD≥tRCD(max) and tASC≥tASC(max), access time is controlled exclusively by tCAC. 19: Either tDZC or tDZO must be satisfied. 20: Either tRDD or tCDD or tODD must be satisfied. 21: tT is measured between VIH(min) and VIL(max). MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 6 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM Read and Refresh Cycles Limits Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL tORH tOCH Parameter Read cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read Setup time after /CAS high Read hold time after /CAS low Read hold time after /RAS low Column address to /RAS hold time Column address to /CAS hold time /RAS hold time after /OE low /CAS hold time after /OE low -5 (Note 22) (Note 22) Min 84 50 8 35 13 0 0 0 25 13 13 13 -6 Max Min 104 60 10 48 15 0 0 0 30 18 15 15 10000 10000 Unit Max 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns Note 22: Either tRCH or tRRH must be satisfied for a read cycle. Write Cycle (Early Write and Delayed Write) Limits Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH Parameter -5 Write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Write setup time before /CAS low (Note 24) Write hold time after /CAS low /CAS hold time after /W low /RAS hold time after /W low Write pulse width Data setup time before /CAS low or /W low Data hold time after /CAS low or /W low Min 84 50 8 35 13 0 8 8 8 8 0 8 Unit -6 Max 10000 10000 Min 104 60 10 40 15 0 10 10 10 10 0 10 Max 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns Read-Write and Read-Modify-Write Cycles Limits Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tOEH Parameter Read write/read modify write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read setup time before /CAS low Delay time, /CAS low to /W low Delay time, /RAS low to /W low Delay time, address to /W low /OE hold time after /W low -5 (Note23) (Note24) (Note24) (Note24) Min 109 75 38 70 38 0 28 65 40 13 Unit -6 Max 10000 10000 Min 133 89 44 82 44 0 32 77 47 15 Max 10000 10000 ns ns ns ns ns ns ns ns ns ns Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS≥tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD≥tCWD(min), tRWD≥tRWD (min), tAWD≥tAWD(min) and tCPWD ≥tCPWD(min) (for Hyper page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until /CAS or /OE goes back to VIH) is indeterminate. MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 7 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM Hyper Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle, Read Write Mix Cycle,Hi-Z control by /OE or /W) (Note 25) Limits Symbol Parameter tHPC tHPRWC tDOH tRAS tCP tCPRH tCPWD Hyper page mode read/write cycle time tCHOL tOEPE tWPE tHCWD tHAWD tHPWD Hold time to maintain the data Hi-Z until /CAS access tHCOD tHAOD tHPOD Delay time, /CAS low to /OE high after read Delay time, Address to /OE high after read Delay time, /CAS precharge to /OE high after read Hyper page mode read write/read modify write cycle time Output hold time from /CAS low /RAS low pulse width for read write cycle /CAS high pulse width /RAS hold time after /CAS precharge Delay time, /CAS precharge to W low (Note26) (Note27) (Note24) /OE Pulse width (Hi-Z control) /W Pulse width (Hi-Z control) Delay time, /CAS low to /W low after read Delay time, Address to /W low after read Delay time, /CAS precharge to /W low after read Max Min 20 55 5 65 8 28 43 7 7 7 Unit -6 -5 100000 13 Max Min 25 66 5 77 10 33 50 100000 16 ns ns ns ns ns ns ns ns ns ns 28 40 43 7 7 7 32 47 50 13 25 28 15 30 33 ns ns ns ns ns ns Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle. 26: tRAS(min) is specified as two cycles of /CAS input are performed. 27: tCP(max) is specified as a reference point only. If tCP ≥ tCP(max),access time is controlled exclusively by tCAC. /CAS before /RAS Refresh Cycle (Note 28) Limits Symbol tCSR tCHR tRSR tRHR Parameter /CAS setup time before /RAS low /CAS hold time after /RAS low Read setup time before /RAS low Read hold time after /RAS low -5 Min 5 10 10 10 Unit -6 Max Min 5 10 10 10 Max ns ns ns ns Note 28: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh mode. MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 8 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM Timing Diagrams Read Cycle (Note 29) tRC tRAS tRP VIH /RAS VIL tCSH tCRP tRCD tCRP tRSH tCAS VIH /CAS VIL tRAL tCAL tRAD tASR Address VIH VIL tRAH tASC ROW ADDRESS tASR tCAH ROW ADDRESS COLUMN ADDRESS tRRH tRCH tRCS VIH /W VIL tCDD tDZC DQ (INPUTS) tRDD VIH Hi-Z VIL tREZ tCAC tAA tOHR tCLZ DQ (OUTPUTS) tWEZ tOFF tOHC VOH Hi-Z VOL Hi-Z DATA VALID tRAC tDZO tOEA tOCH tOEZ tODD VIH /OE VIL tORH VIN VII VII VII VII Indicates the don't care input. VIH(min) VIN VIH(max) or VIL(min) Note 29 VIL(max) Indicates the invalid output. MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 9 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM Early Write Cycle tWC tRAS /RAS tRP VIH VIL tCSH tCRP tRCD tRSH tCAS tCRP VIH /CAS VIL tASR Address VIH VIL tASR tRAH tCAH tASC tWCS /W ROW ADDRESS COLUMN ADDRESS ROW ADDRESS tWCH VIH VIL tDH tDS DQ (INPUTS) DQ (OUTPUTS) VIH DATA VALID VIL VOH Hi-Z VOL VIH /OE VIL MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 10 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM Delayed Write Cycle tWC tRP tRAS /RAS VIH VIL tCSH tCRP tCRP tRSH tRCD tCAS VIH /CAS VIL tASR VIH Address VIL tRAH tCAH tASC tASR ROW ADDRESS ROW ADDRESS COLUMN ADDRESS tCWL tRWL tWP tRCS /W VIH VIL tWCH tDZC DQ (INPUTS) tDS VIH tDH DATA VALID Hi-Z VIL tCLZ DQ (OUTPUTS) VOH Hi-Z Hi-Z VOL tDZO tOEZ tOEH tODD /OE VIH VIL MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 11 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM Read-Write, Read-Modify-Write Cycle tRWC tRAS tRP VIH /RAS VIL tCRP tCSH tRCD tCRP tRSH tCAS VIH /CAS VIL tRAD tASR VIH Address VIL tRAH tCAH tASC COLUMN ADDRESS ROW ADDRESS ROW ADDRESS tAWD tCWD tRWD tRCS /W tASR tCWL tRWL tWP VIH VIL tDH tDS tDZC DQ (INPUTS) VIH Hi-Z VIL DATA VALID tCAC tAA tCLZ DQ (OUTPUTS) VOH DATA VALID Hi-Z VOL tRAC Hi-Z tODD tDZO tOEA tOEH tOEZ /OE VIH VIL MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 12 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM Hyper Page Mode Read Cycle tRAS tRP VIH /RAS VIL tCSH tCRP tCAS tRCD tCP tHPC tCAS tCP tRSH tCAS tASC tCAH tASC VIH /CAS VIL tRAD tASR VIH Address VIL tRAH ROW ADDRESS tCAH tASC COLUMN-2 COLUMN-1 tCPRH tCAH tASR ROW ADDRESS COLUMN-3 tRCS tRRH tCAL tCAL tCAL tRCH VIH /W VIL tWEZ tDZC DQ (INPUTS) tRDD tCDD VIH Hi-Z tCAC VIL tCAC tAA tCLZ DQ (OUTPUTS) DATA VALID-1 Hi-Z VOL VIL /OE tAA tDOH tDOH VOH tRAC tDZO tCAC tAA tCPA DATA VALID-2 tREZ tOHR tOFF tOHC DATA VALID-3 tCPA tOEA tOCH tOEZ VIH tODD MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 13 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM Hyper Page Mode Early Write Cycle tRAS tRP VIH /RAS VIL tCSH tCRP tCAS tRCD tCP tHPC tCAS tASC tCAH tRSH tCP tCAS tCRP VIH /CAS VIL tCAL tASR VIH Address VIL tRAH ROW ADDRESS tASC tCAH COLUMN-2 COLUMN-1 tWCS tWCH tWCS tWCH tASC tCAL tCAH COLUMN-3 tWCS tASR ROW ADDRESS tWCH VIH /W VIL tDS DQ (INPUTS) DQ (OUTPUTS) VIH VIL tDH tDS tDH DATA VALID-2 DATA VALID-1 tDS tDH DATA VALID-3 VOH Hi-Z VOL VIL /OE MIT-DS-0240-0.0 VIH MITSUBISHI ELECTRIC ( 14 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM Hyper Page Mode Read-Write,Read-Modify-Write Cycle tRAS tRP VIH /RAS VIL tCSH tCRP tRCD tRWL tCRP tHPRWC tCAS tCAS tCP VIH /CAS VIL tRAD tASR VIH Address VIL tRAH tCAH tASC ROW ADDRESS tASC COLUMN-1 tASR ROW ADDRESS COLUMN-2 tAWD tRCS tCWL tCAH tAWD tCWL tCWD tRCS tCWD tWP tWP VIH /W VIL tRWD tDZC DQ (INPUTS) tCPWD tDS VIH tDZC tCLZ tCLZ VOH DATA VALID-1 Hi-Z VOL tODD tOEA tOEZ MIT-DS-0240-0.0 tCPA tDZO VIH /OE DATA VALID-2 Hi-Z tRAC tDZO DATA VALID-2 Hi-Z tCAC tAA tAA DQ (OUTPUTS) tDH tDS DATA VALID-1 Hi-Z tCAC VIL tDH tOEA Hi-Z tODD tOEH tOEZ VIL MITSUBISHI ELECTRIC ( 15 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM Hyper Page Mode Mix Cycle (1) tRP tRAS /RAS tRWL VIH VIL tCRP tCSH tHPC tCRP tCAS tRCD tHPRWC tCAS tCP tCP tCAS VIH /CAS tCWL VIL tRAD tASR VIH Address VIL tRAH ROW ADDRESS tASC tCAH tASC tCAL ROW ADDRESS COLUMN-3 tCPWD tAWD tWCH tWCS tASR tASC tCAH COLUMN-2 COLUMN-1 tRCS /W tCAH tCAL tCWD tWP VIH VIL tDZC DQ (INPUTS) VIH tDZ tDS C DATA VALID-2 tCAC VIL tDH tDS DATA VALID-3 tAA tCAC tAA tWEZ tCLZ DQ (OUTPUTS) VOH DATA VALID-3 VOL tRAC tDZO tCPA tOEA tOEZ VIL /OE tCLZ DATA VALID-1 Hi-Z tDH tDZO tOEA tOEZ tOEH tOCH VIH tODD tODD Note 30: /OE=L; /W Hi-Z control /OE=H; /OE Hi-Z control MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 16 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM Hyper Page Mode Mix Cycle (2) VIH /RAS VIL tHPC VIH /CAS VIL tCP tASC Address tCAS tCAS tCAH tCAH tASC tCAH tASC VIH COLUMN-1 COLUMN-2 COLUMN-3 VIL tCAL tRCH tCAL tWCS tWCH VIH /W tHCWD VIL tHAWD tDH tDS tHPWD DQ (INPUTS) VIH DATA VALID-2 Hi-Z tCAC VIL tDZC tAA tCAC Hi-Z tAA tCPA tWEZ tCPA tCLZ DQ (OUTPUTS) VOH DATA VALID-1 VOL DATA VALID-3 Hi-Z tHCOD tDZC tOEZ tHAOD tOEA tODD VIL /OE tHPOD VIH Note 30: /OE=L; /W Hi-Z control /OE=H; /OE Hi-Z control MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 17 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM Hyper Page Mode Read Cycle ( Hi-Z control by OE ) tRAS tRP VIH /RAS VIL tCSH tCRP tCAS tRCD tCP tHPC tCAS tRSH tCAS tCP tCRP VIH /CAS VIL tRAD tASR Address VIH VIL tRAH tCPRH tASC ROW ADDRESS tASC tCAH COLUMN-1 tCAH tASC COLUMN-2 tASR tCAH ROW ADDRESS COLUMN-3 tRAL tRRH tRCS tRCH VIH /W VIL tWEZ tDZC DQ (INPUTS) tRDD tCDD VIH tCAC tCAC VIL tAA tCLZ DQ (OUTPUTS) VOH DATA VALID-1 Hi-Z VOL tRAC tDZO VIL /OE tAA tCAC tAA tDOH tCLZ DATA VALID-1 DATA VALID-2 tOCH Hi-Z tREZ tOHR tOFF tOHC DATA VALID-3 tCPA tCPA tOEZ tOEA tCHOL tOEZ tOEZ tOEA VIH tOEPE MIT-DS-0240-0.0 Hi-Z MITSUBISHI ELECTRIC ( 18 / 22 ) tOEPE tODD 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM Hyper Page Mode Read Cycle ( Hi-Z control by W ) tRAS /RAS tRP VIH VIL tCSH tCRP tCAS tRCD tHPC tCAS tCP tRSH tCAS tCP tCRP VIH /CAS VIL tRAD tASR VIH Address VIL tRAH ROW ADDRESS tASC tCAH tASC tASC tCAH COLUMN-2 COLUMN-1 tCPRH tCAH tRCH tRCS /W ROW ADDRESS COLUMN-3 tRAL tRCS tASR tRRH tRCH VIH VIL tDZC DQ (INPUTS) tWPE VIH tCAC tCAC VIL tAA tDOH VOH VOL VIL /OE tCAC tAA tWEZ DATA VALID-2 DATA VALID-1 Hi-Z tRAC tDZO Hi-Z tAA tCLZ DQ (OUTPUTS) tRDD tCDD tCPA tOEA tOCH tCLZ Hi-Z tREZ tOHR tOFF tOHC DATA VALID-3 tCPA tOEZ VIH tODD MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 19 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM /CAS before /RAS Refresh Cycle tRC tRP /RAS tRC tRAS tRAS tRP VIH VIL tRPC tCSR /CAS tCHR tRPC tCSR tCHR tRPC tCRP VIH VIL tCPN tASR Address VIH ROW ADDRESS VIL COLUMN ADDRESS tRRH tRCH /W tRCS VIH VIL DQ (INPUTS) DQ (OUTPUTS) VIH VIL tREZ tOHR tOFF tOHC VOH Hi-Z VOL tOEZ VIH /OE VIL MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 20 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM Hidden Refresh Cycle (Read) (Note 31) tRC tRAS /RAS tRC tRP tRAS tRP VIH VIL tCRP tRCD tRSH tCHR VIH /CAS VIL tRAD tASR Address VIH tRAH tASC tASR tCAH COLUMN ADDRESS ROW ADDRESS ROW ADDRESS VIL tRCS /W tRRH tRAL tRCH VIH VIL tCDD tDZC tRDD DQ (INPUTS) VIH Hi-Z VIL tCAC tAA tOFF tOHC tCLZ DQ (OUTPUTS) tREZ tOHR VOH Hi-Z Hi-Z DATA VALID VOL tRAC tDZO tOEA tORH tOEZ tODD VIH /OE VIL Note 31: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. MIT-DS-0240-0.0 MITSUBISHI ELECTRIC ( 21 / 22 ) 28/Jul/`98 MITSUBISHI LSIs Preliminary Spec. Specifications subject to change without notice. MH16V645BWJ -5, -6 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM Unit:mm Package outline 133.35 3.0 8.6MAX 127.35 4.0 3.0 17.78 31.75 17.78 3.0 4.0 2-R2.0 2.0 2-ø3.0 2.0 6.35 1.27 29x1.27=36.83 8.89 1.27 6.35 43x1.27=54.61 9x1.27=11.43 24.495 MIT-DS-0240-0.0 42.18 MITSUBISHI ELECTRIC ( 22 / 22 ) 28/Jul/`98