MITSUBISHI LSIs MH2M365CXJ/CNXJ-5,-6,-7 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM PIN CONFIGURATION (TOP VIEW) [Double side] DESCRIPTION The MH2M365CXJ/CNXJ is 2097152-word x 36-bits dynamic RAM. This consists of four industry standard 1M x 16 dynamic RAMs in SOJ and two industry 1M x 4 dyanmic RAMs in SOJ. The mounting of SOJ on a single in-line package provides any application where high densities and large quantities of memory are required. This is a socket-type memory module,suitable for easy interchange or addition of modules. FEATURES Type name RAS CAS access access time time (max.ns) (max.ns) Address Cycle Power access dissipatime time tion (max.ns) (min.ns) (typ.mW) MH2M365CXJ/CNXJ-5 50 13 25 90 2137 MH2M365CXJ/CNXJ-6 60 15 30 110 1767 MH2M365CXJ/CNXJ-7 70 20 35 130 1537 72pin single in-line package Single 5.0V ± 10% supply Low stand-by power dissipation 33mW (Max) Low operating power dissipation MH2M365CXJ/CNXJ- 5 MH2M365CXJ/CNXJ- 6 MH2M365CXJ/CNXJ- 7 CMOS lnput level 2.69W (Max) 2.22W (Max) 1.92W (Max) 1.Vss 37.MP1 2.DQ0 38.MP3 3.DQ16 39.Vss 4.DQ1 40.CAS0 5.DQ17 41.CAS2 6.DQ2 42.CAS3 7.DQ18 43.CAS1 8.DQ3 44.RAS0 11.NC 45.RAS1 10.Vcc 46.NC 11.NC 47.W 12.A0 48.NC 13.A1 49.DQ8 14.A2 50.DQ24 15.A3 51.DQ9 16.A4 52.DQ25 17.A5 53.DQ10 18.A6 54.DQ26 19.NC 55.DQ11 20.DQ4 56.DQ27 37 38 57.DQ12 39 40 41 58.DQ28 42 43 59.Vcc 44 45 60.DQ29 46 47 61.DQ13 48 49 62.DQ30 50 51 63.DQ14 52 53 54 64.DQ31 55 56 65.DQ15 57 58 66.NC 59 60 67.PD1 61 62 68.PD2 63 64 69.PD3 65 66 70.PD4 67 68 69 71.NC 70 71 72.Vss 72 21.DQ20 22.DQ5 Hyper-page mode , RAS-only refresh , CAS before RAS refresh, Hidden refresh capabilities All inputs and output directly TTL compatible 1024 refresh cycles every 16.4ms (A0 ~ A9) 23.DQ21 24.DQ6 25.DQ22 26.DQ7 27.DQ23 28.A7 29.NC APPLICATION 30.Vcc Main memory unit for computers, Microcomputer memory, Refresh memory for CRT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 31.A8 32.A9 33.RAS3 34.RAS2 35.MP2 36.MP0 Outline 72N9J-C PD1 PD2 PD3 PD4 MIT-DS-0083-1.2 -5 NC NC Vss Vss MITSUBISHI ELECTRIC ( 1 / 15 ) -6 NC NC NC NC -7 NC NC Vss NC NC: NO CONNECTION 21/Feb./1997 MITSUBISHI LSIs MH2M365CXJ/CNXJ-5,-6,-7 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM FUNCTION in addition to normal read, write, a number of other functions, e.g., hyper page mode, RAS only refresh, The input conditions for each are shown in Table 1. Table 1 Input conditions for each mode Inputs Operation Input/Output NAC Row address APD Column address APD ACT ACT APD ACT NAC DNC ACT ACT NAC CAS before RAS refresh ACT ACT Standby NAC DNC RAS CAS W Read ACT ACT Early write ACT RAS-only refresh Hidden refresh Input Output OPN VLD APD VLD OPN APD DNC DNC OPN APD DNC OPN VLD DNC DNC DNC DNC OPN DNC DNC DNC DNC OPN Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid,APD : applied, OPN : open BLOCK DIAGRAM RAS1 45 RAS3 33 LCAS UCAS LCAS 0 M5M418165CJ LDATA DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 MP0 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 MP1 UDATA 1 2 M5M418165CJ M5M44505CJ 0 1 UCAS 3 2 3 LDATA UDATA 2 4 3 5 6 8 20 22 24 26 7 9 21 23 25 27 36 49 51 53 55 57 61 63 65 37 35 50 52 54 56 58 60 62 64 38 LDATA UDATA LDATA 0 M5M418165CJ 1 2 44 40 43 CAS0 CAS1 UDATA M5M418165CJ 3 UCAS RAS0 MIT-DS-0083-1.2 1 DQ19 DQ20 DQ21 DQ22 DQ23 MP2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 MP3 3 M5M44505CJ 0 LCAS 2 DQ16 DQ17 DQ18 LCAS 12 13 14 15 16 17 18 28 31 32 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 MITSUBISHI ELECTRIC ( 2 / 15 ) 34 41 RAS2 CAS2 UCAS 42 CAS3 47 W 21/Feb./1997 MITSUBISHI LSIs MH2M365CXJ/CNXJ-5,-6,-7 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Ratings Unit Vcc Supply voltage VI Input voltage V0 Output voltage -1 ~ 7 V I0 Output current 50 mA Pd Power dissipation Topr Operating temperature Tstg Storage temperature With respect to Vss Ta=25 C RECOMMENDED OPERATING CONDITIONS Symbol V -1 ~ 7 V 6000 mW 0 ~ 70 C -40 ~ 125 C (Ta=0 ~ 70 °C, unless otherwise noted) (Note 1) Limits Parameter -1 ~ 7 Min Nom Max Unit Vcc Supply voltage 4.5 5.0 5.5 V Vss Supply voltage 0 0 0 V VIH High-level input voltage, all inputs 2.4 6.0 V VIL Low-level input voltage, all inputs -1 0.8 V Note 1 : All voltage values are with respect to Vss ELECTRICAL CHARACTERISTICS Symbol (Ta=0 ~ 70°C, Vcc=5.0V ± 10%, Vss=0V, unless otherwise noted) (Note 2) Parameter Test conditions VOH High-level output voltage IOH=-5.0mA VOL Low-level output voltage IOL=4.2mA IOZ Off-state output current II Input current ICC1 (AV) Average supply current from Vcc operating (Note 3,4,5) ICC2 MH2M365C -5 MH2M365C -6 MH2M365C -7 Supply current from Vcc , stand-by (Note 6) ICC3 (AV) ICC4(AV) ICC6(AV) MH2M365C -5 MH2M365C -6 (Note 3,5) MH2M365C -7 Average supply current from Vcc Hyper-Page-Mode (Note 3,4,5) MH2M365C -5 MH2M365C -6 MH2M365C -7 Average supply current from Vcc CAS before RAS refresh mode (Note 3) MH2M365C -5 MH2M365C -6 MH2M365C -7 Average supply current from Vcc refreshing Limits Min Typ Max Unit 2.4 Vcc 0 0.4 V Q floating 0V ≤ VOUT ≤ 5.5V -20 20 µA 0V ≤ VIN ≤ 6 V, Other inputs pins=0V -60 60 µA RAS, CAS cycling tRC=tWC=min. output open V 491 406 mA 351 RAS= CAS =VIH, output open RAS= CAS ≥ Vcc - 0.2 V RAS cycling, CAS= VIH tRC=min. output open RAS=VIL, CAS cycling tPC=min. output open CAS before RAS refresh cycling tRC=min. output open 12 6 mA 491 406 mA 351 461 366 mA 311 471 391 mA 341 Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc3 (AV) and Icc4 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column Address can be changed once or less while RAS=VIL and CAS=VIH . MIT-DS-0083-1.2 MITSUBISHI ELECTRIC ( 3 / 15 ) 21/Feb./1997 MITSUBISHI LSIs MH2M365CXJ/CNXJ-5,-6,-7 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM CAPACITANCE (Ta=0 ~ 70 °C, Vcc=5.0V ± 10%, Vss=0V, unless Symbol otherwise noted) Parameter Limits Test conditions Min Typ Max Unit CI (A) Input capacitance,address inputs 45 pF CI (W) Input capacitance, write control input 57 pF CI (RAS) Input capacitance, RAS input 36 pF CI (CAS) Input capacitance, CAS input 43 pF CI / O Input/Output capacitance, data ports 29 pF SWITCHING CHARACTERISTICS VI=Vss f=1MHZ Vi=25mVrms (Ta=0 ~ 70 °C, Vcc = 5V ± 10%, Vss=0V, unless otherwise noted , see notes 6,14,15) Limits Symbol tCAC tRAC tAA tCPA tOHC tOHR tCLZ tWEZ tOFF tREZ Parameter MH2M365C -5 MH2M365C -6 MH2M365C -7 Min Min Min Max Max Unit Max Access time from CAS (Note 7,8) 13 15 20 ns Access time from RAS (Note 7,9) 50 60 70 ns Column address access time (Note 7,10) 25 30 35 ns Access time from CAS precharge (Note 7,11) 30 35 40 ns Output hold time from CAS 5 5 5 ns (Note 13) Output hold time from RAS Output low impedance time from CAS low (Note 7) (Note 12) Output disable time after WE high 5 5 5 5 5 ns 5 13 15 20 15 15 20 20 Output disable time after CAS high (Note 12,13) 13 Output disable time after RAS high (Note 12,13) 13 ns ns ns ns Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS clock such as RAS-Only refresh). Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods (greater than 16.4 ms) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-5mA) / VOL=0.4V(IOL=-4.2mA) load 100pF. The reference levels for measuring of output signal are 2.0V(VOH) and 0.8V(VOL). 8: Assumes that tRCD ≥ tRCD(max) and tASC ≥ tASC(max) and tCP ≥t CP(max). 9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max). 11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max). 12: tWEZ(max) ,tOFF(max) and tREZ(max)defines the time at which the output achieves the high impedance state ( IOUT ≤ I ± 10 µA I) and is not reference to VOH(min) or VOL(max). 13: Output is disabled after both RAS and CAS go to high. MIT-DS-0083-1.2 MITSUBISHI ELECTRIC ( 4 / 15 ) 21/Feb./1997 MITSUBISHI LSIs MH2M365CXJ/CNXJ-5,-6,-7 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM TIMING REQUIREMENTS (For Read, Write, Refresh, and Hyper-Page Mode Cycles) (Ta=0 ~ 70°C, Vcc = 5V ± 10%, Vss=0V, unless otherwise noted See notes 14,15) Symbol MH2M365C -5 Parameter Min tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tRDD tCDD tT Refresh cycle time Max Limits MH2M365C -6 Min 16.4 30 RAS high pulse width Delay time, RAS low to CAS low 37 MH2M365C -7 Min 16.4 40 18 (Note16) Max 16.4 ms ns 50 ns 50 45 20 Unit Max 20 Delay time, CAS high to RAS low 5 5 5 ns Delay time, RAS high to CAS low 0 0 0 ns CAS high pulse width 8 10 10 Column address delay time from RAS low (Note17) Row address setup time before RAS low Column address setup time before CAS low 25 13 0 (Note18) 30 15 0 10 0 ns 15 35 13 0 ns ns 0 13 0 ns Row address hold time after RAS low 8 10 10 ns Column address hold time after CAS low 8 10 10 ns Delay time, data to CAS low (Note19) 0 0 0 ns Delay time, RAS high to data (Note20) 13 15 20 ns Delay time, CAS high to data (Note20) 13 15 20 Transition time (Note21) 1 50 1 50 ns 1 50 ns Note 14: The timing requirements are assumed tT =3ns. 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. 17: tRAD(max) is specified as a reference point only. If tRAD ≤ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA. 18: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC. 19: tDZC must be satisfied. 20: Either tRDD or tCDD or tODD must be satisfied. 21: tT is measured between VIH(min) and VIL(max). Read and Refresh Cycles Symbol Parameter MH2M365C Min tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL -5 Max Limits MH2M365C Min -6 Max MH2M365C Min -7 Unit Max Read cycle time 90 RAS low pulse width 50 10000 60 10000 70 10000 ns CAS low pulse width 8 10000 10 10000 13 10000 ns 110 ns 130 CAS hold time after RAS low 40 48 55 ns RAS hold time after CAS low 13 15 20 ns 0 0 ns 0 0 ns Read Setup time before CAS low Read hold time after CAS high (Note 22) 0 0 Read hold time after RAS high (Note 22) 10 10 10 ns Column address to RAS hold time 25 30 35 ns Column address to CAS hold time 13 18 23 ns Note 22: Either tRCH or tRRH must be satisfied for a read cycle. MIT-DS-0083-1.2 MITSUBISHI ELECTRIC ( 5 / 15 ) 21/Feb./1997 MITSUBISHI LSIs MH2M365CXJ/CNXJ-5,-6,-7 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM Write Cycle (Early Write) Symbol MH2M365C Parameter Min tWC tRAS tCAS tCSH tRSH tWCS tWCH tWP tDS tDH Limits MH2M365C -5 Max Min -6 MH2M365C Max 130 70 10000 ns 10000 ns 90 RAS low pulse width 50 10000 60 10000 CAS low pulse width 8 10000 10 10000 110 40 48 RAS hold time after CAS low 13 15 Write hold time after CAS low 0 8 Write pulse width Unit Min Write cycle time CAS hold time after RAS low -7 Max 13 55 ns ns ns 0 20 0 10 13 ns 8 10 13 ns Data setup time before CAS low or W low 0 0 0 ns Data hold time after CAS low or W low 8 10 13 ns Write setup time before CAS low Hyper page Mode Cycle (Read, Early Write, Hi-Z control by W) Symbol (Note 25) MH2M365C Parameter Min tHPC tDOH tRAS tCP tCPRH tCHOL tWPE Limits MH2M365C -5 Max Min -6 MH2M365C Max Min Hyper page mode read/write cycle time 20 25 30 Output hold time from CAS low 5 65 5 100000 5 77 100000 92 8 13 10 16 13 RAS low pulse width for read write cycle CAS high pulse width ns (Note24) (Note25) -7 Unit Max ns 100000 16 ns ns ns 30 35 40 ns Hold time to maintain the data Hi-Z until CAS access 7 7 7 ns W Pulse Width (Hi-Z control) 7 7 RAS hold time after CAS precharge 7 Note 23: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle. ns 24: tRAS(min) is specified as two cycles of CAS input are performed. 25: tCP(max) is specified as a reference point only. CAS before RAS Refresh Cycle Symbol (Note 26) Parameter MH2M365C Min tCSR CAS setup time before RAS low tCHR CAS hold time after RAS low -5 Max Limits MH2M365C Min -6 Max MH2M365C Min -7 Unit Max 5 5 5 ns 10 10 15 ns Note 26: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode. MIT-DS-0083-1.2 MITSUBISHI ELECTRIC ( 6 / 15 ) 21/Feb./1997 MITSUBISHI LSIs MH2M365CXJ/CNXJ-5,-6,-7 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM Timing Diagrams Read Cycle (Note 27) tRC tRAS RAS tRP VIH VIL tCSH tCRP tRCD tCRP tRSH tCAS VIH CAS VIL tRAL tCAL tRAD tASR VIH A0~A9 VIL tRAH tASC ROW ADDRESS tASR tCAH ROW ADDRESS COLUMN ADDRESS tRRH tRCH tRCS W VIH VIL tCDD tDZC tRDD VIH Hi-Z DQ(INPUTS) VIL tREZ tCAC tAA tCLZ tOHR tWEZ tOFF tOHC VOH Hi-Z DQ(OUTPUTS) VOL Hi-Z tRAC Note 27 MIT-DS-0083-1.2 DATA VALID Indicates the don't care input. VIH(min) ≤ VIN ≤ VIH(max) or VIL(min) ≤ VIN ≤ VIL(max) Indicates the invalid output. MITSUBISHI ELECTRIC ( 7 / 15 ) 21/Feb./1997 MITSUBISHI LSIs MH2M365CXJ/CNXJ-5,-6,-7 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM Early Write Cycle tWC tRAS RAS tRP VIH VIL tCSH tCRP tRCD tRSH tCAS tCRP VIH CAS VIL tASR VIH A0~A9 VIL tASR tRAH tASC ROW ADDRESS COLUMN ADDRESS ROW ADDRESS tWCS W tCAH tWCH VIH VIL tDS VIH DQ(INPUTS) tDH DATA VALID VIL VOH Hi-Z DQ(OUTPUTS) VOL MIT-DS-0083-1.2 MITSUBISHI ELECTRIC ( 8 / 15 ) 21/Feb./1997 MITSUBISHI LSIs MH2M365CXJ/CNXJ-5,-6,-7 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM Hyper Page Mode Read Cycle tRAS tRP VIH RAS VIL tCSH tCRP tCAS tRCD tRSH tCAS tCP tHPC tCAS tCP tASC tCAH tASC VIH CAS VIL tRAD tASR VIH A0~A9 VIL tRAH tCAH tASC ROW ADDRESS COLUMN-1 COLUMN-2 tCPRH tCAH tASR ROW ADDRESS COLUMN-3 tRCS tRRH tCAL tCAL tCAL tRCH VIH W VIL tWEZ tDZC tRDD tCDD VIH DQ(INPUTS) Hi-Z tCAC VIL tCAC tAA tCLZ VOH DQ(OUTPUTS) VOL tRAC MIT-DS-0083-1.2 tAA tDOH tDOH DATA VALID-1 Hi-Z tCPA MITSUBISHI ELECTRIC ( 9 / 15 ) tCAC tAA DATA VALID-2 tREZ tOHR tOFF tOHC DATA VALID-3 tCPA 21/Feb./1997 MITSUBISHI LSIs MH2M365CXJ/CNXJ-5,-6,-7 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM Hyper Page Mode Early Write Cycle tRAS tRP VIH RAS VIL tCSH tCRP tCAS tRCD tCP tHPC tCAS tASC tCAH tRSH tCP tCAS tCRP VIH CAS VIL tCAL tASR VIH A0~A9 VIL tRAH ROW ADDRESS tASC tCAH COLUMN-1 tWCS tWCH COLUMN-2 tWCS tWCH tASC tCAL tCAH COLUMN-3 tWCS tASR ROW ADDRESS tWCH VIH W VIL tDS VIH DQ(INPUTS) VIL VOH DQ(OUTPUTS) tDH DATA VALID-1 tDS tDH DATA VALID-2 tDS tDH DATA VALID-3 Hi-Z VOL MIT-DS-0083-1.2 MITSUBISHI ELECTRIC (10 / 15 ) 21/Feb./1997 MITSUBISHI LSIs MH2M365CXJ/CNXJ-5,-6,-7 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM Hyper Page Mode Read Cycle ( Hi-Z control by W ) tRAS tRP VIH RAS VIL tCSH tCRP tCAS tRCD tHPC tCAS tCP tRSH tCAS tCP tCRP VIH CAS VIL tRAD tASR VIH A0~A9 VIL tRAH tCAH tASC ROW ADDRESS tASC tCAH tASC COLUMN-2 COLUMN-1 tCPRH tCAH ROW ADDRESS COLUMN-3 tRAL tRCS tASR tRCH tRCS tRRH tRCH VIH W VIL tDZC tWPE tRDD tCDD VIH DQ(INPUTS) tCAC tCAC VIL tAA VOH tDOH VOL tRAC MIT-DS-0083-1.2 tAA tWEZ DATA VALID-2 DATA VALID-1 Hi-Z tCAC tAA tCLZ DQ(OUTPUTS) Hi-Z tCPA MITSUBISHI ELECTRIC (11 / 15 ) tCLZ Hi-Z tREZ tOHR tOFF tOHC DATA VALID-3 tCPA 21/Feb./1997 MITSUBISHI LSIs MH2M365CXJ/CNXJ-5,-6,-7 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM RAS-only Refresh Cycle tRC tRAS tRP VIH RAS VIL tRPC tCRP tCRP VIH CAS VIL tASR VIH A0~A9 VIL tRAH tASR ROW ADDRESS ROW ADDRESS VIH W VIL VIH DQ(INPUT) VIL VOH DQ(OUTPUT) Hi-Z VOL MIT-DS-0083-1.2 MITSUBISHI ELECTRIC (12 / 15 ) 21/Feb./1997 MITSUBISHI LSIs MH2M365CXJ/CNXJ-5,-6,-7 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM CAS before RAS Refresh Cycle tRC tRP tRC tRAS tRAS tRP VIH RAS VIL tRPC tCSR tCHR tRPC tCSR tCHR tRPC tCRP VIH CAS VIL tCPN tASR VIH A0~A9 ROW ADDRESS VIL COLUMN ADDRESS tRRH tRCH tRCS VIH W VIL VIH DQ(INPOUT) VIL VOH tREZ tOHR tOFF tOHC Hi-Z DQ(OUTPUT) VOL MIT-DS-0083-1.2 MITSUBISHI ELECTRIC (13 / 15 ) 21/Feb./1997 MITSUBISHI LSIs MH2M365CXJ/CNXJ-5,-6,-7 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM Hidden Refresh Cycle (Read) (Note 28) tRC tRAS tRC tRP tRAS tRP VIH RAS VIL tCRP tRCD tRSH tCHR VIH CAS VIL tRAD tASR VIH A0~A9 tRAH tASC ROW ADDRESS VIL tASR tCAH COLUMN ADDRESS tRCS ROW ADDRESS tRRH tRAL tRCH VIH W VIL tCDD tDZC tRDD VIH Hi-Z DQ(INOUT) VIL tCAC tAA tREZ tOHR tOFF tOHC tCLZ VOH Hi-Z DQ(OUTPUT) DATA VALID Hi-Z VOL tRAC Note 28: Early write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. MIT-DS-0083-1.2 MITSUBISHI ELECTRIC (14 / 15 ) 21/Feb./1997 MITSUBISHI LSIs MH2M365CXJ/CNXJ-5,-6,-7 HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM 72pin DRAM Module Outline 107.95 8.6MAX 101.19 72 5.96MIN. 1 5.96MIN. 6.35 10.16 20.2 3.38 R1.57 6.35 MIT-DS-0083-1.2 35x1.27=44.45 6.35 35x1.27=44.45 MITSUBISHI ELECTRIC (15 / 15 ) 1.27 1.27 R1.57 2.03 2-ø3.18 21/Feb./1997