Renesas M62342P 8-bit d/a converter (buffered) Datasheet

M62342P/FP, M62343P/FP
8-Bit D/A Converter (Buffered)
REJ03F0073-0300
Rev.3.00
Mar 25, 2008
Description
The M62342 and M62343 are CMOS-structure semiconductor integrated circuits incorporating two or three 8-bit D/A
converter channels with output buffer op-amps.
Serial data transfer type input can easily be used through a combination of three lines: DI, CLK, and LD.
Outputs incorporate buffer op-amps that have a drive capacity of 1 mA or above for both sink and source, and can
operate over the entire voltage range from almost ground to VCC (0 to 5 V), making peripheral elements unnecessary
and enabling configuration of a system with few component parts.
Features
• Data transfer format
10-bit serial data input type
• Output buffer op-amps
Operable over entire voltage range from almost ground to VCC (0 to 5 V)
• High output current capacity
±1 mA or higher
Application
Signal gain setting and automatic adjustment in CTV, and display monitors, conversion from digital data to analog data
in consumer and industrial products
Block Diagram
VCC
LD
CLK
DI
GND
4
8
7
6
5
10-bit shift register
8
Channel
decoder
8-bit latch
8-bit latch
8-bit latch
8-bit upper
segment R-2R
8-bit upper
segment R-2R
8-bit upper
segment R-2R
← M62343 only
+ −
+ −
+ −
1
2
3
AO1
AO2
AO3
(NC in M62342)
REJ03F0073-0300 Rev.3.00 Mar 25, 2008
Page 1 of 8
M62342P/FP, M62343P/FP
Pin Arrangement
M62342P/FP
M62343P/FP
AO1
1
8
LD
AO2
2
7
CLK
AO3*
3
6
DI
VCC
4
5
GND
(Top view)
Outline: PRDP0008AA-A (8P4) [P]
PRSP0008DE-C [FP] (recommend)
PRSP0008DA-A (8P2S-A) [FP] (not recommend for new design)
Note:
Pin 3 of the M62342 is a NC pin.
Pin Description
Pin No.
Symbol
Function
6
7
DI
CLK
8
LD
Load pin. When “H” level is input to LD pin, value in 10-bit shift register is loaded into
decoder and D/A output register.
1
2
3
AO1
AO2
8-bit resolution D/A converter output pins
(After power-on, all channels are reset and DAC data 00h is output.)
AO3
(M62343 only)
VCC
GND
Power supply voltage pin
GND pin
4
5
Serial data input pin. Inputs serial data with a 10-bit data length.
Serial clock input pin. Input signal from DI pin is input to 10-bit shift register at rise of
shift clock.
REJ03F0073-0300 Rev.3.00 Mar 25, 2008
Page 2 of 8
M62342P/FP, M62343P/FP
Absolute Maximum Ratings
Item
Power supply voltage
Input voltage
Output voltage
Internal power consumption
Operating ambient temperature
Storage temperature
Symbol
Rated Value
–0.3 to 7.0
–0.3 to VCC+0.3 ≤ 7.0
–0.3 to VCC+0.3 ≤ 7.0
417 (P) / 272 (FP)
–20 to +85
–40 to +125
VCC
Vin
VO
Pd
Topr
Tstg
Unit
V
V
V
mW
°C
°C
Electrical Characteristics
(Unless specified otherwise, VCC = +5 V ±10%, GND = 0 V, Ta = -20ºC to 85ºC)
Item
Power supply voltage
Power supply current
Symbol
Specification Values
Min
Typ
Max
Unit
VCC
ICC
2.7
0
V
mA
Test Conditions
5.0
5.5
0.7
(M62342)
0.8
(M62343)
2.5
(M62342)
2.7
(M62343)
0
0.5
(M62342)
0.6
(M62343)
1.6
(M62342)
1.8
(M62343)
—
—
—
—
—
—
10
0.2VCC
VCC
VCC−0.1
VCC−0.2
1.0
mA
Upper saturation voltage = 0.3 V
Lower saturation voltage = 0.2 V
VCC = 5.12 V (20 mV/LSB)
No load (IAO = 0)
DI = CLK = LD = GND, IAO = 0 µA
µA
V
V
V
Input leakage current
Input voltage “L”
Input voltage “H”
IILK
VIL
VIH
Buffer amp output
voltage range
VAO
Buffer amp output
drive range
IAO
–10
0
0.5VCC
0.1
0.2
–1.0
Differential
nonlinearity error
Nonlinearity error
Zero point error
Full-scale error
SDL
–1.0
—
1.0
LSB
SL
SZERO
SFULL
—
—
—
—
1.5
2.0
2.0
0.1
LSB
LSB
LSB
µF
5.0
—
Ω
Oscillation limit output
capacitance
CO
–1.5
–2.0
–2.0
—
Buffer amp output
impedance
RO
—
REJ03F0073-0300 Rev.3.00 Mar 25, 2008
Page 3 of 8
At CLK = 1 MHz operation, IAO = 0 µA
D/A data: 6 Ah (at maximum current)
VIN = 0 to VCC
IAO = ±100 µA
IAO = ±500 µA
M62342P/FP, M62343P/FP
AC Characteristics
(Unless specified otherwise, VCC = +5 V ±10%, GND = 0 V, Ta = -20ºC to 85ºC)
Item
Clock “L” pulse width
Clock “H” pulse width
Clock rise time
Clock fall time
Data setup time
Data hold time
Load setup time
Load hold time
Load “H” pulse width
D-A output settling time
Symbol
Specification Values
Min
Typ
Max
tCKL
tCKH
tCR
tCF
tDCH
tCHD
tCHL
tLDC
tLDH
tLDD
200
200
—
—
30
60
200
100
100
—
—
—
—
—
—
—
—
—
—
—
Unit
Test Conditions
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
200
200
—
—
—
—
—
300
Until output reaches last 1/2 LSB
Timing Chart
tCR
tCKH
tCF
CLK
tCKL
tLDC
DI
tDCH
tCHD
tLDH
LD
tCHL
tLDD
D/A
output
REJ03F0073-0300 Rev.3.00 Mar 25, 2008
Page 4 of 8
M62342P/FP, M62343P/FP
Digital Data Format
First
MSB
Last
LSB
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
For channel
address
For D-A output
Channel Select Data
D8
0
1
0
D9
0
0
1
1
1
Channel Selection
AO1 selected
AO2 selected
M62343 : AO3 selected
M62343 Don’t care
Don’t care
DAC Data
D0
0
D1
0
D2
0
D3
0
D4
0
D5
0
D6
0
D7
0
DAC output
VCC/256×1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VCC/256×2
VCC/256×3
VCC/256×4
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VCC/256×255
VCC/256×256
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
Data Timing Chart (Model)
DI
D9
D8
D7
CLK
LD
D/A
output
REJ03F0073-0300 Rev.3.00 Mar 25, 2008
Page 5 of 8
D6
D5
•••
•••
D2
D1
D0
M62342P/FP, M62343P/FP
Usage Notes
1. With this IC, D/A converter upper reference voltage setting is performed by means of the power supply voltage. If
ripples or spikes are imposed on this pin, conversion accuracy may fall. When using this IC, a capacitor must be
inserted between the power supply pin and GND in order to ensure stable D/A conversion.
2. The output buffer amps of this IC are highly tolerant of capacitive loads. Therefore, connecting capacitors (0.1 µF
max.) between the output pins and ground in order to eliminate jitter or noise due to output line wiring presents no
problems whatever in terms of operation.
Sample Standard Application Circuit
1
AO1
2
AO2
3
AO3
(M62343 only)
LD 8
Analog voltage
output pins
CLK 7
DI 6
5V
REJ03F0073-0300 Rev.3.00 Mar 25, 2008
Page 6 of 8
4
+
10 µF
V CC
GND 5
MCU
M62342P/FP, M62343P/FP
Package Dimensions
RENESAS Code
PRDP0008AA-A
5
1
4
MASS[Typ.]
0.5g
c
*1
E
8
Previous Code
8P4
e1
JEITA Package Code
P-DIP8-6.3x8.84-2.54
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
*2
D
e1
D
E
A
A1
A2
bp
b2
b3
c
L
A1
A
A2
Reference Dimension in Millimeters
Symbol
SEATING PLANE
*3 b
3
*3 b
2
bp
e
e
L
JEITA Package Code
P-SOP8-4.4x4.85-1.27
RENESAS Code
PRSP0008DE-C
*1
Previous Code
—
MASS[Typ.]
0.1g
F
D
8
Min Nom Max
7.32 7.62 7.92
8.7 8.9 9.1
6.15 6.3 6.45
4.5
0.51
3.3
0.4 0.5 0.6
0.9 1.0 1.3
1.4 1.5 1.8
0.22 0.27 0.34
15°
0°
2.29 2.54 2.79
3.0
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
5
c
*2
E
HE
bp
Index mark
Terminal cross section
( Ni/Pd/Au plating )
Z
Reference Dimension in Millimeters
Symbol
4
1
e
*3
bp
x
M
A
A2
L1
A1
θ
L
y
Detail F
REJ03F0073-0300 Rev.3.00 Mar 25, 2008
Page 7 of 8
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Min Nom Max
4.65 4.85 5.05
4.2
4.4 4.6
1.85
0.00 0.1 0.20
2.03
0.34 0.4 0.46
0.15 0.20 0.25
0°
8°
5.7 6.2 6.5
1.12 1.27 1.42
0.12
0.10
0.75
0.25 0.45 0.65
0.90
M62342P/FP, M62343P/FP
JEITA Package Code
P-SOP8-4.4x5-1.27
RENESAS Code
PRSP0008DA-A
MASS[Typ.]
0.07g
E
5
*1
HE
8
Previous Code
8P2S-A
F
1
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
4
Index mark
c
A2
*2
A1
D
L
A
Reference
Symbol
*3
e
bp
y
D
E
A2
A1
A
bp
c
Detail F
HE
e
y
L
REJ03F0073-0300 Rev.3.00 Mar 25, 2008
Page 8 of 8
Dimension in Millimeters
Min Nom Max
4.8 5.0 5.2
4.2 4.4 4.6
1.5
0.05
1.9
0.35 0.4 0.5
0.13 0.15 0.2
0°
10°
5.9 6.2 6.5
1.12 1.27 1.42
0.1
0.2 0.4 0.6
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