ON MC10EP33DTR2 3.3v 5vecl / 4 divider Datasheet

MC10EP33, MC100EP33
3.3V / 5VECL 4 Divider
The MC10/100EP33 is an integrated 4 divider. The differential
clock inputs.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power–up, the internal flip–flops will attain a random state; the
reset allows for the synchronization of multiple EP33’s in a system.
The 100 Series contains temperature compensation.
• 320 ps Propagation Delay
• Maximum Frequency > 4 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
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MARKING DIAGRAMS*
8
HEP33
ALYW
1
SO–8
D SUFFIX
CASE 751
1
1
TSSOP–8
DT SUFFIX
CASE 948R
•
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at VEE
• VBB Output
KEP33
ALYW
1
8
8
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = –3.0 V to –5.5 V
Open Input Default State
8
8
8
KP33
ALYW
HP33
ALYW
1
1
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Package
Shipping
MC10EP33D
Device
SO–8
98 Units/Rail
MC10EP33DR2
SO–8
2500 Tape & Reel
MC100EP33D
SO–8
98 Units/Rail
MC100EP33DR2
SO–8
2500 Tape & Reel
MC10EP33DT
TSSOP–8
100 Units/Rail
MC10EP33DTR2
TSSOP–8
2500 Tape & Reel
MC100EP33DT
TSSOP–8
100 Units/Rail
MC100EP33DTR2 TSSOP–8
 Semiconductor Components Industries, LLC, 2002
September, 2002 – Rev. 5
1
2500 Tape & Reel
Publication Order Number:
MC10EP33/D
MC10EP33, MC100EP33
PIN DESCRIPTION
FUNCTION
PIN
RESET
1
8
VCC
R
CLK
2
7
Q
4
CLK
3
6
Q
CLK*, CLK*
ECL Clock Inputs
Reset*
ECL Asynchronous Reset
VBB
Reference Voltage Output
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
TRUTH TABLE
VBB
4
5
VEE
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
CLK
CLK
RESET
Q
Q
X
Z
X
Z
Z
L
L
F
H
F
Z = LOW to HIGH Transition
Z = HIGH to LOW Transition
F = Divide by 4 Function
CLK
tRR
RESET
Q
Figure 2. Timing Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
NA
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 4 kV
> 200 V
> 2 kV
Level 1
UL–94 V–0 @ 0.125 in
91 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC10EP33, MC100EP33
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
–6
V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
–6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
–40 to +85
°C
Tstg
Storage Temperature Range
–65 to +150
°C
JA
Thermal Resistance (Junction–to–Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JC
Thermal Resistance (Junction–to–Case)
std bd
8 SOIC
41 to 44
°C/W
JA
Thermal Resistance (Junction–to–Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
JC
Thermal Resistance (Junction–to–Case)
std bd
8 TSSOP
41 to 44
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
VI VCC
VI VEE
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
18
26
34
18
26
34
18
26
34
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single–Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single–Ended)
1365
1690
1430
1755
1490
1815
mV
VBB
Output Voltage Reference
1790
1990
1855
2055
1915
2115
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
1890
2.0
150
0.5
1955
150
0.5
0.5
2015
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V.
4. All loading with 50 to VCC–2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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3
MC10EP33, MC100EP33
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
–40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
18
26
34
18
26
34
18
26
34
mA
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single–Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single–Ended)
3065
3390
3130
3455
3190
3515
mV
VBB
Output Voltage Reference
3490
3690
3555
3755
3615
3815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
Symbol
Characteristic
IEE
Power Supply Current
VOH
3590
2.0
3655
150
3715
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V.
7. All loading with 50 to VCC–2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = –5.5 V to –3.0 V (Note 9)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
18
26
34
18
26
34
18
26
34
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 10)
–1135
–1010
–885
–1070
–945
–820
–1010
–885
–760
mV
VOL
Output LOW Voltage (Note 10)
–1935
–1810
–1685
–1870
–1745
–1620
–1810
–1685
–1560
mV
VIH
Input HIGH Voltage (Single–Ended)
–1210
–885
–1145
–820
–1085
–760
mV
VIL
Input LOW Voltage (Single–Ended)
–1935
–1610
–1870
–1545
–1810
–1485
mV
VBB
Output Voltage Reference
–1510
–1310
–1445
–1245
–1385
–1185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
–1410
VEE+2.0
0.0
VEE+2.0
150
0.5
–1345
0.0
VEE+2.0
150
0.5
–1285
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC–2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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4
MC10EP33, MC100EP33
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
–40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
28
33
24
30
36
25
31
37
mA
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single–Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single–Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
Symbol
Characteristic
IEE
Power Supply Current
VOH
1875
2.0
1875
150
0.5
1875
150
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V.
13. All loading with 50 to VCC–2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
28
33
24
30
36
25
31
37
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single–Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single–Ended)
3055
3375
3055
3375
3055
3375
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
3575
2.0
150
0.5
3575
150
0.5
0.5
3575
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V.
16. All loading with 50 to VCC–2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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5
MC10EP33, MC100EP33
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = –5.5 V to –3.0 V (Note 18)
–40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
23
28
33
24
30
36
25
31
37
mA
Output HIGH Voltage (Note 19)
–1145
–1020
–895
–1145
–1020
–895
–1145
–1020
–895
mV
VOL
Output LOW Voltage (Note 19)
–1945
–1820
–1695
–1945
–1820
–1695
–1945
–1820
–1695
mV
VIH
Input HIGH Voltage (Single–Ended)
–1225
–880
–1225
–880
–1225
–880
mV
VIL
Input LOW Voltage (Single–Ended)
–1945
–1625
–1945
–1625
–1945
–1625
mV
VBB
Output Voltage Reference
–1525
–1325
–1525
–1325
–1525
–1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
0.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
Symbol
Characteristic
IEE
Power Supply Current
VOH
–1425
VEE+2.0
0.0
–1425
VEE+2.0
0.0
150
0.5
–1425
VEE+2.0
150
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 to VCC–2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = –3.0 V to –5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
–40°C
Symbol
VOPP
Min
Characteristic
Output Voltage Amplitude
(See Figure 3)
fin < 4.0 GHz
fin < 4.5 GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
CLK/Q
RESET/Q
tRR
Set/Rest Recovery
tPW
Minimum Pulse width
tJITTER
Cycle–to–Cycle Jitter
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Times
(20% – 80%)
RESET
Q, Q
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
mV
700
600
300
370
380
420
150
700
600
440
470
300
370
380
420
100
200
550
480
0.2
<1
150
800
90
170
700
600
440
470
320
400
400
450
100
200
100
ps
550
480
550
480
ps
0.2
<1
0.2
<1
ps
1200
150
800
1200
150
800
1200
mV
200
100
180
250
120
200
280
ps
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC–2.0 V.
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6
460
500
ps
MC10EP33, MC100EP33
900
VOPP, OUTPUT VOLTAGE (mV)
800
700
600
500
400
300
200
100
0
0
500
1000 1500
2000 2500
3000 3500
4000 4500
5000
fin, INPUT FREQUENCY (MHz)
Figure 3. Input Frequency (fin) versus Output Voltage (VOPP)
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC – 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 – Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
–
ECLinPS Circuit Performance at Non–Standard VIH Levels
AN1405
–
ECL Clock Distribution Techniques
AN1406
–
Designing with PECL (ECL at +5.0 V)
AN1504
–
Metastability and the ECLinPS Family
AN1568
–
Interfacing Between LVDS and ECL
AN1650
–
Using Wire–OR Ties in ECLinPS Designs
AN1672
–
The ECL Translator Guide
AND8001
–
Odd Number Counters Design
AND8002
–
Marking and Date Codes
AND8009
–
ECLinPS Plus Spice I/O Model Kit
AND8020
–
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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7
MC10EP33, MC100EP33
PACKAGE DIMENSIONS
SO–8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–07
ISSUE AA
–X–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDAARD IS 751-07
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
–Y–
G
C
N
X 45 SEATING
PLANE
–Z–
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
S
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8
J
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
8
0.010
0.020
0.228
0.244
MC10EP33, MC100EP33
PACKAGE DIMENSIONS
TSSOP–8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R–02
ISSUE A
8x
0.15 (0.006) T U
K REF
0.10 (0.004)
S
2X
L/2
8
1
PIN 1
IDENT
S
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
5
0.25 (0.010)
B
–U–
L
0.15 (0.006) T U
M
M
4
A
–V–
F
DETAIL E
C
0.10 (0.004)
–T– SEATING
PLANE
D
–W–
G
DETAIL E
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9
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0
6
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0
6
MC10EP33, MC100EP33
Notes
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10
MC10EP33, MC100EP33
Notes
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11
MC10EP33, MC100EP33
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: [email protected]
JAPAN: ON Semiconductor, Japan Customer Focus Center
2–9–1 Kamimeguro, Meguro–ku, Tokyo, Japan 153–0051
Phone: 81–3–5773–3850
Email: [email protected]
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
http://onsemi.com
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