ON LV8104V Three-phase brushless motor predriver Datasheet

Ordering number : ENA1677
LV8104V
Bi-CMOS IC
For Variable Speed Control
http://onsemi.com
Three-Phase Brushless Motor Predriver
Overview
The LV8104V is a pre-driver IC designed for variable speed control of 3-phase brushless motors. It can be used to
implement both upper and low output N-channel power FET drive circuit using a built-in charge pump circuit.
High-efficiency drive is possible through the use of direct PWM drive and synchronous rectifyication.
Functions
• VCC max = VG max = 42V
• Three-phase bipolar direct PWM drive
• Built-in charge pump for the upper side gate drive voltage generation
• Speed discriminator and PLL speed control system
• High efficiency drive by synchronous rectification
• 5V regulator output
• Start/Stop switching circuit(power save state in a stop mode)
• Forward/reverse switching circuit
• Braking circuit (short braking)
• Built-in FG amplifier and integrating amplifier
• Built-in VCO circuit
• Speed lock detection output
• Current limiter
• Constaint protection circuit
• Clock disconnection protection circuit
• Thermal shutdown protection circuit
• Low-voltage protection circuit
Semiconductor Components Industries, LLC, 2013
May, 2013
31710 SY 20100219-S00001 No.A1677-1/19
LV8104V
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
VCC max
Charge pump output voltage
VG max
VCC = VG
VG pin
Output current
IO max1
Pins UL, VL, WL
-15 to 15
mA
IO max2
Pins UH, VH, WH, UOUT, VOUT and WOUT
-15 to 15
mA
Pd max1
Independent IC
0.65
W
Pd max2
Mounted on the specified board *
1.70
W
Allowable power dissipation
42
V
42
V
Operating temperature
Topr
-20 to +80
°C
Storage temperature
Tstg
-55 to +150
°C
* Specified board:114.3mm × 76.1mm × 1.6mm, glass epoxy board.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating range at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage range
VCC
16 to 28
V
5V constant voltage output current
IREG
0 to -10
mA
LD pin applied voltage
VLD
ILD
0 to 6
V
0 to 5
mA
VFGS
IFGS
0 to 6
V
0 to 5
mA
LD pin output current
FGS pin applied voltage
FGS pin output current
Electrical Characteristics at Ta = 25°C, VCC = 24V
Parameter
Symbol
Supply current 1
ICC1
Supply current 2
ICC2
Conditions
Ratings
min
typ
Unit
max
6.5
8.2
mA
3
3.8
mA
5.6
6.0
V
10
50
mV
10
50
mV
VREG-0.48
VREG-0.35
VREG-0.22
V
0.19
0.30
0.41
V
VG-0.65
VG-0.5
VG-0.35
V
0.45
0.6
0.8
V
16
20
24
kHz
1.79
2.24
2.69
MHz
VCC+7.9
VCC+9.0
VCC+10.0
V
VCC-1.45
0.5
VCC-1.1
VCC-0.8
0.8
V
0.65
112
140
168
-2
-0.1
At stop
5V Constant-voltage Output (VREG pin)
Output voltage
VREG
Line regulation
ΔV (REG1)
Load regulation
ΔV (REG2)
IO = 5mA
VCC = 16 to 28V
IO = -5 to -10mA
5.2
Output block / Conditions : apply a VG voltage of 33V
High level output voltage 1
VOH1
Pins UL, VL and WL
Low level output voltage 1
VOL1
VOH2
Pins UL, VL and WL
High level output voltage 2
Low level output voltage 2
PWM frequency
VOL2
f (PWM)
Pins UH, VH and WH
Pins UH, VH and WH
IOH = -2mA
IOL = 2mA
IOH = -2mA
IOL = 2mA
Internal Oscillator
Oscillation frequency
f (REF)
Charge Pump Output (VG pin)
Output voltage
VGOUT
CP1 pin
High level output voltage
VOH (CP1)
ICP1 = -2mA
Low level output voltage
VOL (CP1)
f (CP1)
ICP1 = 2mA
Charge pump frequency
V
kHz
Hall Amplifier
Input bias current
Common-mode input voltage range 1
IB (HA)
VICM1
When using Hall elements
Common-mode input voltage range 2
VICM2
At one-side input bias (Hall IC application)
Hall input sensitivity
SIN wave
Input voltage Low → High
ΔVIN (HA)
VSLH
Input voltage High → Low
VSHL
Hysteresis width
μA
0.3
3.5
V
0
VREG
V
50
mVp-p
5
13
24
mV
2
7
12
mV
-12
-6
-2
mV
Continued on next page.
No.A1677-2/19
LV8104V
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
FG Amplifier
Input offset voltage
VIO (FG)
Input bias current
IB (FG)
Reference voltage
VB (FG)
High level output voltage
VOH (FG)
Low level output voltage
VOL (FG)
-10
mV
1
μA
-5%
VREG/2
5%
V
IFGI = -0.1mA, No load
3.95
4.4
4.85
V
IFGI = 0.1mA, No load
0.75
1.2
1.65
-1
FG input sensitivity
GAIN : 100 times
Schmitt width of the next stage
One-side hysteresis comparator
3
fFG = 2kHz
V
mV
120
200
45
48
Operation frequency range
Open-loop gain
10
280
mV
3
kHz
dB
FGS output
Output saturation voltage
VOL (FGS)
IFGS = 2mA
Output leakage current
IL (FGS)
VO = 6V
0.2
0.4
V
10
μA
3.9
V
CSD oscillator
High level output voltage
VOH (CSD)
Low level output voltage
VOL (CSD)
Amplitude
V (CSD)
External capacitor charge current
ICHG1
External capacitor discharge current
ICHG2
Oscillation frequency
f (CSD)
2.9
3.4
1.6
2.0
2.4
V
1.15
1.4
1.65
Vp-p
-13
-10
-7
μA
7.5
10.5
13.5
μA
C = 0.047μF
78
Hz
Speed Discriminator output
High level output voltage
VOH (D)
VREG-1.25
VREG-1.0
VREG-0.75
V
Low level output voltage
VOL (D)
0.65
0.9
1.15
V
Counts
512
LD output
Output saturation voltage
VOL (LD)
ILD = 2mA
Output leakage current
IL (LD)
VO = 6V
Lock range
0.2
-6.25
0.4
V
10
μA
+6.25
%
Speed control PLL output
High level output voltage
VOH (P)
VREG-2.0
VREG-1.7
VREG-1.4
V
Low level output voltage
VOL (P)
1.3
1.6
1.9
V
GDF
0.20
0.25
0.32
VRF
0.225
0.25
0.27
Current control circuit
Drive gain
Current limiter operation
Limiter voltage
V
Integrator
Input offset voltage
VIO (INT)
Input bias current
IB (INT)
Reference voltage
VB (INT)
High level output voltage
VOH (INT)
Low level output voltage
VOL (INT)
Open-loop gain
-10
-1
10
mV
1
μA
-5%
VREG/2
5%
V
IINTI = -0.1mA, No load
3.95
4.4
4.85
V
IINTI = 0.1mA, No load
0.75
1.2
1.65
45
48
fINT = 2kHz
V
dB
VCO Oscillator (C pin)
Oscillation frequency range
f (C)
C = 120pF, R = 24kΩ
0.15
1.54
MHz
High level output voltage
VOH (C)
FIL = 2.5V
2.71
3.16
3.61
V
Low level output voltage
VOL (C)
FIL = 2.5V
2.20
2.60
3.00
V
Amplitude
V (C)
FIL = 2.5V
0.44
0.56
0.68
Vp-p
FIL pin
Output source current
IOH (FIL)
-15
-11
-6
μA
Output sink current
IOL (FIL)
6
10
15
μA
Continued on next page.
No.A1677-3/19
LV8104V
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
Low-voltage protection circuit
Operation voltage
VLVSD
10.0
10.7
11.4
V
Hysteresis width
ΔVLVSD
0.72
0.97
1.22
V
150
175
°C
30
°C
Thermal shutdown operation
Thermal shutdown operation
TSD
Design target value*
ΔTSD
Design target value*
temperature
Hysteresis width
CLK pin
Input frequency
fI (CLK)
High level input voltage range
VIH (CLK)
2.0
VREG
3
kHz
V
Low level input voltage range
VIL (CLK)
0
1.0
V
Input open voltage
VIO (CLK)
VREG-0.5
VREG
V
Hysteresis width
VIS (CLK)
Design target value*
0.18
0.27
0.36
V
High level input current
IIH (CLK)
VCLK = 5V
-22
-10
-3
μA
Low level input current
IIL (CLK)
VCLK = 0V
-133
-93
-70
μA
Pull-up resistance
RU (CLK)
45
60
75
kΩ
VIH (S/S)
2.0
VREG
V
V
S/S pin
High level input voltage range
Low level input voltage range
VIL (S/S)
0
1.0
Input open voltage
VIO (S/S)
VREG-0.5
VREG
V
Hysteresis width
VIS (S/S)
0.18
0.27
0.36
V
μA
High level input current
IIH (S/S)
VS/S = 5V
-22
-10
-3
Low level input current
IIL (S/S)
VS/S = 0V
-133
-93
-70
μA
Pull-up resistance
RU (S/S)
45
60
75
kΩ
High level input voltage range
VIH (F/R)
2.0
VREG
V
Low level input voltage range
VIL (F/R)
0
1.0
V
Input open voltage
VIO (F/R)
VREG-0.5
VREG
V
F/R pin
Hysteresis width
VIS (F/R)
0.18
0.27
0.36
V
High level input current
IIH (F/R)
VF/R = 5V
-22
-10
-3
μA
Low level input current
IIL (F/R)
VF/R = 0V
-133
-93
-70
μA
Pull-up resistance
RU (F/R)
45
60
75
kΩ
VIH (BR)
2.0
VREG
V
V
BR pin
High level input voltage range
Low level input voltage range
VIL (BR)
0
1.0
Input open voltage
VIO (BR)
VREG-0.5
VREG
V
Hysteresis width
VIS (BR)
0.18
0.27
0.36
V
μA
High level input current
IIH (BR)
VBR = 5V
-22
-10
-3
Low level input current
IIL (BR)
VBR = 0V
-133
-93
-70
μA
Pull-up resistance
RU (BR)
45
60
75
kΩ
Note : * These items are design target values and are not tested.
No.A1677-4/19
LV8104V
Package Dimensions
unit : mm (typ)
3277
15.0
0.5
5.6
7.6
23
44
1
0.65
0.2
0.1
(1.5)
1.7max
(0.68)
22
0.22
SANYO : SSOP44(275mil)
Pd max - Ta
Allowable power dissipation, Pd max - W
2.0
1.7
Specified board : 114.3 × 76.1 × 1.6mm3
glass epoxy
Mounted on a board
1.5
1.0
0.95
0.65
Independent IC
0.5
0.36
0
—20
0
20
40
60
80
100
Ambient temperature, Ta - C
IN3+
IN3-
IN2+
IN2IN1+
35 34
RFGND
36
UL
37
RF
VH
38
33 32 31
30
29
28
27
26
25
24
23
21
22
UH
WL
39
UOUT
WOUT
40
VL
WH
41
VOUT
NC
42
NC
VG
44 43
VCC
CP2
CP1
Pin Assignment
12
13 14 15
16
17
18 19 20
POUT
S/S
BR
FGS
LD
FGIN+
IN1-
11
FGOUT
FGIN-
10
F/R
9
CLK
8
DOUT
C
7
INTREF
GND1
6
INTIN
GND2
5
CSD
4
INTOUT
3
R
2
FIL
1
VREG
LV8104
No.A1677-5/19
LV8104V
Three-phase logic truth table (A high level input is the state where IN+ > IN-.)
F/R = “L”
F/R = “H”
IN1
Drive output
IN1
IN2
IN3
IN2
IN3
Upper gate
Lower gate
1
H
L
H
L
H
L
VH
UL
2
H
L
L
L
H
H
WH
UL
3
H
H
L
L
L
H
WH
VL
4
L
H
L
H
L
H
UH
VL
5
L
H
H
H
L
L
UH
WL
6
L
L
H
H
H
L
VH
WL
S/S Input
BR Input
Input
Mode
Input
Mode
High or Open
Stop
High or Open
Brake
Low
Start
Low
Release
Current Control Characteristics
0.3
RF – INTOUT (typical characteristics)
0.25
GAIN = 0.25
RF – V
0.2
0.1
0
1.5
2.0
2.2
2.5
3.0
3.2
3.5
4.0
INTOUT – V
No.A1677-6/19
±5%
120pF
CLK
FIL
C
R
FGIN+
FGIN-
FGOUT
150pF
LD
FGS
VREG
VREG
CLK
VCO
VCO
PLL
1/512
+
SPEED
DISCRI
SPEED
PLL
VREG
+
FGS
LD
FG
FIL
DOUT
POUT DOUT
POUT
INT
REF
VREG
INT
IN
BR F/R
BR
F/R
CONTROL
AMP
RST
CSD
CSD
OSC
+
INT
OUT
RF
CURR
COMP
LATCH
S/S RFGND
S/S
DRIVE
LOGIC
HALL
FIL
INT
OSC
1/112
1/16
WH
WOUT
WL
VH
VOUT
VL
UH
UOUT
UL
VG
CP2
CP1
VREG
VCC
GND1
PRE
DRIVER
CHARGE
PUMP
VREG
GND2
LVSD
HALL
HYS COMP
4700pF
4700pF
4700pF
IN1+ IN1- IN2+ IN2- IN3+ IN3-
680pF
680pF
680pF
680pF
680pF
680pF
+
FW217 × 3
24V
LV8104V
Block Diagram
(Referance constants)
No.A1677-7/19
LV8104V
Relations Hall input with Drive output
(1) When F/R = ”L”
IN1
IN2
IN3
UH
VH
WH
UL
VL
WL
PWM control output
Synchronous rectification output
(2) When F/R = ”H”
IN1
IN2
IN3
UH
VH
WH
UL
VL
WL
PWM control output
Synchronous rectification output
No.A1677-8/19
LV8104V
(3) When F/R = ”L” and the inverting phase input as against Hall input(2).
IN1
IN2
IN3
UH
VH
WH
UL
VL
WL
PWM control output
Synchronous rectification output
(4) When F/R=”H” and the inverting phase input as against Hall input(1).
IN1
IN2
IN3
UH
VH
WH
UL
VL
WL
PWM control output
Synchronous rectification output
No.A1677-9/19
LV8104V
Pin Functions
Pin No.
Pin name
1
VREG
Pin function
Equivalent circuit
5V constant voltage output pin(5.6V).
VCC
Connect a capacitor between this pin and GND.
1
2
GND2
GND pins.
3
GND1
GND1 and GND2 are connected in the IC.
4
C
VCO oscillation pin.
VREG
Connect a capacitor between this pin and GND.
4
5
R
Pin to set the charge / discharge current of the VCO
VREG
circuit.
Connect a resistor between this pin and GND.
5
6
FIL
VCO PLL output filter pin.
VREG
6
Continued on next page.
No.A1677-10/19
LV8104V
Continued from preceding page.
Pin No.
Pin name
7
CSD
Pin function
Equivalent circuit
Pin to set the operating time of the constraint
Reset circuit
VREG
protection.
Connect a capacitor between this pin and GND.
This pin combines also functions as the logic circuit
block initial reset pin.
7
8
INTOUT
Integrating amplifier output pin.
VREG
8
9
INTIN
10
INTREF
Integrating amplifier inverting input pin.
VREG
INTOUT
Integrating amplifier non-inverting input pin.
1/2 VREG potential.
Connect a capacitor between this pin and GND.
10
11
DOUT
Speed discriminator output pin.
Acceleration → high, deceleration → low.
9
VREG
11
12
POUT
Speed control PLL output pin.
Outputs the phase comparison result for CLK and
VREG
FG.
12
Continued on next page.
No.A1677-11/19
LV8104V
Continued from preceding page.
Pin No.
Pin name
13
S/S
Pin function
Start / Stop control pin.
Low : 0V to 1.0V
Equivalent circuit
VREG
High : 2.0V to VREG
Goes high when left open.
Low for start.
The hysteresis width is about 0.27V.
14
CLK
External clock signal input pin.
Low : 0V to 1.0V
13
VREG
High : 2.0V to VREG
Goes high when left open.
The hysteresis width is about 0.27V.
f = 3kHz, maximum.
14
15
F/R
Forward / reverse control pin.
Low : 0V to 1.0V
VREG
High : 2.0V to VREG
Goes high when left open.
Low for forward.
The hysteresis width is about 0.27V.
15
16
BR
Brake pin(short braking operation).
Low : 0V to 1.0V
VREG
High : 2.0V to VREG
Goes high when left open.
High or open for brake mode operation.
The hysteresis width is about 0.27V.
16
17
FGS
FG amplifier Schmitt output pin.
This is an open collector output.
VREG
17
Continued on next page.
No.A1677-12/19
LV8104V
Continued from preceding page.
Pin No.
Pin name
18
LD
Pin function
Equivalent circuit
Speed lock detection output pin.
VREG
This is an open collector output.
Goes low when the motor speed is within the speed
lock range(±6.25%)
19
FGOUT
18
FG amplifier output pin.
VREG
This pin is connected to the FG Schmitt comparator
circuit internally in the IC.
19
FG Schmitt comparator
20
FGIN-
FG amplifier inverting input pin.
VREG
21
FGIN+
FGOUT
FG amplifier non-inverting input pin.
1/2 VREG potential.
21
20
Connect a capacitor between this pin and GND.
IN1IN1+
IN2-
Hall input pins.
26
IN2+
IN3-
If noise on the Hall signals is a problem, insert
capacitors between the corresponding IN+ and IN-
27
IN3+
inputs.
22
23
24
25
The input is seen as a high level input when IN+ >
IN-, and as a low level input for the opposite state.
VREG
22 24 26
28
RFGND
Output current detection reference pin.
Connect to GND side of the current detection
23 25 27
VREG
resistor Rf.
28
Continued on next page.
No.A1677-13/19
LV8104V
Continued from preceding page.
Pin No.
Pin name
29
RF
Pin function
Output current detection pin.
Connect to the current detection resistor Rf.
Equivalent circuit
VREG
Sets the the maximum output current IOUT to be
0.25/Rf.
29
30
UL
Output pins for gate drive of the lower side N
33
VL
channel power FET.
36
WL
VREG
30 33 36
32
UH
Output pins for gate drive of the upper side N
35
VH
channel power FET.
38
WH
VG
32 35 38
31
UOUT
Pins to detect the source voltage of the upper side N
34
VOUT
channel power FET.
37
WOUT
31 34 37
40
VCC
Power supply pin.
Connect a capacitor between this pin and GND for
stabilization.
42
VG
Charge pump output pin.
Connect a capacitor between this pin and VCC.
43
CP2
VCC
Pin to connect the capacitor for charge pump.
Connect a capacitor between this pin and CP1.
42
43
Continued on next page.
No.A1677-14/19
LV8104V
Continued from preceding page.
Pin No.
Pin name
44
CP1
Pin function
Pin to connect the capacitor for charge pump.
Connect a capacitor between this pin and CP2.
Equivalent circuit
VCC
44
39
NC
No connection pins.
41
No.A1677-15/19
LV8104V
Description of LV8104V
1. Speed control circuit
This IC controls the speed with a combination of the speed discriminator circuit and the PLL circuit. Therefore, when a
motor that has large load variation is used, it is possible to prevent the rotation variation as compared with the speed
control method only the speed discriminator. The speed discriminator circuit and the PLL circuit outputs an error signal
once every one FG period. The FG servo frequency signal (fFG) is controlled to have the equal frequency with the
clock signal (fCLK) which is input through the CLK pin.
fFG = fCLK
2. VCO circuit
This IC has the VCO circuit to generate the reference signal of the speed discriminator circuit. The reference signal
frequency is calculated as follows.
fVCO = fCLK × 512
fVCO : Reference signal frequency, fCLK : Clock signal frequency
The components connected to the R, C and FIL pins must be connected to the GND1 pin (pin 3) with a line that is as
short as possible to reduce influence of noise.
3. Output drive circuit
This IC can be used to implement both upper and lower output N channel power FET drive circuit using a built-in
charge pump circuit. The upper side gate voltage is VCC+9V. The lower side gate voltage is VREG(5.6V).
The PWM switching is performed on the UL, VL and WL pins. Therefore, it is performed on the lower output N
channel power FET. The driving force of the motor is adjusted by changing the duty that the lower output N channel
power FET is on. The PWM frequency is determined with 20kHz (typical) in the IC.
When the PWM switching of the lower output N channel power FET is off, the upper output N channel power FET is
turned on (Synchronous rectification). Therefore, it is possible to reduce the temperature increase of the upper output N
channel power FET.The off-time of the synchronous rectification is determined in the IC and varies from 1.7μs to
3.7μs.
4. Speed lock range
The speed lock range is less than ±6.25% of the fixes speed. When the motor speed is in the lock range, the LD pin (an
open collector output) goes low. If the motor speed goes out of the lock range, the PWM output on-duty is adjusted
according to the speed error to control the motor speed to be within the lock range.
5. Hall input signal
The input amplitude of 100mVp-p or more (differential) is desirable in the Hall sensor inputs. The closer the input
wave-form is to a square wave, the required input amplitude is lower. Inversely, the closer the input waveform is to a
triangular wave, the higher input amplitude is required. Also, note that the input DC voltage must be set to be within the
common-mode input voltage range.
If a Hall sensor IC is used to provide the Hall inputs, those signals can be input to one side (either the + or - side) of the
Hall sensor signal inputs as 0 to VREG level signals if the other side is held fixed at a voltage within the common-mode
input voltage range that applies when the Hall sensors are used.
If noise on the Hall inputs is a problem, that noise must be excluded by inserting capacitors across the inputs. Those
capacitors must be located as close as possible to the input pins. When the Hall inputs for all three phases are in the
same state, all the outputs will be in the off state.
6. Current limiter circuit
The current limiter circuit limits the (peak) current at the value I = VRF/Rf (VRF = 0.25V (typical), Rf : current
detection resistor). The current limitation operation consists of reducing the PWM output on-duty to suppress the
current.
High accuracy detection can be achieved by connecting the RF and RFGND pins lines near at the ends of the current
detection resistor (Rf).
7. S/S switching circuit
When the S/S pin is set to the low level, S/S switching circuit is the start mode. Inversely, when the S/S pin is set to the
high level or open, S/S switching circuit is the stop mode. This IC will be in the power save state of decreasing the
supply current at the stop mode. The bias current to most of the circuit in the IC is cut off in the power save state. The
operating circuit in the power save state are limited to the S/S switching circuit , the 5V constant voltage output, FG
amplifier and FG amplifier Schmitt output. The other circuit do not operate. The upper side output transistors for all
phases (the UH, VH and WH side) and the lower side output transistors for all phases (the UL, VL and WL side) are
turned off in the power save state.
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8. Braking circuit
When the BR pin is set to the high level or open, the brake is on. Inversely, when the BR pin is set to the low level, the
brake is released. The brake becomes a short brake that turns on the upper side output transistors for all phases (the UH,
VH and WH side) and turns off the lower side output transistors for all phases (the UL, VL and WL side). Note that the
current limiter does not operate during braking. The current that flows in the output transistors during braking is
determined by the motor back EMF voltage and the coil resistance. Applications must be designed so that this current
does not exceed the ratings of the output transistors used. (The higher the motor speed at which braking is applied, the
more severe this problem becomes).
The BR pin can be switching at the start mode. (This IC is designed to avoid through currents at changeover.) This
means that motor startup and stop control can be performed using the BR pin with the S/S pin held at the low level (the
start mode). If the startup time becomes excessive, it can be reduced by controlling the motor startup and stop with the
BR pin rather than with the S/S pin (Since the IC will be in the power save state at the stop mode, enough time for the
VCO circuit to stabilize will be required at the beginning of the motor start operation).
9. Forward/Reverse switching circuit
The motor rotation direction can be switched by using the F/R pin. However, the following notes must be observed if
the F/R pin is switched while the motor is rotating.
• This IC is designed to avoid through currents at changeover. However, the rise in the motor supply voltage (due to
instantaneous return of the motor current to the power supply) during direction switching may cause problems. If this
rise is a problem, the value of the capacitor inserted between power and ground must be increased.
• If the motor current after direction switching exceeds the current limit value, the PWM drive side outputs will be
turned off, but the opposite side output will be in the short-circuit braking state, and a current determined by the motor
back EMF voltage and the coil resistance will flow. Applications must be designed so that this current does not exceed
the ratings of the output transistors used. (The higher the motor speed at which the direction is switched, the more
severe this problem becomes.)
10. Constraint protection circuit
This IC includes the constraint protection circuit to protect the motor and the output transistors in the motor constrained
state. If the LD output remains high (indicating the unlocked state) for a fixed period in the motor drive state (the S/S
pin : start, the BR pin : brake release), the lower side output transistors (the UL, VL and WL side) are turned off. This
time can be set by adjusting the oscillation frequency of the CSD pin by using a external capacitor. By the value (C) of
the capacitor attached to the CSD pin, the set time is calculated as follows.
The set time (sec) = 60.8 × C (μF)
When a 0.047μF capacitor is connected with the CSD pin, the set time becomes about 2.9sec.
By the variance of the IC, “60.8” of the above formula has varied from 40.8 to 80.8.
To restart a motor by cancelling the constraint protection function, any of the following operation is necessary.
• Put the S/S pin into the start state again after the stop mode (about 1ms or more).
• Put the BR pin into the brake release state again after the braking state (about 1ms or more).
• Turn on the power supply again after the turn off state.
When the clock disconnect protection function, the thermal shutdown function and the low-voltage protection function
are operating, the constraint protection function does not operate even if the motor does not rotate.
The oscillation waveform of the CSD pin is used as the reference signal for some circuits in addition to the motor
constraint protection circuit. Therefore, it is desirable to oscillate the CSD pin even if the constraint protection function
is unnecessary. If the constraint protection circuit is not used, the oscillation of the CSD pin must be stopped by
connecting a 220kΩ resistor and a 0.01μF capacitor in parallel between the CSD pin and GND. However, in that case,
the clock disconnection protection circuit does not operate too. And, the synchronous rectification does not operate in
any of the following cases.
• When the motor does not rotate in the motor constrained state since the motor is started up by the S/S or the BR
input, the PWM switching is performed by using the current limiter circuit. But, the synchronous rectification does
not operate when the oscillation of the CSD pin is stopped.
The CSD pin combines also functions as the initial reset pin. The time that the CSD pin voltage is charged to about
1.25V is determined as the initial reset. At the initial reset, all the outputs will be in the off state.
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11. Clock disconnection protection circuit
If the clock input through the CLK pin goes to the no input state in the motor drive state (the S/S pin : start, the BR pin :
brake release), the lower side output transistors (the UL, VL and WL side) are turned off. If the clock is resupplied, the
clock disconnection protection function is cancelled. When the clock period is longer than about thirty-fourth part of
the constraint protection set time, the clock disconnection protection circuit judges the clock input to be the no input
state and this protection function will operate.
12. Thermal shutdown circuit
If the junction temperature rises to the specified temperature (TSD) in the motor drive state (the S/S pin : start, the BR
pin : brake release), the lower side output transistors (the UL, VL and WL side) are turned off. If the junction
temperature falls to more than the hysteresis width (ΔTSD), the thermal shutdown function is cancelled.
13. Low-voltage protection circuit
The IC includes a low-voltage protection circuit to protect against incorrect operation when the VCC power is applied
or if the power supply voltage falls below its operating level. When the VCC voltage falls under the specified voltage
(VLVSD), all the outputs will be in the off state. If the VCC voltage rises to more than the hysteresis width (ΔVLVSD),
the low-voltage protection function is cancelled.
14. Power supply stabilization
Since this IC is used in applications that flow the large output current, the power supply line is subject to fluctuations.
Therefore, capacitors with capacitance adequate to stabilize the power supply voltage must be connected between the
VCC pin and GND. If diodes are inserted in the power supply line to prevent the IC destruction due to reverse power
supply connection, since this makes the power supply voltage even more subject to fluctuations, even larger
capacitance will be required.
15. Ground lines
The signal system GND and the output system GND must be separated, and connected to one GND at the connector. As
the large current flows to the output system GND, this GND line must be made as short as possible.
Output system GND : GND for Rf and VCC line capacitors
Signal system GND : GND for the IC and external components
16. Integrating amplifier
The integrating amplifier integrates the speed error pulses and phase error pulses and converts them to the speed
command voltage. At that time it also sets the control loop gain and the frequency characteristics. External components
of the integrating amplifier must be placed as close to the IC as possible to reduce influence of noise.
17. FG amplifier
The FG amplifier normally makes up a filter amplifier to reject noise. Since a clamp circuit has been added at the FG
amplifier output, the output amplitude is clamped at about 3.2Vp-p, even if the amplifier gain is increased.
After the FG amplifier, the Schmitt comparator on one side hysteresis(200mV (typical)) is inserted. The Schmitt
comparator output (FGS output) becomes high level when the FG amplifier output is lower than the FGIN+ voltage,
and becomes low level when the FG amplifier output is higher to more than Schmitt width as compared with the FGIN+
voltage. Therefore, it is desirable that the amplifier gain be set so that the output amplitude is over 1.0Vp-p at the lowest
controlled speed to be used.
The capacitor connected between the FGIN+ pin and GND is required for bias voltage stabilization. This capacitor
must be connected to the GND1 pin (pin 3) with a line that is as short as possible to reduce influence of noise.
As the FG amplifier and the FGS output are operating even if the S/S pin is the stop state, it is possible to monitor the
motor rotation by the FGS output.
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PS No.A1677-19/19
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