TI CD74FCT543 Bicmos fct interface logic, octal register/transceiver, three-state Datasheet

CD74FCT543
Data sheet acquired from Harris Semiconductor
SCHS258
January 1997
Features
D
ENDE
M
M
O
S
EC
IGN
NOT R NEW DES ology
FOR OS Techn
BiCMOS FCT Interface Logic,
Octal Register/Transceiver, Three-State
M
Use C
-
• Buffered Inputs
• Typical Propagation Delay: 6.4ns at VCC = 5V,
TA = 25oC, CL = 50pF
• Noninverting
• Family Features
- SCR Latchup Resistant BiCMOS Process and
Circuit Design
Speed of Bipolar FAST™/AS/S
64mA Output Sink Current
Output Voltage Swing Limited to 3.7V at VCC = 5V
Controlled Output Edge Rates
Input/Output Isolation to VCC
BiCMOS Technology with Low Quiescent Power
Ordering Information
PART NUMBER
TEMP.
RANGE (oC)
PKG.
NO.
PACKAGE
CD74FCT543EN
0 to 70
24 Ld PDIP
E24.3
CD74FCT543M
0 to 70
24 Ld SOIC
M24.3
CD74FCT543SM
0 to 70
24 Ld SSOP
M24.209
NOTE: When ordering the suffix M and SM packages, use the entire
part number. Add the suffix 96 to obtain the variant in the tape and reel.
Pinout
CD74FCT543
(PDIP, SOIC, SSOP)
TOP VIEW
LEBA 1
24 VCC
OEBA 2
23 CEBA
A0 3
22 B0
A1 4
21 B1
A2 5
20 B2
A3 6
19 B3
A4 7
18 B4
A5 8
17 B5
A6 9
16 B6
A7 10
15 B7
CEAB 11
14 LEAB
GND 12
13 OEAB
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1997
8-1
File Number
2399.2
CD74FCT543
Functional Diagram
D
DETAIL A
Q
B0
LE
D
LE
Q
A0
B1
A1
DETAIL A x 7
B7
A7
OEBA
OEAB
CEBA
CEAB
LEBA
LEAB
TRUTH TABLE For A to B (Symmetric with B to A)
LATCH STATUS
OUTPUT BUFFERS
CEAB
INPUTS
LEAB
OEAB
A TO B
B0 THRU B7
H
X
X
Storing
High Z
X
H
−
Storing
-
X
-
H
-
High Z
L
L
L
Transparent
Current A Inputs
L
H
L
Storing
Previous A Inputs (Note 1)
NOTE:
1. Before LEAB LOW to HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A to B data flow shown; B to A flow control is the same, except using CEBA, LEBA, and OEBA.
IEC Logic Symbol
CD74FCT543
11
14
13
23
1
2
3
4
5
6
7
8
9
10
≥1
EN1
≥1
EN2
1
8-2
2
22
21
20
19
18
17
16
15
CD74FCT543
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK (For VI < -0.5V) . . . . . . . . . . . . . -20mA
DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA
DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . . 70mA
DC Output Source Current per Output Pin, IO . . . . . . . . . . . . -30mA
DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140mA
DC Ground Current (IGND). . . . . . . . . . . . . . . . . . . . . . . . . . . 528mA
Thermal Resistance (Typical, Note 2)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC and SSOP-Lead Tips Only)
Operating Conditions
Operating Temperature Range (TA) . . . . . . . . . . . . . . . .0oC to 70oC
Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V
DC Input Voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC
DC Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ VCC
Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Commercial Temperature Range 0oC to 70oC, VCC Max = 5.25V, VCC Min = 4.75V
AMBIENT TEMPERATURE (TA)
25oC
TEST CONDITIONS
PARAMETER
SYMBOL
VI (V)
IO (mA)
0oC TO 70oC
VCC (V)
MIN
MAX
MIN
MAX
UNITS
High Level Input Voltage
VIH
4.75 to
5.25
2
-
2
-
V
Low Level Input Voltage
VIL
4.75 to
5.25
-
0.8
-
0.8
V
High Level Output Voltage
VOH
VIH or VIL
-15
Min
2.4
-
2.4
-
V
Low Level Output Voltage
VOL
VIH or VIL
64
Min
-
0.55
-
0.55
V
High Level Input Current
IIH
VCC
Max
-
0.1
-
1
µA
Low Level Input Current
IIL
GND
Max
-
-0.1
-
-1
µA
IOZH
VCC
Max
-
0.5
-
10
µA
IOZL
GND
Max
-
-0.5
-
-10
µA
Input Clamp Voltage
VIK
VCC or
GND
Min
-
-1.2
-
-1.2
V
Short Circuit Output Current
(Note 3)
IOS
VO = 0
VCC or
GND
Max
-60
-
-60
-
mA
Quiescent Supply Current,
MSI
ICC
VCC or
GND
Max
-
8
-
80
µA
∆ICC
3.4V
(Note 4)
Max
-
1.6
-
1.6
mA
Three-State Leakage Current
Additional Quiescent Supply
Current per Input Pin
TTL Inputs High, 1 Unit Load
-18
0
NOTES:
3. Not more than one output should be shorted at one time. Test duration should not exceed 100ms.
4. Inputs that are not measured are at VCC or GND.
5. FCT Input Loading: All inputs are 1 unit load. Unit load is ∆ICC limit specified in Electrical Specifications table, e.g., 1.6mA Max. at 70oC.
8-3
CD74FCT543
Switching Specifications Over Operating Range FCT Series tr, tf = 2.5ns, CL = 50pF, RL (Figure 4)
25oC
0oC TO 70oC
SYMBOL
VCC (V)
TYP
MIN
TYP
MAX
UNITS
An ↔ Bn
tPLH, tPHL
5
6.4
2.5
-
8.5
ns
LEBA to An or LEAB to Bn
tPLH, tPHL
5
9.4
2.5
-
12.5
ns
CEBA or CEAB to An or Bn
tPLZ, tPHZ
5
6.8
2
-
9
ns
tPZL, tPZH
5
9
2
-
12
ns
CPD
(Note 6)
-
49
-
49
-
pF
Minimum (Valley) VOHV During Switching of
Other Outputs (Output Under Test Not Switching)
VOHV
5
0.5
-
-
-
V
Maximum (Peak) VOLP During Switching of
Other Outputs (Output Under Test Not Switching)
VOLP
5
1
-
-
-
V
CI
-
-
-
-
10
pF
CI/O
-
-
-
-
15
pF
PARAMETER
Propagation Delays
Power Dissipation Capacitance
Input Capacitance
Input/Output Capacitance
NOTE:
6. CPD, measured per flip-flop, is used to determine the dynamic power consumption.
PD (per package) = VCC ICC + Σ(VCC2 fI CPD + VO2 fO CL + VCC ∆ICC D) where:
VCC = supply voltage
∆ICC = flow through current x unit load
CL = output load capacitance
D = duty cycle of input high
fO = output frequency
fI = input frequency
Prerequisite for Switching
25oC
PARAMETER
0oC TO 70oC
SYMBOL
VCC (V)
TYP
MIN
MAX
UNITS
tSU
5
(Note 7)
-
3
-
ns
Data to Latch Enable Hold Time
tH
5
-
2
-
ns
Latch Enable Pulse Width
tW
5
-
9
-
ns
Data to Latch Enable Setup Time
NOTE:
7. 5V: Minimum is at 4.75V for 0oC to 70oC, Typical is at 5V.
8-4
CD74FCT543
Test Circuits and Waveforms
VCC
tr, tf = 2.5ns
(NOTE 8)
VI
3V
0
PULSE ZO
GEN
SWITCH POSITION
7V
500Ω
RL
V0
DUT
CL
50pF
RT
RT = ZO
500Ω
RL
8. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; ZOUT ≤ 50Ω;
tf, tr ≤ 2.5ns.
FIGURE 1. TEST CIRCUIT
tPLZ, tPZL, Open Drain
Closed
tPHZ, tPZH, tPLH, tPHL
Open
3V
1.5V
0V
DATA
INPUT
tH
3V
1.5V
0V
TIMING
INPUT
tREM
ASYNCHRONOUS CONTROL
SWITCH
DEFINITIONS:
CL = Load capacitance, includes jig and probe
capacitance.
RT = Termination resistance, should be equal to ZOUT of
the Pulse Generator.
VIN = 0V to 3V.
Input: tr = tf = 2.5ns (10% to 90%), unless otherwise specified
NOTE:
tSH
TEST
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
SYNCHRONOUS CONTROL
PRESET CLEAR
CLOCK ENABLE
ETC.
tSH
3V
1.5V
0V
tH
HIGH-LOW-HIGH
PULSE
FIGURE 2. SETUP, HOLD, AND RELEASE TIMING
ENABLE
1.5V
FIGURE 3. PULSE WIDTH
DISABLE
3V
3V
SAME PHASE
INPUT TRANSITION
1.5V
CONTROL INPUT
1.5V
0V
3.5V
OUTPUT
NORMALLY LOW
SWITCH
CLOSED
SWITCH
OPEN
tPHL
3.5V
VOH
1.5V
1.5V
VOL
OUTPUT
0.3V
tPZH
OUTPUT
NORMALLY HIGH
tPLH
tPLZ
tPZL
tPHZ
0.3V
VOL
tPLH
tPHL
VOH
3V
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
0V
0V
1.5V
0V
FIGURE 4. ENABLE AND DISABLE TIMING
FIGURE 5. PROPAGATION DELAY
VOH
OTHER
OUTPUTS
VOL
VOH
OUTPUT
UNDER
TEST
VOHV
VOLP
VOL
NOTES:
9. VOLP is measured with respect to a ground reference near the output under test. VOHV is measured with respect to VOH.
10. Input pulses have the following characteristics:
PRR ≤ 1MHz, tr = 2.5ns, tf = 2.5ns, skew 1ns.
11. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and
probes require 700MHz bandwidth.
FIGURE 6. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS
8-5
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