Rohm BA7630S Video switch for canal-plus decoder Datasheet

Multimedia ICs
Video switch for CANAL-Plus decoder
BA7630S / BA7630F
The BA7630S and BA7630F are decoder switching ICs for the scrambled broadcasts in France. The ICs include a 3input multiplexer, 2-input multiplexers with 6dB amplifiers, and a 9-bit serial-to-parallel converter.
These ICs greatly simplify decoder switching, and can be connected to a control microprocessor using just two lines.
Applications
•Video
cassette recorders
•1)Features
All the switching functions required for SECAM
3) Inputs have a sync-tip clamp.
4) The switch section can be used independently.
5) Low power consumption off a 5V supply.
CANAL plus decoder integrated onto one chip.
2) Built-in 9-bit serial-to-parallel converter for decoder
and TV control reduces number of microprocessor
wiring connections required.
•Absolute maximum ratings (Ta = 25°C)
Parameter
Power supply voltage
Power dissipation
Symbol
Limits
VCC
Pd
Unit
9∗1
BA7630S
BA7630F
V
500∗2
600∗3
mW
Operating temperature
Topr
– 25 ~ + 70
°C
Storage temperature
Tstg
– 55 ~ + 125
°C
∗1 13V for switches 1 to 9.
∗2 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C.
∗3 Reduced by 6.0mW for each increase in Ta of 1°C over 25°C.
•Recommended operating conditions (Ta = 25°C)
Parameter
Power supply voltage
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
V
1
Multimedia ICs
BA7630S / BA7630F
•Block diagram
22
21
20
19
18
17
16
15
14
13
12
BA7630S
BUFF
BUFF
SW4
CONTROL
LOGIC
LATCHES
6dB
AMP
SW3
SW12
SW12
SHIFT
REGISTER
SW2
LOGIC
6dB
AMP
BIAS
SW1
1
28
27
2
26
3
25
4
24
5
6
23
7
22
SW2
8
21
20
SW3
BIAS
SW4
SW1
10
11
9
19
18
17
16
15
BA7630F
BUFF
BUFF
SW4
CONTROL
LOGIC
LATCHES
SW3
6dB
AMP
SW12
SW12
SHIFT
REGISTER
SW2
LOGIC
6dB
AMP
BIAS
SW1
1
2
3
4
5
6
7
8
9
•Pin descriptions
Pin No.
Pin name
Pin name
IN 4
12 (15)
OUT 2
2
VCC
13 (16)
GND
3
IN 1
14 (17)
SW 4 IN / OUT
4
(5)
RESET IN
15 (20)
SW 5 OUT
5
(6)
IN 2
16 (21)
SW 6 OUT
6
(7)
GND
17 (22)
SW 7 OUT
7
(8)
IN 3
18 (23)
SW 8 OUT
8
(9)
SW 1 IN / OUT
19 (24)
CLOCK IN
9
(10)
SW 2 IN / OUT
20 (26)
DATA IN
10 (13)
SW 3 IN / OUT
21 (27)
SW 9 OUT
11 (14)
OUT 3
22 (28)
OUT 1
Pin numbers in parentheses are for the BA7630F.
2
Pin No.
1
10
11
12
SW3
BUFF
SW4
SW2
SW1
13
14
Multimedia ICs
BA7630S / BA7630F
•Electrical characteristics (unless otherwise noted Ta = 25°C and V
CC
= 5.0V)
Symbol
Min.
Typ.
Max.
Unit
Conditions
Measurement
Circuit
ICC
—
28
40
mA
—
Fig.1
Vom
2.5
2.8
—
VP-P
f = 1kHz, THD = 0.5%
Voltage gain 1
GV1
– 0.5
0
0.5
dB
f = 1MHz, VIN = 1.0VP-P
Voltage gain 2
GV2
5.5
6.0
6.5
dB
f = 1MHz, VIN = 1.0VP-P
Frequency characteristic
Gf
– 4.0
– 1.5
+ 1.0
dB
10MHz / 1MHz
VIN = 1.0VP-P
CTM
—
– 60
– 45
dB
f = 4.43MHz
VIN = 1.0P-P
VTH1 ~ 4
1.0
2.0
3.0
V
—
"H" input voltage
VIH
3.0
—
—
V
—
"L" input voltage
VIL
—
—
1.0
V
—
Parameter
Supply current
〈Analog〉
Maximum output level
Interchannel crosstalk
SW1 ~ SW4 switch level
Fig.1
〈Digital〉
"H" input current
IIH
—
10
µA
—
"L" input current
I IL
– 80
– 100
– 150
µA
—
230
350
µA
VCC = 12V
"H" output leakage current 1
IQH1 ~ 4
150
"H" output leakage current 2
2
IQH5 ~ 9
—
0
50
µA
VCC = 12V
"L" output voltage
VQL
—
0.1
0.5
V
ICC = 2mA
Maximum clock frequency
fMax.
250
500
—
kHz
—
Setup time
t su
—
0.1
1.0
µs
—
Fig.3
Fig.2
Fig.1
3
Multimedia ICs
BA7630S / BA7630F
Measurement circuits
•BA7630S
Distortion
meter
V
~
1
Distortion
meter
~V
1
2
2
SWK
22
SWJ
21
20
19
18
17
16
15
14
13
12
BUFF
SW4
BUFF
CONTROL
LOGIC
SW12
LATCHES
6dB
AMP
SW3
SW12
SHIFT
REGISTER
SW2
LOGIC
BIAS
SW1
6dB
AMP
SW2
8
9
BUFF
SW4
SW1
SW3
VCC5.0V
1
2
3
4
5
6
7
10
11
A
47µ
1µ
1µ +
1µ +
+
SWB
SWA
1
SWC
1
2
1µ +
SWD
1
2
SWE
2
1
1
2
SWF
2
1
SWH
SWG
2
2
1
SWI
2
1
1
2
~
50Ω
~
50Ω
~
50Ω
~
50Ω
OSC
~V
3V
Fig.1
4
1V
Distortion
meter
Multimedia ICs
BA7630S / BA7630F
BA7630S
Output
Measurement Circuit
VCC = 5.0V
Input
Measurement Circuit
47µ
Input Measurement Circuit
+
5.0V
1
BIAS
BUFF
2
22
21
SW12
A1
Input
Measurement Circuit
A
3
20
SHIFT
REGISTER
SW1
CONTROL
LOGIC
4
A2
19
V
5
Output
Measurement Circuit
18
Output Measurement Circuit
SW1SW2
SW0
A
A3
12V
6
17
SW12
LOGIC
7
Output
Measurement Circuit
16
LATCHES
SW1
V
V1
8
15
SW4
SW2
9
Output
Measurement Circuit
14
SW4
10
SW3
13
SW3
Output
Measurement Circuit
Output
Measurement Circuit
11
BUFF
6dB
AMP
6dB
AMP
BUFF
Output
Measurement Circuit
12
Output
Measurement Circuit
Fig.2
5
Multimedia ICs
BA7630S / BA7630F
BA7630S
VCC = 5.0V
12V
47µ
+
1
BUFF
BIAS
22
PG
CL
RL
SW9
21
2
SW12
PG
3
50Ω
20
SHIFT
REGISTER
CONTROL
LOGIC
4
19
5
18
CL
50Ω
RL
SW8
SW1SW2
RL
CL
SW12
RL
LOGIC
7
CL
RL
SW1
RL
CL
CL
SW4
SW2
9
RL
14
SW2
RL
SW4
CL
10
SW3
BUFF
6dB
AMP
6dB
AMP
Fig.3
6
13
SW3
SW3
11
SW5
15
8
RL
SW6
16
LATCHES
CL
SW1
SW7
17
6
12V
50Ω
CL
BUFF
12
SW4
PG
Multimedia ICs
BA7630S / BA7630F
•Measurement conditions
SWA
SWB
SWC
SWD
SWE
SWF
SWG
SWH
SW I
SWJ
SWK
Measurement
method
I CC
2
2
2
2
2
2
2
2
×
×
×
—
Vom1-1
Vom2-1
Vom3-1
2
2
2
1
2
2
2
1
2
2
2
1
1
1
2
1
2
2
2
1
2
2
2
2
1
×
×
×
×
×
×
×
×
Vom1-2
Vom3-2
×
×
×
×
×
2
2
2
Vom2-3
Vom4-3
2
1
2
2
1
2
2
2
1
2
2
2
Voltage gain 1
Gv11-2
Gv13-2
Gv12-3
Gv14-3
2
2
2
1
1
2
2
2
2
2
1
2
2
1
2
2
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Voltage gain 2
Gv21-1
Gv22-1
Gv23-1
2
2
2
1
2
2
2
1
2
2
2
1
1
1
2
Gf1-1
Gf2-1
Gf3-1
2
2
2
1
2
2
2
1
2
2
2
1
1
1
2
Gf1-2
Gf3-2
2
2
1
2
2
2
2
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Gf2-3
G f4-3
2
1
2
2
1
2
1
2
2
2
CTM1-1-2
CTM1-1-3
CTM2-1-1
CTM2-1-3
CTM3-1-1
CTM3-1-2
2
2
2
2
2
2
2
2
1
2
1
2
CTM1-2-3
CTM3-2-1
2
2
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
CTM2-3-4
CTM4-3-2
1
2
1
2
1
1
Switch setting
Parameter
Current
dissipation
Maximum
output level
Frequency
characteristics
Interchannel
crosstalk
Symbol
×
×
×
×
×
×
×
×
×
1
2
×
1
2
2
2
×
×
×
×
×
×
×
×
×
1
2
2
2
2
1
2
1
2
1
2
2
1
1
1
1
2
2
1
1
2
2
2
2
2
1
2
2
1
2
2
2
2
1
2
2
×
×
×
×
×
×
×
×
2
2
×
×
1
2
×
×
×
×
×
×
×
×
2
2
×
×
×
×
×
×
×
×
1
2
×
×
1
2
2
2
2
2
×
×
1
2
×
×
×
×
×
×
×
×
2
2
×
×
×
×
×
×
×
×
1
1
×
×
×
×
×
×
×
×
×
×
Note 1
Note 2
1
1
1
2
2
2
×
×
×
×
1
1
1
1
1
1
Note 3
Note 4
×
×
×
×
The measurements in the above table were made with switching voltage levels for SW1 to SW4 of "L" = 1V, and "H" = 3V.
Note 1: Connect distortion meters to the outputs. Adjust the input level so that the output distortion is 0.5% for a f = 1kHz sine wave input.
This output voltage is the maximum output level Vom (VP-P).
Note 2: Input a f = 1MHz, 1VP-P sine wave. The voltage gain GV = 20 log VOUT / VIN (dB).
Note 3: Input a f = 1MHz and 10MHz, 1VP-P sine wave. The frequency characteristic Gf = 20 log VOUT (f = 10M) / VOUT (f = 1M) (dB).
Note 4: Input a f = 4.43MHz, 1VP-P sine wave.
0dB amplifier SW crosstalk is CTM0, and the 6dB amplifier SW crosstalk is CTM6.
CTM0 = 20 log VOUT / VIN (dB)
CTM6 = 20 log VOUT / VIN + 6 (dB)
7
Multimedia ICs
BA7630S / BA7630F
Circuit operation
•Digital
block truth table
INPUT
OUTPUT
Note
Reset
Clock
Data
SW1···························SW9
H
×
L
L
L
H
×
×
×
L
↑
H
SW1-O ·····················SW 9-O
Data "L" sent to internal shift register
L
↑
L
SW1-O ·····················SW 9-O
Data "H" sent to internal shift register
L
↓
L
SW1-O ·····················SW 9-O
Internal shift register data unchanged
L
↓
H
SW1-N ·····················SW 9-N
Contents of internal shift register sent to
internal latch
H····································H
—
SW1-O ·····················SW 9-O
—
SW1-O ·····················SW 9-O
—
Note 1: H: high level
Note 2: L: low level
Note 3: ×: either H or L
Note 4: ↑: L to H transition
Note 5: ↓: H to L transition
Note 6: SW1-O to SW9-O: SW1 to SW9 levels before establishing the input conditions shown in the table.
Note 7: SW1-N to SW9-N
nearest clock ↓ transition.
Analog truth table
(1) OUT1 switch
SW1
SW2
RESET
SELECT
L
L
H
IN1
L
H
H
IN2
H
L
H
IN3
H
H
H
IN3
(2) OUT2 switch
SW3
RESET
SELECT
L
H
IN1
H
H
IN3
(3) OUT3 switch
SW4
RESET
SELECT
L
H
IN2
H
H
IN4
Note: When using the switches independently
without the digital block, the RESET pin
must be set to "H".
8
Multimedia ICs
BA7630S / BA7630F
circuit operation
•(1)Digital
Introduction
The BA7630S has 9-bit serial-to-parallel converter and
latch circuit that has been included to expand the number of microprocessor output ports. The breakdown
voltage of the output pins is 13V, so switch them in the
range 0 to 12V. In addition to controlling the BA7630S
switching block, these outputs can be used to control
audio switching, scrambling decoders, and television
sets.
(2) Using the serial-to-parallel convertor block
Signal input is basically done using clock and date
pulses. As shown in Fig.10, the date is read on the rising edge of the clock pulses. If the date is “H” on the
rising edge of the clock pulse, a “L” data bit is input to
the shift register, and if the data is “L” on the rising
edge of the clock pulse, a “H” data bit is input to the
shift register. The shift register is sequentially incremented by the bit corresponding to SW 1 . Data in
excess of 9 bits is sequentially discarded.
If the data is “H” on a falling edge of the clock, the contents of the shift register are read into the internal latch,
and simultaneously output to the output port (the data
polarity is inverted on output). This output is maintained
until the latch is setup again.
To reset, set the RESET pin to “H”. The internal shift
register and latch contents go low (latch output all “H”),
for the duration that RESET is held high.
(3) Pulse timing
The pulse timing diagrams are given below.
CLK
DATA
tsu
tsu
0.1µs (Typ.) 1.0µs (Max.)
Fig. 6 Clock rising edge and data relationship
(setup time)
CLK
DATA
tsu
tsu
0.1µs (Typ.) 1.0µs (Max.)
Fig. 7 Clock falling edge and data relationship
(setup time)
RESET
SW1 ~ SW9
OUT
CLK
tPLH
tPHL
0.26µs (Typ.) 2.0µs (Max.)
DATA
1
2
3
4
Fig. 8 Reset and output relationship
(reset transmission time)
5
At points 1 to 4 data is input to the shift register.
At point 5 the contents of the shift register are transferred to the
latch and simultaneously output.
Fig. 4 CLK and DATA relationship
CLK
Data flow
DATA
Data in
1
2
3
4
5
6
7
8
9
—
Q
—
Q
—
Q
—
Q
—
Q
—
Q
—
Q
—
Q
—
Q
Shift register
SW1 ~ SW9
OUT
Latch
Latch
tPLH9 tPHL
Reset
1.2µs (Typ.) 5.0µs (Max.)
SW1 SW2
SW9
Fig. 5 Digital block
Fig. 9 Clock falling edge and output relationship
(latch transmission time)
9
Multimedia ICs
BA7630S / BA7630F
•Timing chart
RESET
DATA
CLOCK
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
SW9
RESET
DATA
Fig.10
10
DATA
RESET
Multimedia ICs
BA7630S / BA7630F
examples
•(1)Application
Analog block
BA7630S pin layout
2
5V
+
IN2
VCC2
R
+
IN3
7
6dB
AMP
1
6dB
AMP
12
75Ω
470 ~ 1000µF
2SA933
VCC2
R
+
1µF
75Ω
+
IN4
1µF
75Ω
GND
11
to VCR
+
22
OUT3
from
VIDEO OUT
47µF
OUT1
5
1µF
75Ω
OUT2
from
TV OUT
VCC1
VCC
3
+
IN1
1µF
75Ω
+
from
DECODER OUT
+
from
VTR TUNER OUT
75Ω
470 ~ 1000µF
2SA933
to
DECODER IN
to
TV IN
VCC2
R
5V
100
12V
390
GND
6
13
Fig.11
(2) Digital block
VCC 4.5 ~ 13V
22k
SW OUT
SW1 ~ SW9
OPEN
COLLECTOR
50kΩ
SW1 ~ SW4
ONLY
28kΩ
Fig.12
11
Multimedia ICs
BA7630S / BA7630F
0
3pin-22pin
5pin-22pin
7pin-22pin
VIN = 10VP-P
– 20
– 30
GAIN (dB)
0
–2
–4
–6
–8
– 10
– 12
– 14
– 16
– 18
– 20
3pin-22pin
5pin-22pin
7pin-22pin
VIN = 1.0VP-P
– 10
CROSSTALK: CT (dB)
GAIN (dB)
•Electrical characteristic curves
– 40
– 50
– 60
– 70
100k 200k 500k 1M 2M
5M 10M 20M 30M
100k 200k
FREQUENCY (Hz)
500k 1M
2M
6
4
2
0
–2
–4
–6
–8
– 10
– 12
– 14
100k 200k 500k 1M 2M
5M 10M 20M
5M 10M 20M 30M
FREQUENCY (Hz)
FREQUENCY (Hz)
Fig. 13 Frequency characteristic(OUT1)
Fig. 15 Frequency characteristic
(OUT2 and OUT3)
Fig. 14 Crosstalk characteristic (OUT1)
0
1pin-11pin
5pin-11pin
3pin-12pin
7pin-12pin
Input 1VP-P
– 10
– 20
CROSSTALK: CT (dB)
1pin-11pin
5pin-11pin
3pin-12pin
7pin-12pin
Input 1VP-P
– 30
– 40
– 50
– 60
– 70
100k 200k
500k 1M
2M
5M 10M 20M
FREQUENCY (Hz)
Fig. 16 Crosstalk characteristic
(OUT2 and OUT3)
•External dimensions (Units: mm)
BA7630S
BA7630F
18.5 ± 0.2
19.4 ± 0.3
28
1.778
0.5 ± 0.1
0° ~ 15°
7.5 ± 0.2
15
1
0.15 ± 0.1
0.3 ± 0.1
2.2 ± 0.1
7.62
0.11
11
1
9.9 ± 0.3
12
6.5 ± 0.3
0.51Min.
3.4 ± 0.2 3.95 ± 0.3
22
14
1.27
0.4 ± 0.1
0.3Min.
0.15
SDIP22
12
SOP28
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