AVAGO HCPL-5301 Intelligent power module and gate drive interface hermetically sealed optocoupler Datasheet

HCPL-5300, HCPL-5301, HCPL-530K, 5962-96852
Intelligent Power Module and Gate Drive
Interface Hermetically Sealed Optocouplers
Data Sheet
Description
Features
The HCPL-530X devices consist of a GaAsP LED optically
coupled to an integrated high gain photo detector in a
hermetically sealed package. The products are capable of
operation and storage over the full military temperature
range and can be purchased as either standard product
or with full MIL-PRF-38534 Class Level H or K testing or
from the DLA Drawing 5962-96852. All devices are manufactured and tested on a MIL-PRF-38534 certified line
and are included in the DLA Qualified Manufacturers
List QML-38534 for Hybrid Microcircuits. Minimized propagation delay difference between devices make these
optocouplers excellent solutions for improving inverter
efficiency through reduced switching dead time. An on
chip 20 k output pull-up resistor can be enabled by
shorting output pins 6 and 7, thus eliminating the need
for an external pull-up resistor in common IPM applications. Specifications and performance plots are given for
typical IPM applications.
 Performance specified over full military temperature
Range: -55° C to +125° C
 Minimized pulse width distortion (PWD = 450 ns)
 High common mode rejection (CMR): 10 kV/s at VCM =
1000 V
 CTR > 30% at IF = 10 mA
 1500 Vdc withstand test voltage
 Manufactured and tested on a MIL-PRF-38534 certified
line
 Hermetically sealed packages
 Dual marked with device part number and DLA
drawing number
 QML-38534, Class H and K
Schematic Diagram
 HCPL-4506 function compatibility
8
1
 Fast maximum propagation delays
tPHL = 450 ns,
tPLH = 650 ns
Applications
 Military and space
20 k
2
7
3
6
 High reliability systems
 Harsh industrial environments
 Transportation, medical, and life critical systems
4
5
SHIELD
 IPM isolation
 Isolated IGBT/MOSFET gate drive
Truth Table
LED
VO
ON
L
OFF
H
 AC and brushless DC motor drives
 Industrial inverters
The connection of a 0.1 F bypass capacitor between pins 5 and 8 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Selection Guide-Lead Configuration Options
Avago Part # and Options
Commercial
HCPL-5300
MIL-PRF-38534, Class H
HCPL-5301
MIL-PRF-38534, Class K
HCPL-530K
Standard Lead Finish
Gold Plate
Solder Dipped*
Option #200
Butt Cut/Gold Plate
Option #100
Gull Wing/Soldered*
Option #300
Class H SMD Part #
Prescript for all below
5962-
Gold Plate
9685201HPC
Solder Dipped*
9685201HPA
Butt Cut/Gold Plate
9685201HYC
Butt Cut/Soldered*
9685201HYA
Gull Wing/Soldered*
9685201HXA
Class K SMD Part #
Prescript for all below
5962-
Gold Plate
9685201KPC
Solder Dipped*
9685201KPA
Butt Cut/Gold Plate
9685201KYC
Butt Cut/Soldered*
9685201KYA
Gull Wing/Soldered*
9685201KXA
*Solder contains lead.
Outline Drawing
9.40 (0.370)
9.91 (0.390)
0.76 (0.030)
1.27 (0.050)
8.13 (0.320)
MAX.
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
3.81 (0.150)
MIN.
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
2
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
Device Marking
Avago DESIGNATOR
Avago P/N
DLA SMD*
DLA SMD*
PIN ONE/
ESD IDENT
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
COUNTRY OF MFR.
Avago CAGE CODE*
Hermetic Optocoupler Options
Option
Description
100
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on
commercial and hi-rel product in 8 pin DIP (see drawings below for details).
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
300
Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in
8 pin DIP. DLA Drawing part numbers contain provisions for lead finish.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available
on commercial and hi-rel product in 8 pin DIP (see drawings below for details). This option has solder dipped leads.
4.57 (0.180)
MAX.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
1.40 (0.055)
1.65 (0.065)
4.57 (0.180)
MAX.
5° MAX.
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Note: Solder contains lead.
3
0.20 (0.008)
0.33 (0.013)
9.65 (0.380)
9.91 (0.390)
1.07 (0.042)
1.32 (0.052)
Absolute Maximum Ratings
Parameter
Symbol
Min.
Storage Temperature
TS
-65
+150
°C
Operating Temperature
TA
-55
+125
°C
Junction Temperature
TJ
+175
°C
260 for 10 sec
°C
Average Input Current
IF(AVG)
25
mA
Peak Input Current
(50% duty cycle, ≤ 1 s pulse width)
IF(PEAK)
50
mA
1.0
A
5
V
Lead Solder Temperature
Peak Transient Input Current
(≤ 1 s pulse width, 300 pps)
Reverse Input Voltage (Pin 3-2)
VR
Max.
Units
Average Output Current (Pin 6)
IO(AVG)
15
mA
Resistor Voltage (Pin 7)
V7
-0.5
VCC
V
Output Voltage (Pin 6-5)
VO
-0.5
30
V
Supply Voltage (Pin 8-5)
VCC
-0.5
30
V
Output Power Dissipation
PO
100
mW
Total Power Dissipation
PT
145
mW
ESD Classification
(MIL-STD-883, Method 3015)
( ), Class 1
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Power Supply Voltage
VCC
4.5
30
Volts
Output Voltage
VO
0
30
Volts
Input Current (ON)
IF(ON)
10
20
mA
Input Voltage (OFF)
VF(OFF)
-5
0.8
V
4
Electrical Specifications
Over recommended operating conditions (TA = -55° C to +125° C, VCC = +4.5 V to 30 V, IF(ON) = 10 mA to 20 mA,
VF(OFF) = -5 V to 0.8 V) unless otherwise specified.
Parameter
Symbol
Group A
Subgroups[12]
Min.
Typ.*
Current Transfer Ratio
CTR
1, 2, 3
30
Low Level Output
Current
IOL
1, 2, 3
3.0
Low Level Output
Voltage
VOL
1, 2, 3
0.3
Input Threshold
Current
ITH
1, 2, 3
High Level Output
Current
IOH
High Level Supply
Current
Units
Test Conditions
90
%
IF = 10 mA,
VO = 0.6 V
9.0
mA
IF = 10 mA,
VO = 0.6 V
0.6
V
IO = 2.4 mA
1.5
5.0
mA
VO = 0.8 V,
IO = 0.75 mA
1
1, 2, 3
5
75
A
VF = 0.8 V
3
ICCH
1, 2, 3
0.6
1.5
mA
VF = 0.8 V,
VO = Open
7
Low Level Supply
Current
ICCL
1, 2, 3
0.6
1.5
mA
IF = 10 mA,
VO = Open
7
Input Forward Voltage
VF
1, 2, 3
1.5
1.8
V
IF = 10 mA
Temperature Coefficient
of Forward Voltage
VF/TA
mV/°C
IF = 10 mA
Input Reverse
Breakdown Voltage
BVR
V
IR = 100 A
Input Capacitance
CIN
pF
f = 1 MHz,
VF = 0 V
Input-Output Insulation
Leakage Current
II-O
A
RH ≤ 65%,
t = 5 sec,
VI-O = 1500 Vdc,
TA = 25° C
2
Resistance
(Input-Output)
RI-O
1012

VI-O = 500 Vdc
2
Capacitance
(Input-Output)
CI-O
2.4
pF
f = 1 MHz
2
Internal Pull-up Resistor
RL
k
TA = 25° C
4, 5, 6
Internal Pull-up Resistor
Temperature Coefficient
RL/TA
*All typical values at 25° C, VCC = 15 V.
5
1.0
Max.
-1.6
1, 2, 3
5
90
1
1
1.0
14
20
0.014
28
k/°C
Fig.
Note
1
1, 2
7
4
Switching Specifications (RL= 20 k External)
Over recommended operating conditions: (TA = -55° C to +125° C, VCC = +4.5 V to 30 V, IF(ON) = 10 mA to 20 mA,
VF(OFF) = -5 V to 0.8 V) unless otherwise specified.
Parameter
Symbol
Group A
Subgrps.[12]
Min.
Typ.*
Max.
Units
Test Conditions
Propagation Delay
Time to Low
Output Level
tPHL
9, 10, 11
30
180
450
ns
CL = 100 pF
ns
CL = 10 pF
Propagation Delay
Time to High
Output Level
tPLH
ns
CL = 100 pF
Pulse Width
Distortion
PWD
Propagation Delay
Difference Between
Any Two Parts
tPLH -tPHL 9, 10, 11
Output High Level
Common Mode
Immunity Transient
|CMH|
Output Low Level
Common Mode
Transient Immunity
|CML|
100
250
350
650
CL = 10 pF
130
*All typical values at 25° C, VCC = 15 V.
6
9, 10, 11
9, 10, 11
150
450
ns
CL = 100 pF
-170
140
500
ns
9
10
17
kV/s
IF = 0 mA,
VO > 3.0 V
9
10
17
kV/s
IF = 10 mA
VO < 1.0 V
IF(on) = 10 mA,
VF(off ) = 0.8 V,
VCC = 15.0 V,
V THLH = 2.0 V,
V THHL = 1.5 V
Fig.
Note
5, 7,
9-12
3, 4, 5,
6, 7
11
8
VCC = 15.0 V,
6, 17, 9, 13
CL = 100 pF,
18, 21
VCM = 1000 VP-P
TA = 25° C
10, 13
Switching Specifications (RL= Internal Pull-up)
Over recommended operating conditions: (TA = -55°C to +125°C, VCC = +4.5 V to 30 V, IF(ON) = 10 mA to 20 mA,
VF(OFF) = -5 V to 0.8 V) unless otherwise specified.
Parameter
Symbol
Group A
Subgrps.[12]
Min.
Typ.*
Max.
Units
Test Conditions
Fig.
Note
Propagation Delay
Time to Low
Output Level
tPHL
9, 10, 11
20
185
500
ns
5, 8,
3, 4, 5,
6, 7
Propagation Delay
Time to High
Output Level
tPLH
9, 10, 11
220
415
750
ns
IF(on) = 10 mA,
VF(off ) = 0.8 V,
VCC = 15.0 V,
CL = 100 pF,
V THLH = 2.0 V
V THHL = 1.5 V
150
600
ns
11
150
650
ns
8
Pulse Width Distortion PWD
9, 10, 11
Propagation Delay
Difference Between
Any Two Parts
tPLH -tPHL 9, 10, 11
-225
Output High Level
Common Mode
Transient Immunity
|CMH|
10
kV/s
IF = 0 mA,
VO > 3.0 V
Output Low Level
Common Mode
Transient Immunity
|CML|
10
kV/s
IF = 16 mA
VO < 1.0 V
Power Supply
Rejection
PSR
1.0
VP-P
Square Wave, tRISE, tFALL > 5 ns,
no bypass capacitors.
VCC = 15.0 V,
6, 21
CL = 100 pF,
VCM = 1000 VP-P
TA = 25° C
9
10
7
*All typical values at 25° C, VCC = 15 V.
Notes:
1. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (IO) to the forward LED input current (IF) times 100.
2. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together and Pins 5, 6, 7 and 8 shorted together.
3. Pulse: f = 20 kHz, Duty Cycle = 10%
4. The internal 20 k resistor can be used by shorting pins 6 and 7 together.
5. Due to the tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performance can be improved
by using an external 20 k 1% load resistor. For more information on how propagation delay varies with load resistance, see Figure 8.
6. The RL = 20 k, CL = 100 pF represents a typical IPM (Intelligent Power Module) load.
7. Use of a 0.1 F bypass capacitor connected between pins 5 and 8 can improve performance by filtering power supply line noise.
8. The difference in tPLH and tPHL between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay Specifications
section.)
9. Common mode transient immunity in a Logic High level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a Logic High state (i.e., VO > 3.0 V).
10. Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a Logic Low state (i.e., VO < 1.0 V).
11. Pulse Width Distortion (PWD) is defined as the difference between tPLH and tPHL for any given device.
12. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25° C, +125° C, and -55° C (Subgroups
1 and 9, 2 and 10, 3 and 11 respectively).
13. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specified
for all lots not specifically tested.
7
LED Drive Circuit Considerations For Ultra High CMR
Performance
Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the
input side of the optocoupler, through the package, to
the detector IC as shown in Figure 14. The HCPL-530X
improves CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts
the capacitively coupled current away from the sensitive
IC circuitry. However, this shield does not eliminate the
capacitive coupling between the LED and the optocoupler
output pins and output ground as shown in Figure 15.
This capacitive coupling causes perturbations in the LED
current during common mode transients and becomes
the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED
drive circuit becomes keeping the LED in the proper state
(on or off ) during common mode transients. For example,
the recommended application circuit (Figure 13), can
achieve 10 kV/s CMR while minimizing component complexity. Note that a CMOS gate is recommended in Figure
13 to keep the LED off when the gate is in the high state.
Another cause of CMR failure for a shielded optocoupler
is direct coupling to the optocoupler output pins through
CLEDO1 and CLEDO2 in Figure 15. Many factors influence the
effect and magnitude of the direct coupling including: the
use of an internal or external output pull-up resistor, the
position of the LED current setting resistor, the connection of the unused input package pins, and the value of
the capacitor at the optocoupler output (CL).
Techniques to keep the LED in the proper state and
minimize the effect of the direct coupling are discussed in
the next two sections.
CMR With The LED On (CMRL)
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that
it is not pulled below the threshold during a transient.
The recommended minimum LED current of 10 mA
provides adequate margin over the maximum ITH of
5.0 mA (see Figure 1) to achieve 10 kV/s CMR. Capacitive
coupling is higher when the internal load resistor is used
(due to CLEDO2) and an IF = 16 mA is required to obtain
10 kV/s CMR.
The placement of the LED current setting resistor affects
the ability of the drive circuit to keep the LED on during
transients and interacts with the direct coupling to the
optocoupler output. For example, the LED resistor in
Figure 16 is connected to the anode. Figure 17 shows the
AC equivalent circuit for Figure 16 during common mode
transients. During a +dVCM/dt in Figure 17, the current
available at the LED anode (ITOTAL) is limited by the series
resistor. The LED current (IF) is reduced from its DC value
by an amount equal to the current that flows through
CLEDP and CLEDO1. The situation is made worse because
the current through CLEDO1 has the effect of trying to pull
the output high (toward a CMR failure) at the same time
the LED current is being reduced. For this reason, the recommended LED drive circuit (Figure 13) places the current
setting resistor in series with the LED cathode. Figure 18
is the AC equivalent circuit for Figure 13 during common
mode transients. In this case, the LED current is not
reduced during a +dVCM/dt transient because the current
flowing through the package capacitance is supplied by
the power supply. During a -dVCM/dt transient, however,
the LED current is reduced by the amount of current
flowing through CLEDN. But better CMR performance is
achieved since the current flowing in CLEDO1 during a
negative transient acts to keep the output low.
Coupling to the LED and output pins is also affected by the
connection of pins 1 and 4. If CMR is limited by perturbations in the LED on current, as it is for the recommended
drive circuit (Figure 13), pins 1 and 4 should be connected
to the input circuit common. However, if CMR performance is limited by direct coupling to the output when the
LED is off, pins 1 and 4 should be left unconnected.
8
CMR With The LED Off (CMRH)
IPM Dead Time and Propagation Delay Specifications
A high CMR LED drive circuit must keep the LED off
(VF ≤ VF(OFF)) during common mode transients. For
example, during a +dVCM/dt transient in Figure 18, the
current flowing through CLEDN is supplied by the parallel
combination of the LED and series resistor. As long as the
voltage developed across the resistor is less than VF(OFF)
the LED will remain off and no common mode failure will
occur. Even if the LED momentarily turns on, the 100 pF
capacitor from pins 6-5 will keep the output from dipping
below the threshold. The recommended LED drive circuit
(Figure 13) provides about 10 V of margin between
the lowest optocoupler output voltage and a 3 V IPM
threshold during a 10 kV/s transient with VCM = 1000 V.
Additional margin can be obtained by adding a diode
in parallel with the resistor, as shown by the dashed line
connection in Figure 18, to clamp the voltage across the
LED below VF(OFF).
These devices include a Propagation Delay Difference
specification intended to help designers minimize “dead
time” in their power inverter designs. Dead time is the time
period during which both the high and low side power
transistors (Q1 and Q2 in Figure 22) are off. Any overlap in
Q1 and Q2 conduction will result in large currents flowing
through the power devices between the high and low
voltage motor rails.
Since the open collector drive circuit, shown in Figure 19,
cannot keep the LED off during a +dVCM/dt transient, it is
not desirable for applications requiring ultra high CMRH
performance. Figure 20 is the AC equivalent circuit for
Figure 16 during common mode transients. Essentially
all the current flowing through CLEDN during a +dVCM/dt
transient must be supplied by the LED. CMRH failures can
occur at dv/dt rates where the current through the LED
and CLEDN exceeds the input threshold. Figure 21 is an
alternative drive circuit which does achieve ultra high
CMR performance by shunting the LED in the off state.
To minimize dead time the designer must consider the
propagation delay characteristics of the optocoupler
as well as the characteristics of the IPM IGBT gate drive
circuit. Considering only the delay characteristics of the
optocoupler (the characteristics of the IPM IGBT gate drive
circuit can be analyzed in the same way) it is important
to know the minimum and maximum turn-on (tPHL) and
turn-off (tPLH) propagation delay specifications, preferably
over the desired operating temperature range.
The limiting case of zero dead time occurs when the input
to Q1 turns off at the same time that the input to Q2 turns
on. This case determines the minimum delay between
LED1 turn-off and LED2 turn-on, which is related to the
worst case optocoupler propagation delay waveforms,
as shown in Figure 23. A minimum dead time of zero is
achieved in Figure 23 when the signal to turn on LED2
is delayed by (tPLH max - tPHL min) from the LED1 turn off.
This delay is the maximum value for the propagation
delay difference specification which is specified at 500 ns
for the HCPL-530X over an operating temperature range
of -55° C to +125° C.
Delaying the LED signal by the maximum propagation
delay difference ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time occurs in
the highly unlikely case where one optocoupler with the
fastest tPLH and another with the slowest tPHL are in the
same inverter leg. The maximum dead time in this case
becomes the sum of the spread in the tPLH and tPHL propagation delays as shown in Figure 24. The maximum
dead time is also equivalent to the difference between the
maximum and minimum propagation delay difference
specifications. The maximum dead time (due to the optocouplers) for the HCPL-530X is 670 ns (= 500 ns - (-170 ns))
over an operating temperature range of -55° C to +125° C.
9
1.0
NORMALIZED OUTPUT CURRENT
IO – OUTPUT CURRENT – mA
10
8
6
4
VO = 0.6 V
2
0
125°C
25°C
-55°C
0
5
10
15
0.9
0.8
0.7
0.6
IF = 10 mA
VO = 0.6 V
0.5
0
-60 -40 -20 0 20 40 60 80 100 120 140
20
TA – TEMPERATURE – °C
IF – FORWARD LED CURRENT – mA
IOH – HIGH LEVEL OUTPUT CURRENT – PA
Figure 1. Typical transfer characteristics
Figure 2. Normalized output current vs. temperature
1000
25
IF – FORWARD CURRENT – mA
VF = 0.8 V
VCC = VO = 30 V
20
15
10
5
100
IF
+
10
VF
–
1.0
0.1
0.01
0.001
1.10
0
-60 -40 -20 0 20 40 60 80 100 120 140
1.20
1.30
1.40
1.50
1.60
VF – FORWARD VOLTAGE – VOLTS
TA – TEMPERATURE – °C
Figure 3. High level output current vs. temperature
Figure 4. Input current vs. forward voltage
8
1
2
20 k:
0.1 μF
20 k:
IF(ON) =10 mA
+
TA = 25°C
+
–
7
If
VCC = 15 V
5V
–
3
6
tf
VO
VOUT
tr
90%
90%
10%
10%
CL*
4
5
SHIELD
*TOTAL LOAD CAPACITANCE
Figure 5. Propagation delay test circuit
10
VTHHL
VTHLH
tPHL
tPLH
1
8
0.1 μF
20 k:
IF
2
20 k:
7
+
–
A
B
3
6
4
5
VCM
VCC = 15 V
GV = VCM
Gt
't
VOUT
100 pF*
+
OV
't
SHIELD
VFF
*100 pF TOTAL
CAPACITANCE
–
VO
VCC
SWITCH AT A: IF = 0 mA
VO
–
+
VOL
SWITCH AT B: IF = 10 mA
VCM = 1000 V
Figure 6. CMR test circuit. Typical CMR waveform
500
600
IF = 10 mA
VCC = 15 V
CL = 100 pF
RL = 20 k: (EXTERNAL)
tP – PROPAGATION DELAY – ns
tP – PROPAGATION DELAY – ns
600
400
tPLH
tPHL
300
200
100
-60 -40 -20 0 20 40 60 80 100 120 140
IF = 10 mA
VCC = 15 V
CL = 100 pF
RL = 20 k: (INTERNAL)
500
400
tPLH
tPHL
300
200
100
-60 -40 -20 0 20 40 60 80 100 120 140
TA – TEMPERATURE – °C
TA – TEMPERATURE – °C
Figure 7. Propagation delay with external 20 k RL vs. temperature
1400
tP – PROPAGATION DELAY – ns
tP – PROPAGATION DELAY – ns
800
1000
400
tPLH
tPHL
200
10
20
IF = 10 mA
VCC = 15 V
RL = 20 k:
TA = 25°C
1200
IF = 10 mA
VCC = 15 V
CL = 100 pF
TA = 25 °C
600
0
30
40
50
RL – LOAD RESISTANCE – K:
Figure 9. Propagation delay vs. load resistance
11
Figure 8. Propagation delay with internal 20 k RL vs. temperature
tPLH
tPHL
800
600
400
200
0
0
100
200
300
400
500
CL – LOAD CAPACITANCE – pF
Figure 10. Propagation delay vs. load capacitance
500
IF = 10 mA
CL = 100 pF
RL = 20 k:
TA = 25°C
tPLH
tPHL
1200
1000
tP – PROPAGATION DELAY – ns
tP – PROPAGATION DELAY – ns
1400
800
600
400
200
0
5
10
15
20
VCC – SUPPLY VOLTAGE – V
300
200
0
10
5
15
20
Figure 12. Propagation delay vs. input current
8
1
2
7
3
6
20 k:
CLEDP
+
– VCC = 15 V
20 k:
2
7
3
VOUT
CMOS
6
CLEDN
100 pF
4
8
1
0.1 μF
20 k:
310 :
tPLH
tPHL
IF – FORWARD LED CURRENT – mA
Figure 11. Propagation delay vs. supply voltage
+5 V
400
100
30
25
VCC = 15 V
CL = 100 pF
RL = 20 k:
TA = 25°C
5
4
SHIELD
5
SHIELD
*100 pF TOTAL
CAPACITANCE
Figure 13. Recommended LED drive circuit
8
1
2
Figure 14. Optocoupler input to output
capacitance model for unshielded optocouplers
CLEDP
CLED02
2
7
3
6
20 k:
+
– VCC = 15 V
310 :
6
CLEDN
4
0.1 μF
20 k:
7
CLED01
3
8
1
+5 V
20 k:
CMOS
5
SHIELD
VOUT
100 pF
4
5
SHIELD
*100 pF TOTAL
CAPACITANCE
Figure 15. Optocoupler input to output
capacitance model for shielded optocouplers
12
Figure 16. LED drive circuit with resistor connected to LED anode (not recommended)
8
1
8
1
300 
ICLEDP
2
IF
CLED02
CLEDP
7
CLED01
CLED02
20 k
7
CLEDN
6
VOUT
ICLEDN*
+ VR** –
100 pF
4
3
VOUT
6
CLEDN
CLEDP
CLED01
300 
ICLED01
3
2
20 k
100 pF
4
5
SHIELD
5
SHIELD
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
+
–
+
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH
PERFORMANCE. VR < VF (OFF) DURING +dVCM/dt.
VCM
–
ITOTAL*
20
k
20
k
VCM
Figure 17. AC equivalent circuit for Figure 16 during common mode transients
Figure 18. AC equivalent circuit for Figure 13 during common mode transients
8
1
2
8
+5 V
20 k
7
3
6
Q1
4
5
SHIELD
CLED02
20 k
7
CLED01
Q1
2
CLEDP
3
CLEDN
6
VOUT
ICLEDN*
100 pF
4
5
SHIELD
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
+
–
1
20
k
VCM
Figure 19. Not recommended open collector LED drive circuit
8
1
+5 V
20 k
2
7
3
6
4
5
SHIELD
Figure 21. Recommended LED drive circuit for ultra high CMR
13
Figure 20. AC equivalent circuit for Figure 19 during common mode transients
HCPL-5300
8
1
20 k
I
LED1
2
+5 V
VCC1
0.1 μF
IPM
20 k
7
+HV
310 
3
6
4
5
VOUT1
CMOS
Q1
M
SHIELD
Q2
HCPL-5300
8
1
20 k
I
LED2
2
+5 V
VCC2
0.1 μF
HCPL-5300
20 k
7
HCPL-5300
310 
3
6
4
5
VOUT2
CMOS
Figure 22. Typical application circuit
ILED1
Q1 OFF
VOUT1
VOUT2
HCPL-5300
HCPL-5300
SHIELD
Q1 ON
Q2 OFF
Q2 ON
ILED2
tPLH MAX.
tPHL
MIN.
PDD* MAX. =
(tPLH-tPHL) MAX. = tPLH MAX. - tPHL MIN.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE
PDD ARE TAKEN AT EQUAL TEMPERATURES.
Figure 23. Minimum LED skew for zero dead time
14
HCPL-5300
-HV
MIL-PRF-38534 Class H, Class K, and
DLA SMD Test Program
ILED1
Q1 OFF
VOUT1
VOUT2
Q1 ON
Q2 OFF
Q2 ON
ILED2
Testing consists of 100% screening and quality conformance inspection to MIL-PRF-38534.
tPLH
MIN.
tPLH
MAX.
PDD*
MAX.
Avago Technologies’ Hi-Rel Optocouplers are in compliance with MIL-PRF-38534 Classes H and K. Class H and
Class K devices are also in compliance with DLA drawing
5962-96852.
tPHL
MIN.
tPHL
MAX.
MAX.
DEAD TIME
MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)
= (tPLH MAX. - tPLH MIN.) + (tPHL MAX. - tPHL MIN.)
= (tPLH MAX. - tPHL MIN.) - (tPLH MIN. - tPHL MAX.)
= PDD* MAX. - PDD* MIN.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM
DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.
Figure 24. Waveforms for dead time calculations
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5968-9402EN
AV02-3839EN - October 10, 2012
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