www.fairchildsemi.com
FSD210, FSD200
Green Mode Fairchild Power Switch (FPSTM)
Features
• Single Chip 700V Sense FET Power Switch
• Precision Fixed Operating Frequency (134kHz)
• Advanced Burst-Mode operation Consumes under 0.1W
at 265Vac and no load (FSD210 only)
• Internal Start-up Switch and Soft Start
• Under Voltage Lock Out (UVLO) with Hysteresis
• Pulse by Pulse Current Limit
• Over Load Protection (OLP)
• Internal Thermal Shutdown Function (TSD)
• Auto-Restart Mode
• Frequency Modulation for EMI
• FSD200 does not require an auxiliary bias winding
Applications
• Charger & Adaptor for Mobile Phone, PDA & MP3
• Auxiliary Power for White Goods, PC, C-TV & Monitor
OUTPUT POWER TABLE
230VAC ±15%(3)
PRODUCT
85-265VAC
Open
Open
Adapter(1)
Adapter(1)
Frame(2)
Frame(2)
FSD210
5W
7W
4W
5W
FSD200
5W
7W
4W
5W
FSD210M
5W
7W
4W
5W
FSD200M
5W
7W
4W
5W
Table 1. Notes: 1. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient. 2.
Maximum practical continuous power in an open frame
design at 50°C ambient. 3. 230 VAC or 100/115 VAC with
doubler.
Typical Circuit
Description
The FSD200 and FSD210 are integrated Pulse Width Modulators (PWM) and Sense FETs specially designed for high
performance off-line Switch Mode Power Supplies (SMPS)
with minimal external components. Both devices are monolithic high voltage power switching regulators which combine an LDMOS Sense FET with a voltage mode PWM
control block. The integrated PWM controller features include: a fixed oscillator with frequency modulation for reduced EMI, Under Voltage Lock Out (UVLO) protection,
Leading Edge Blanking (LEB), optimized gate turn-on/turnoff driver, thermal shut down protection (TSD), temperature
compensated precision current sources for loop compensation and fault protection circuitry. When compared to a discrete MOSFET and controller or RCC switching converter
solution, the FSD200 and FSD210 reduce total component
count, design size, weight and at the same time increase efficiency, productivity, and system reliability. The FSD200
eliminates the need for an auxiliary bias winding at a small
cost of increased supply power. Both devices are a basic platform well suited for cost effective designs of flyback converters.
AC
IN
DC
OUT
Vstr
Drain
PWM
Vfb
Vcc
Source
Figure 1. Typical Flyback Application using FSD210
AC
IN
DC
OUT
Vstr
Drain
PWM
Vfb
Vcc
Source
Figure 2. Typical Flyback Application using FSD200
Rev.1.0.3
©2004 Fairchild Semiconductor Corporation
FSD210, FSD200
Internal Block Diagram
Vstr
8
L
Vcc 5
Voltage
Ref
UVLO
Internal
Bias
7 Drain
H
8.7/6.7V
Frequency
Modulation
5uA
Vck
OSC
SFET
DRIVER
250uA
S
Vfb 4
Q
R
BURST
V BURST
LEB
OLP
Reset
Iover
S
V SD
Rsense
Vth
Q
R
TSD
S/S
3mS
A/R
GND
1, 2, 3
Figure 3. Functional Block Diagram of FSD210
Vstr
8
Vcc 5
HV/REG
7V
UVLO
Frequency
Modulation
5uA
Voltage
Ref.
7 Drain
ON/OFF
INTERNAL
BIAS
Vck
OSC
SFET
DRIVER
250uA
S
Vfb 4
Q
R
BURST
V BURST
LEB
OLP
Iover
Rsense
Vth
Reset
S
V SD
R
TSD
A/R
Q
S/S
3mS
1, 2, 3
Figure 4. Functional Block Diagram of FSD200 showing internal high voltage regulator
2
GND
FSD210, FSD200
Pin Definitions
Pin Number
Pin Name
1, 2, 3
GND
4
5
7
8
Pin Function Description
Sense FET source terminal on primary side and internal control ground.
Vfb
The feedback voltage pin is the inverting input to the PWM comparator with
nominal input levels between 0.5Vand 2.5V. It has a 0.25mA current source
connected internally while a capacitor and opto coupler are typically
connected externally. A feedback voltage of 4V triggers overload protection
(OLP). There is a time delay while charging between 3V and 4V using an
internal 5uA current source, which prevents false triggering under transient
conditions but still allows the protection mechanism to operate under true
overload conditions.
Vcc
FSD210
Positive supply voltage input. Although connected to an auxiliary
transformer winding, current is supplied from pin 8 (Vstr) via an internal
switch during startup (see Internal Block Diagram section). It is not until Vcc
reaches the UVLO upper threshold (8.7V) that the internal start-up switch
opens and device power is supplied via the auxiliary transformer winding.
FSD200
This pin is connected to a storage capacitor. A high voltage regulator
connected between pin 8 (Vstr) and this pin, provides the supply voltage to
the FSD200 at startup and when switching during normal operation. The
FSD200 eliminates the need for auxiliary bias winding and associated
external components.
Drain
The Drain pin is designed to connect directly to the primary lead of the
transformer and is capable of switching a maximum of 700V. Minimizing the
length of the trace connecting this pin to the transformer will decrease
leakage inductance.
Vstr
The startup pin connects directly to the rectified AC line voltage source for
both the FSD200 and FSD210. For the FSD210, at start up the internal
switch supplies internal bias and charges an external storage capacitor
placed between the Vcc pin and ground. Once this reaches 8.7V, the
internal current source is disabled. For the FSD200, an internal high voltage
regulator provides a constant supply voltage.
Pin Configuration
7-DIP
7-LSOP
GND
1
8
Vstr
GND
2
7
Drain
GND
3
Vfb
4
5
Vcc
Figure 5. Pin Configuration (Top View)
3
FSD210, FSD200
Absolute Maximum Ratings
(Ta=25°C unless otherwise specified)
Parameter
Symbol
Value
Unit
Maximum Supply Voltage (FSD200)
VCC,MAX
10
V
Maximum Supply Voltage (FSD210)
VCC,MAX
20
V
VFB
−0.3 to VSTOP
V
Input Voltage Range
Operating Junction Temperature.
TJ
+150
°C
Operating Ambient Temperature
TA
−25 to +85
°C
TSTG
−55 to +150
°C
Symbol
Value
Unit
θJA(1)
θJA(1)
θJC(2)
74.07(3)
°C/W
(4)
°C/W
22.00
°C/W
θJA(1)
θJA(1)
θJC(2)
-
°C/W
-
°C/W
-
°C/W
Storage Temperature Range
Thermal Impedance
Parameter
7DIP
Junction-to-Ambient Thermal
Junction-to-Case Thermal
60.44
7LSOP
Junction-to-Ambient Thermal
Junction-to-Case Thermal
Note:
1. Free standing without heat sink.
2. Measured on the GND pin close to plastic interface.
3. Soldered to 100mm2 copper clad.
4. Soldered to 300mm2 copper clad.
4
FSD210, FSD200
Electrical Characteristics
(Ta=25°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
700
-
-
V
700
-
-
V
Sense FET SECTION
Drain-Source Breakdown Voltage
BVDSS
Startup Voltage (Vstr) Breakdown
BVSTR
Off-State Current
IDSS
On-State Resistance
RDS(ON)
VCC = 0V, ID = 100µA
VDS = 560V
-
-
100
µA
Tj = 25°C, ID = 25mA
-
28
32
Ω
Tj = 100°C, ID = 25mA
-
42
48
Ω
Rise Time
TR
VDS = 325V, ID = 50mA
-
100
-
ns
Fall Time
TF
VDS = 325V, lD = 25mA
-
50
-
ns
CONTROL SECTION
Output Frequency
FOSC
Tj = 25°C
126
134
142
kHz
Output Frequency Modulation
FMOD
Tj = 25°C
-
±4
-
kHz
IFB
Vfb = 0V
0.22
0.25
0.28
mA
60
65
70
%
Feedback Source Current
Maximum Duty Cycle
Minimum Duty Cycle
DMAX
Vfb = 3.5V
DMIN
Vfb = 0V
VSTART
UVLO Threshold Voltage (FSD200)
VSTOP
After turn on
VSTART
UVLO Threshold Voltage (FSD210)
VSTOP
Supply Shunt Regulator (FSD200)
After turn on
-
0
0
%
7
7.7
V
5.3
6
6.7
V
8.0
8.7
9.4
V
6.0
6.7
7.4
V
-
7
-
V
TS/S
-
3
-
ms
VBURH
0.58
0.64
0.7
V
0.5
0.58
0.64
V
Hysteresis
-
60
-
mV
IOVER
0.275
0.320
0.365
A
-
220
-
ns
125
145
160
°C
3.5
4.0
4.5
V
3
5
7
µA
200
-
-
ns
-
µA
VCCREG
Internal Soft Start Time
0
6.3
BURST MODE SECTION
VBURL
Burst Mode Voltage
Tj = 25°C
PROTECTION SECTION
Drain to Source Peak Current Limit
Current Limit
Delay(1)
Thermal Shutdown Temperature (Tj)
Shutdown Feedback Voltage
Feedback Shutdown Delay Current
Leading Edge Blanking Time(2)
TCLD
(1)
Tj = 25°C
TSD
-
VSD
IDELAY
Vfb = 4.0V
TLEB
TOTAL DEVICE SECTION
Operating Supply Current (FSD200)
IOP
Vcc = 7V
-
600
IOP
Vcc = 11V
-
700
-
µA
Start Up Current (FSD200)
ISTART
Vcc = 0V
-
1
1.2
mA
Start Up Current (FSD210)
ISTART
Vcc = 0V
-
700
900
µA
Vcc = 0V
20
-
-
V
Operating Supply Current (FSD210)
Vstr Supply Voltage
Note:
1. These parameters, although guaranteed, are not 100% tested in production
2. This parameter is derived from characterization
5
FSD210, FSD200
Comparison Between FSDH565 and FSD210
Function
6
FSDH0565
FSD210
FSD210 Advantages
Soft-Start
not applicable
3mS
• Gradually increasing current limit
during soft-start further reduces peak
current and voltage component
stresses
• Eliminates external components used
for soft-start in most applications
• Reduces or eliminates output
overshoot
Switching Frequency
100kHz
134kHz
• Smaller transformer
Frequency Modulation
not applicable
±4kHz
• Reduced conducted EMI
Burst Mode Operation
not applicable
Yes-built into
controller
• Improve light load efficiency
• Reduces no-load consumption
• Transformer audible noise reduction
Drain Creepage at
Package
1.02mm
3.56mm DIP
3.56mm LSOP
• Greater immunity to acting as a result
of build-up of dust, debris and other
contaminants
FSD210, FSD200
Typical Performance Characteristics
1.2
1.2
1.0
1.0
Operating Current (A)
Fosc (kHz)
(These characteristic graphs are normalized at Ta=25℃)
0.8
0.6
0.4
0.2
0.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
125
-25
Junction Temperature (℃)
50
75
100
125
Operating Current vs. Temp
1.2
Feedback SOurce Current (A)
1.2
Peak Current Limit (A)
25
Junction Temperature (℃)
Frequency vs. Temp
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100
1.0
0.8
0.6
0.4
0.2
0.0
125
-25
Junction Temperature (℃)
0
25
50
75
100
125
Junction Temperature (℃)
Peak Current Limit vs. Temp
Feedback Source Current vs. Temp
1.20
1.20
1.00
1.00
0.80
0.80
Vstop (V)
Vstart (V)
0
0.60
0.40
0.20
0.60
0.40
0.20
0.00
0.00
-25
0
25
50
75
100
Junction Temperature (℃)
Vstart Voltage vs. Temp
125
-25
0
25
50
75
100
125
Junction Temperature (℃)
Vstop Voltage vs. Temp
7
FSD210, FSD200
Typical Performance Characteristics (Continued)
1.8
1.2
1.6
1.4
1.0
1.2
0.8
BVdss (V)
On State Resistance (Ω)
(These characteristic graphs are normalized at Ta=25℃)
1.0
0.8
0.6
0.4
0.2
0.4
0.2
0.0
0.0
-25
0
25
50
75
100
125
-25
50
75
100
On State Resistance vs. Temp
Breakdown Voltage vs. Temp
1.2
1.2
1.0
1.0
0.8
0.8
0.6
0.4
125
0.6
0.4
0.2
0.2
0.0
0.0
0
25
50
75
100
-25
125
0
25
50
75
100
125
Junction Temperature (℃)
Junction Temperature (℃)
Vcc Regulation Voltage vs. Temp (for FSD200)
Shutdown Feedback Voltage vs. Temp
1.4
1.2
1.2
1.0
Istart (A)
1.0
Istart (A)
25
Junction Temperature (℃)
-25
0.8
0.6
0.4
0.8
0.6
0.4
0.2
0.2
0.0
0.0
-25
0
25
50
75
100
Junction Temperature (℃)
Start Up Current vs. Temp (for FSD210)
8
0
Junction Temperature (℃)
VSD (V)
Vcc Regulation Voltage (V)
0.6
125
-25
0
25
50
75
100
Junction Temperature (℃)
Start Up Current vs. Temp (for FSD200)
125
FSD210, FSD200
Functional Description
Vin,dc
1. Startup : At startup, the internal high voltage current
source supplies the internal bias and charges the external
Vcc capacitor as shown in figure 7. In the case of the
FSD210, when Vcc reaches 8.7V the device starts switching
and the internal high voltage current source is disabled (see
figure 1). The device continues to switch provided that Vcc
does not drop below 6.7V. For FSD210, after startup, the
bias is supplied from the auxiliary transformer winding. In
the case of FSD200, Vcc is continuously supplied from the
external high voltage source and Vcc is regulated to 7V by
an internal high voltage regulator (HVReg), thus eliminating
the need for an auxiliary winding (see figure 2).
Vin,dc
Istr
UVLO
Vref
FSD2xx
Vcc
Vcc must not drop
to UVLO stop
Vstr
Vcc
H
8.7V/
6.7V
J-FET
100uA
Istr
Vstr
L
Vstr
i = Is tr - m ax 1 00 u A
i = Istr-max
100uA
Vcc
max
UVLO
start
Vin,dc
Vcc
Istr
FSD210
UVLO
stop
Auxiliary winding
voltage
HV
Reg.
7V
t
FSD200
Figure 6. Internal startup circuit
Figure 7. Charging the Vcc capacitor through Vstr
Calculating the Vcc capacitor is an important step to designing in the FSD200/210. At initial start-up in both the
FSD200/210, the stand-by maximum current is 100uA, supplying current to UVLO and Vref Block. The charging current (i) of the Vcc capacitor is equal to Istr - 100uA. After
Vcc reaches the UVLO start voltage only the bias winding
supplies Vcc current to device. When the bias winding voltage is not sufficient, the Vcc level decreases to the UVLO
stop voltage. At this time Vcc oscillates. In order to prevent
this ripple it is recommended that the Vcc capacitor be sized
between 10uF and 47uF.
3. Leading edge blanking (LEB) : At the instant the internal Sense FET is turned on, there usually exists a high current spike through the Sense FET, caused by the primary side
capacitance and secondary side rectifier diode reverse recovery. Exceeding the pulse-by-pulse current limit could cause
premature termination of the switching pulse (see Protection
Section). To counter this effect, the FPS employs a leading
edge blanking (LEB) circuit. This circuit inhibits the over
current comparator for a short time (TLEB) after the Sense
FET is turned on.
2. Feedback Control : The FSD200/210 are both voltage
mode devices as shown in Figure 8. Usually, a H11A817
optocoupler and KA431 voltage reference (or a FOD2741
integrated optocoupler and voltage reference) are used to
implement the isolated secondary feedback network. The
feedback voltage is compared with an internally generated
sawtooth waveform, directly controlling the duty cycle.
When the KA431 reference pin voltage exceeds the internal
reference voltage of 2.5V, the optocoupler LED current
increases pulling down the feedback voltage and reducing
the duty cycle. This event will occur when either the input
voltage increases or the output load decreases.
Vcc
5uA
Vfb
Vo
OSC
Vref
0.25mA
Gate
driver
FB
4
Cfb
R
KA431
VSD
OLP
Figure 8. PWM and feedback circuit
4. Protection Circuit : The FSD200/210 has 2 self protection functions: over load protection (OLP) and thermal shutdown (TSD). Because these protection circuits are fully
integrated into the IC with no external components, system
9
FSD210, FSD200
reliability is improved without a cost increase. If either of
these thresholds are triggered, the FPS starts an auto-restart
cycle. Once the fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to
fall. When Vcc reaches the UVLO stop voltage
(6.7V:FSD210, 6V:FSD200), the protection is reset and the
internal high voltage current source charges the Vcc capacitor. When Vcc reaches the UVLO start voltage
(8.7V:FSD210,7V:FSD200), the device attempts to resume
normal operation. If the fault condition is no longer present
start up will be successful. If it is still present the cycle is
repeated (see figure 10).
to detect the temperature of the Sense FET. When the temperature exceeds approximately 145°C, thermal shutdown is
activated.
Vfb
under Vstop of UVLO
OLP
4V
3V
FPS Switching Area
Idelay (5uA) charges Cfb
IC Reset
OSC
t
5uA
250uA
Vfb
4
R
Cfb
S
+
-
GATE
DRIVER
Q
R
3V
RESET
Vth 4V
R
TSD
A/R
Q
FSD2xx
OLP, TSD
Protection Block
Figure 9. Protection block
4.1 Over Load Protection (OLP) : Over load protection
occurs when the load current exceeds a pre-set level due to
an abnormal situation. If this occurs, the protection circuit
should be triggered to protect the SMPS. It is possible that a
short term load transient can occur under normal operation.
In order to avoid false shutdowns, the over load protection
circuit is designed to trigger after a delay. Therefore the
device can differentiate between transient over loads and
true fault conditions. The maximum input power is limited
using the pulse-by-pulse current limit feature. If the load
tries to
draw more than this, the output voltage will drop below its
set value. This reduces the optocoupler LED current which
in turn reduces the photo-transistor current (see figure 9).
Therefore, the 250uA current source will charge the feedback pin capacitor, Cfb, and the feedback voltage, Vfb, will
increase. The input to the feedback comparator is clamped at
3V. Once Vfb reaches 3V, the device switches at maximum
power, the 250uA current source is blocked and the 5uA
source continues to charge Cfb. Once Vfb reaches 4V,
switching stops.and overload protection is triggered. The
resultant shutdown delay time is set by the time required to
charge Cfb from 3Vto 4Vwith 5uA as shown in Fig. 10.
4.2 Thermal Shutdown (TSD) : The Sense FET and the
control IC are integrated, making it easier for the control IC
t2
t3
t1<<t2, t3
t1 = -1/RCΧ ln( 1-v(t1)/R )
t2 = Cfb Χ {v(t1+t2)-v(t1)} / Idelay
OLP
S
10
t1
v(t1)=3V
Figure 10. Over load protection delay
5. Soft Start : FSD200/210 has an internal soft start circuit
that gradually increases current through the Sense FET as
shown in figure 11. The soft start time is 3msec in FSD200/
210.
I(A)
3mS
0.3A
Iover
0.25A
0.2A
t
FSD200/210
Figure 11. Internal Soft Start
6. Burst operation : In order to minimize the power dissipation in standby mode, the FSD200/210 implements burst
mode functionality (see figure 12). As the load decreases, the
feedback voltage decreases. As shown in figure 13, the
device automatically enters burst mode when the feedback
voltage drops below VBURL(0.58V). At this point switching
stops and the output voltages start to drop at a rate dependant
on standby current load. This causes the feedback voltage to
rise. Once it passes VBURH(0.64V) switching starts again.
The feedback voltage falls and the process repeats. Burst
mode operation alternately enables and disables switching of
the power Sense FET thereby reducing switching loss in
FSD210, FSD200
standby mode.
Internal
Oscillator
OSC
138kHz
S
5uA
250uA
Q
GATE
DRIVER
R
4
Drain to
Source
voltage
on/off
Vfb
0.64V
/0.58V
FSD2xx
Burst Operation Block
Drain to
Source
current
Figure 12. Circuit for burst operation
Vds
Waveform
8kHz
130kHz
134kHz
138kHz
Vo
Voset
Turn-off
point
Turn-on
Figure 14. Frequency Modulation Waveforms
VFB
0.64V
0.58V
CISPR22Q(PK)
CISPR22A(AV)
Amplitude(dBµV)
Ids
Vds
time
Frequency(MHz)
7. Frequency Modulation : EMI reduction can be accomplished by modulating the switching frequency of a SMPS.
Frequency modulation can reduce EMI by spreading the
energy over a wider frequency range. The amount of EMI
reduction is directly related to the level of modulation
(Fmod) and the rate of modulation. As can be seen in Figure
14, the frequency changes from 130kHz to 138kHz in 4mS
for the FSD200/FSD210. Frequency modulation allows the
use of a cost effective inductor instead of an AC input mode
choke to satisfy the requirements of world wide EMI limits.
Figure 15. FSDH0165 Full Range EMI scan(100kHz, no
Frequency Modulation) with charger set
CISPR22Q(PK)
CISPR22A(AV)
Amplitude(dBµV)
Figure 13. Burst mode operation
Frequency(MHz)
Figure 16. FSD210 Full Range EMI scan(134kHz, with Frequency Modulation) with charger set
11
FSD210, FSD200
Typical application circuit
Application
Output power
Input voltage
Output voltage (Max current)
Cellular Phone Charger
3.38W
Universal input (85-265Vac)
5.2V (650mA)
Features
•
•
•
•
•
•
High efficiency (>67% at Universal Input)
Low zero load power consumption (<100mW at 240Vac) with FSD210
Low component count
Enhanced system reliability through various protection functions
Internal soft-start (3ms)
Frequency Modulation for low EMI
Key Design Notes
• The constant voltage (CV) mode control is implemented with resistors, R8, R9, R10 and R11, shunt regulator, U2, feedback
capacitor, C9 and opto-coupler, U3.
• The constant current (CC) mode control is designed with resistors, R8, R9, R15, R16, R17 and R19, NPN transistor, Q1 and
NTC, TH1. When the voltage across current sensing resistors, R15,R16 and R17 is 0.7V, the NPN transistor turns on and the
current through the opto coupler LED increases. This reduces the feedback voltage and duty ratio. Therefore, the output
voltage decreases and the output current is regulated.
• The NTC(negative thermal coefficient) is used to compensate the temperature characteristics of the transistor Q1.
1. Schematic
C6 152M-Y, 250Vac
R6
R7
4.7M 1/4W 4.7M, 1/4W
L1 330uH
Fuse
AC
1W, 10R
1
R1 4.7k
D1
1N4007
D2
1N4007
AC
D3
1N4007
R3
47k
C1
4.7UF 400V
D4
1N4007
C2
4.7uF 400V
7
L3
R9
56R
C7
330uF 16V
2
8
Vo
4uH
SB260
C3
102k 1kV
R4
47k
0
D7
TX1
R8
510R
(5.2V/0.65A)
C8
330uF 16V
R10
2.2k
U3
H11A817B
.
C9 470nF
D5
UF4007
D6
5
GND
4
H11A817B
R5
1
3
12
Q1
KSP2222A
R12
2k
0
TH1 10k
R19
510R
C5
33uF 50V
R15 3R0
R16 3R0
4
For FSD21x
U2
TL431
1N4148 39R
3
GND
1
Vcc
Vfb
GND
Vstr
2
8
U1
FSD210
Drain
7
C10
4.7uF 50V
R17 3R0
0
C4
100nF
FSD210, FSD200
2. Demo Circuit Part List
Reference
Part #
Quantity
Description
Requirement/Comment
D1,D2,D3,D4
1N4007
4
1A/1000V Junction Rectifier
DO41 Type
D5
UF4007
1
1A/1000V Ultra Fast Diode
DO41 Type
D6
1N4148
1
10mA/100V Junction Diode
D0-213 Type
D7
SB260
1
2A/60V Schottky Diode
D0-41 Type
Q1
KSP2222A
1
Ic=600mA, Vce=30V
TO-92 Type
U1
FSD210
(FSD200)
1
0.5A/700V
Iover=0.3A, Fairchildsemi
U2
KA431AZ
1
Vref=2.495V(Typ.)
TO-92 Type, LM431
U3
H11A817A
1
CTR 80~160%
-
3. Transformer Schematic Diagram
2mm
1
8
2
7
2mm
W4
W3
3
W2
6
W1
.
4
5
CORE : EE1616
BOBBIN : EE1616(H)
4. Winding Specification
No.
Pin (S → F)
Wire
Turns
Winding Method
W1
1→ 2
0.16Φ Χ 1
99 Ts
SOLENOID WINDING
INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 2Ts
4→3
W2
0.16Φ Χ 1
18 Ts
CENTER SOLENOID
WINDING
INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 2Ts
W3
1 → open
0.16Φ Χ 1
50 Ts
SOLENOID WINDING
INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 3Ts
8→7
W4
0.40Φ Χ 1
9 Ts
SOLENOID WINDING
INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 3Ts
5. Electrical Characteristics
ITEM
TERM INAL
SPECIFICATION
SPECIFICAT ION
REM ARKS
INDUCTANCE
1–2
1.6mH
1kHz, 1V
LEAKAGE L
1–2
50uH
3,4,7,8 short
100kHz, 1V
13
FSD210, FSD200
Typical application circuit
Application
Output power
Non Isolation Buck
1.2W
Input voltage
Output voltage (Max current)
Universal dc input
12V (100mA)
(100 ~ 375Vac)
Features
• Non isolation buck converter
• Low component count
• Enhanced system reliability through various protection functions
Key Design Notes
• The output voltage(12V) is regulated with resistors, R1, R2 and R3, zener diode, D3, the transistor, Q1 and the capacitor,
C2. While the FSD210 is off diodes, D1 and D2, are on. At this time the output voltage, 12V, can be sensed by the feedback
components above. This output is also used with bias voltage for the FSD210.
• R, 680K, is to prevent the OLP(over load protection) at startup.
• R, 8.2K, is a dummy resistor to regulate output voltage in light load.
1. Schematic
R2
110
GND
GND
UF4004
4
Vfb
D3(ZD)
1N759A
3
1
C1
4.7uF/400V
GND
U1
FSD21x
Vstr
D2
5
Vcc
2
8
Drain
7
VINDC
R1 110
R
680K
C2
47nF/50V
C5
47uF 50V
Q1
KSP2222A
R3
750
D1
VOUT(12V/100mA)
L1
GND
1mH
UF4004
C4
1000uF 16V
R
8.2K
GND
0
2. Demo Circuit Part List
Reference
Part #
Quantity
Description
Requirement/Comment
D1,D2
D1,D2,
UF4007
2
11A/1000V Ultra Fast Diode
DO41 Type
Q1
KSP2222A
1
Ic=200mA, Vcc=40V
TO-92 Type
ZD1
1N759A
1
12VZD/0.5W
DO-35 Type
U1
FSD210
1
0.5A/700V
Iover=0.3A
14
FSD210, FSD200
Layout Considerations (for Flyback Convertor)
Copper area for heatsink
#1 : GND
#2 : GND
#3 : GND
#4 : Vfb
#5 : Vcc
#6 : N.C.
#7 : Drain
#8 : Vstr
Figure 17. Layout Considerations for FSD2x0 using 7DIP
15
FSD210, FSD200
Package Dimensions
7-DIP
16
FSD210, FSD200
Package Dimensions (Continued)
7-LSOP
17
FSD210, FSD200
Ordering Information
Product Number
Package
Rating
Topr (°C)
FSD210
7DIP
700V, 0.5A
−25°C to +85°C
FSD200
7DIP
700V, 0.5A
−25°C to +85°C
FSD210M
7LSOP
700V, 0.5A
−25°C to +85°C
FSD200M
7LSOP
700V, 0.5A
−25°C to +85°C
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
6/21/04 0.0m 001
2004 Fairchild Semiconductor Corporation