IDT ICS9P935YFLF-T Ddr i/ddr ii phase lock loop zero delay buffer Datasheet

DATASHEET
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Pin Configuration
DDR I/DDR II Zero Delay Clock Buffer
DDRC0
DDRT0
VDD2.5/1.8
DDRT1
DDRC1
GND
VDDA2.5/1.8
GND
CLK_INT
CLK_INC
VDD2.5/1.8
DDRT2
DDRC2
GND
Output Features
•
•
•
•
•
•
•
•
Low skew, low jitter PLL clock driver
Max frequency supported = 400MHz (DDRII 800)
I2C for functional and output control
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Programmable skew through SMBus
Frequency defect control thorugh SMBus
Individual output control programmable through SMBus
Key Specifications
•
•
•
•
•
•
CYCLE - CYCLE jitter: <100ps
OUTPUT - OUTPUT skew: <100ps
DUTY CYCLE: 48% - 52%
28-pin SSOP package
Available in RoHS compliant packaging
Operates @ 2.5V or 1.8V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ICS9P935
Description
GND
DDRC5
DDRT5
VDD2.5/1.8
GND
DDRC4
DDRT4
VDD2.5/1.8
SDATA
SCLK
FB_IN
FB_OUT
DDRT3
DDRC3
28-SSOP/TSSOP
Funtional Block Diagram
FB_OUT
SCLK
SDATA
Control
DDRT0
DDRC0
Logic
DDRT1
DDRC1
DDRT2
DDRC2
DDRT3
DDRC3
FB_IN
CLK_INT
PLL
DDRT4
DDRC4
CLK_INC
DDRT5
DDRC5
IDTTM/ICSTM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
ICS9P935
1
REV H 12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Pin Description
Pin# Pin Name
1
DDRC0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DDRT0
VDD2.5/1.8
DDRT1
DDRC1
GND
VDDA2.5/1.8
GND
CLK_INT
CLK_INC
VDD2.5/1.8
DDRT2
DDRC2
GND
DDRC3
DDRT3
FB_OUT
18
FB_IN
19
20
21
22
23
24
25
26
27
28
SCLK
SDATA
VDD2.5/1.8
DDRT4
DDRC4
GND
VDD2.5/1.8
DDRT5
DDRC5
GND
Type
OUT
Pin Description
"Complementary" Clock of differential pair output.
OUT
PWR
OUT
OUT
PWR
PWR
PWR
IN
IN
PWR
OUT
OUT
PWR
OUT
OUT
OUT
"True" Clock of differential pair output.
Power supply, nominal 2.5V or 1.8V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
Output power supply, nominal 2.5V or 1.8V
Ground pin.
"True" reference clock input.
"Complementary" reference clock input.
Power supply, nominal 2.5V or 1.8V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
Feedback output, dedicated for external feedback.
Single-ended feedback input, provides feedback signal to internal PLL to eliminate
phase error with the input clock.
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Power supply, nominal 2.5V or 1.8V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
Power supply, nominal 2.5V or 1.8V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
IN
IN
I/O
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
IDTTM/ICSTM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
ICS9P935
2
REV H 12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Absolute Max
Supply Voltage
Logic Inputs
Ambient Operating Temperature
Case Temperature
Storage Temperature
-0.5V to 2.7V
GND –0.5 V to VDD +0.5 V
0°C to +70°C
115°C
–65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Input High Current
IIH
V I = VDD or GND
Input Low Current
IIL
V I = VDD or GND
Output Disabled Low
OE = L, VODL = 100mV
100
IODL
Current
Operating Supply
IDD1.8 CL = 0pf @ 100MHz
Current
I DDLD CL = 0pf
Input Clamp Voltage
VIK
V DDQ = 1.8V Iin = -18mA
High-level output
I OH = -100µA
VDD -0.2
V OH
voltage
I OH = -9mA
1.1
I OL=100µA
Low-level output voltage
V OL
I OL=9mA
1
CIN
V I = GND or VDD
2
Input Capacitance
1
C
V
=
GND
or
V
2
Output Capacitance
OUT
OUT
DD
IDTTM/ICSTM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
MAX
±250
±10
µA
300
500
-1.2
0.1
0.6
3
3
ICS9P935
3
UNITS
µA
µA
mA
µA
V
V
V
V
V
pF
pF
REV H 12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Recommended Operating Condition (see note1)
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Supply Voltage
V DDQ, AVDD
1.7
Low level input voltage
VIL
CLK_INT, CLK_INC, FB_IN
High level input voltage
V IH
CLK_INT, CLK_INC, FB_IN
0.65 x V DD
-0.3
DC input signal voltage (note 2)
V IN
V IN-Diff
CLK_INT, CLK_INC
GND - 0.3
DC input signal voltage swing
DC - CLK_INT, CLK_INC,
0.3
Differential input signal voltage
FB_IN
V ID
(note 3)
AC - CLK_INT, CLK_INC,
0.6
FB_IN
Output differential cross-voltage
VOX
V DD / 2 - 0.1
(note 4)
Input differential cross-voltage
V IX
V DD/2 - 0.15
(note 4)
High level output current
IOH
Low level output current
IOL
High Impedance
V DD=1.9V, V OUT=V DD or GND
IOZ
Output Current
0
Operating free-air temperature
TA
TYP
1.8
1.5
MAX
1.9
0.35 x VDD
V DD + 0.3
VDD + 0.3
UNITS
V
V
V
V
V
V DD + 0.4
V
V DD + 0.4
V
V DD / 2 + 0.1
V
VDD/2 V DD / 2 + 0.15
V
-9
9
mA
mA
±10
mA
70
°C
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required
for switching, where VTR is the true input level and VCP is the complementary input
level.
4. Differential cross-point voltage is expected to track variations of VDD and is the voltage
at which the differential signal must be crossing.
IDTTM/ICSTM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
ICS9P935
4
REV H 12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Timing Requirements
TA = 0 - 70°C Supply Voltage AVDD, VDD = 1.8 V +/- 0.1V (unless otherwise stated)
CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
Max clock frequency
freqop
Application Frequency
Range
freqApp
Input clock duty cycle
dtin
CLK stabilization
UNITS
1.8V+0.1V @ 25°C
125
500
MHz
1.8V+0.1V @ 25°C
160
400
MHz
40
60
%
15
µs
TSTAB
Switching Characteristics1
PARAMETER
Output enable time
Output disable time
Period jitter
Half-period jitter
Input slew rate
Output clock slew rate
Cycle-to-cycle period jitter
Dynamic Phase Offset
Phase error
Output to Output Skew
SSC modulation frequency
SSC clock input frequency deviation
SYMBOL
t en
tdis
tjit (per)
t jit(hper)
SLr1(i)
CONDITION
OE to any output
OE to any output
Input Clock
Output Enable (OE), (OS)
SLr1(o)
tjit(cc+)
t jit(cc-)
t ( )dyn
t(phase error)2
t skew
MIN
-40
-75
1
0.5
1.5
0
0
-50
-50
TYP
2.5
2.5
0
30.00
0.00
MAX
8
8
40
75
4
3
40
-40
50
50
40
33
-0.50
UNITS
ns
ns
ps
ps
v/ns
v/ns
v/ns
ps
ps
ps
ps
ps
kHz
%
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error increases at
higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc)
decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
IDTTM/ICSTM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
ICS9P935
5
REV H 12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5V ± 0.2V
PARAMETER
Input High Current
Input Low Current
Operating Supply
Current
Output High Current
SYMBOL
IIH
IIL
IDD2.5
IDDPD
IOH
Output Low Current
IOL
VDD = 2.3V, VOUT = 1.2V
IOZ
VDD=2.7V, Vout=VDD or GND
±10
mA
VIK
VDDQ = 2.3V Iin = -18mA
-1.2
V
High Impedance
Output Current
Input Clamp Voltage
High-level output
voltage
Low-level output voltage
Input Capacitance1
Output Capacitance1
VOH
VOL
CIN
COUT
CONDITIONS
VI = VDD or GND
VI = VDD or GND
CL = 0pf @ 200MHz
CL = 0pf
VDD = 2.3V, VOUT = 1V
VDD = min to max,
IOH = -1 mA
VDDQ = 2.3V,
IOH = -12 mA
VDD = min to max
IOL=1 mA
VDDQ = 2.3V
IOH=12 mA
VI = GND or VDD
VOUT = GND or VDD
MIN
5
TYP
MAX
-18
-32
UNITS
µA
µA
mA
µA
mA
26
35
mA
5
250
100
VDDQ - 0.1
V
1.7
V
0.1
V
0.6
V
3
3
IDTTM/ICSTM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
pF
pF
ICS9P935
6
REV H 12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Recommended Operating Condition (see note 1)
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Supply Voltage
Low level input voltage
High level input voltage
DC input signal voltage
(note 2)
Differential input signal
voltage (note 3)
MAX
2.7
VDD/2 - 0.18
UNITS
V
V
V
-0.3
VDD + 0.3
V
0.36
0.7
VDD + 0.6
VDD + 0.6
V
V
VOX
VDD/2 - 0.15
VDD/2 + 0.15
V
VIX
VDD/2 - 0.2
VDD/2 + 0.2
V
I OH
-30
mA
Low level output current
I OL
-30
mA
Operating free-air
temperature
TA
85
°C
Output differential crossvoltage (note 4)
Input differential crossvoltage (note 4)
High level output
current
SYMBOL
CONDITIONS
VDD, AVDD
DDRT,DDRC
VIL
DDRT,DDRC
VIH
VIN
VID
DC - DDRT
AC - DDRT
MIN
2.3
VDD/2 + 0.18
0
TYP
2.5
0.4
2.1
VDD/2
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required
for switching, where VT is the true input level and VCP is the complementary input level.
4. Differential cross-point voltage is expected to track variations of VDD and is the voltage
at which the differential signal must be crossing.
IDTTM/ICSTM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
ICS9P935
7
REV H 12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Timing Requirements
TA = 0 - =70°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
Max clock frequency
freqop
Application Frequency
Range
Input clock duty cycle
freqApp
o
2.5V+0.2V @ 25 C
2.5V+0.2V @ 25oC
dtin
CLK stabilization
UNITS
45
600
MHz
95
233
MHz
40
60
%
15
µs
TSTAB
Switching Characteristics3
PARAMETER
Low-to high level
propagation delay time
High-to low level propagation
delay time
Period jitter
Half-period jitter
Input clock slew rate
Output clock slew rate
Cycle to Cycle Jitter1
Static Phase Offset
Output to Output Skew
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
t PLH1
BUF_IN to any output
3.5
ns
t PLL1
BUF_IN to any output
3.5
ns
Tjit (per)
t(jit_hper)
t sl(i)
t sl(o)
Tcyc -Tcyc
100MHz to 200MHz
100MHz to 200MHz
100MHz to 200MHz
t (static phase offset)4
Tskew
-30
-100
1
1
-50
-50
0
30
100
4
2
50
50
40
ps
ps
V/ns
V/ns
ps
ps
ps
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error increases at
higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc)
decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
IDTTM/ICSTM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
ICS9P935
8
REV H 12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
General I2C serial interface information for the ICS9P935
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D4 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D4(H)
WRite
WR
Controller (host) will send start bit.
Controller (host) sends the write address D4 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D5 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Controller (Host)
T
starT bit
Slave Address D4(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D5(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
Notes:
1.
2.
3.
4.
5.
6.
The IDT clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support SMBus block read protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must
be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred.
The Command code and Byte count shown above must be sent, The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
IDTTM/ICSTM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
ICS9P935
9
REV H 12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
2
I C Table: Output Control Register
Byte 6
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
-
Freq Detect
Low Frequency Detect
PLL OFF Control
RW
OFF
ON
1
Bit
Bit
Bit
Bit
Bit
Bit
Bit
-
FB_IN/OUT
DDR_T5/C5
DDR_T4/C4
DDR_T3/C3
DDR_T2/C2
DDR_T1/C1
DDR_T0/C0
FB_OUT Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
Control Function
Type
0
1
PWD
6
5
4
3
2
1
0
2
I C Table: Group Skew Control Register
Pin #
Name
Byte 8
7
6
5
4
3
2
-
DDR Skw3
DDR Skw2
DDR Skw1
DDR Skw0
DDR Skw3
DDR Skw2
Bit 1
-
DDR Skw1
Bit 0
-
DDR Skw0
Bit
Bit
Bit
Bit
Bit
Bit
RW
RW
RW
RW
RW
RW
CLKIN to DDR
Skew Control
CLKIN to DDR
Skew Control
0
0
0
0
0
0
See Table 1: 7-Step Skew
Programming Table
See Table 2: 7-Step Skew
Programming Table
RW
0
RW
0
2
I C Table: Revision ID and Vendor ID Register
Pin #
Name
Control Function
Byte 10
7
6
5
4
3
-
Revision_ID bit 3
Revision_ID bit 2
Revision_ID bit 1
Revision_ID bit 0
Vendor_ID bit3
Bit 2
-
Vendor_ID bit2
Bit 1
-
Vendor_ID bit1
Bit 0
-
Vendor_ID bit0
Bit
Bit
Bit
Bit
Bit
Type
0
1
PWD
RW
RW
RW
RW
RW
-
-
RW
RW
-
-
X
X
X
X
0
Control Function
Type
0
1
Byte Count
Programming b(7:0)
RW
RW
RW
RW
RW
RW
RW
RW
Rev ID
Vendor ID
RW
0
0
1
2
I C Table: Byte Count Register
Byte 15
Pin #
Name
BC7
Bit 7
BC6
Bit 6
BC5
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
I2C Table: All other I2C Registers are Reserved
11
10
01
11
600 ps
500 ps
400 ps
10
N/A
N/A
N/A
01
N/A
N/A
N/A
00
N/A
N/A
N/A
0
0
0
0
1
1
1
1
Writing to this register will
configure how many bytes
will be read back, default is
0F = 15 bytes
Table 2: 7-Steps Skew Programming Table
Table 1: 7-Steps Skew Programming Table
7 Step
PWD
7 Step
11
10
01
300 ps
11
-600 ps
-500 ps
-400 ps
-300 ps
200 ps
10
N/A
N/A
N/A
-200 ps
100 ps
01
N/A
N/A
N/A
-100 ps
0.0 ps
00
N/A
N/A
N/A
0.0 ps
00
LSB
MSB
00
LSB
MSB
IDTTM/ICSTM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
ICS9P935
10
REV H 12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
c
N
L
E1
INDEX
AREA
E
1 2
α
D
A
A2
A1
-Ce
b
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-2.00
-.079
A1
0.05
-.002
-A2
1.65
1.85
.065
.073
b
0.22
0.38
.009
.015
c
0.09
0.25
.0035
.010
D
SEE VARIATIONS
SEE VARIATIONS
E
7.40
8.20
.291
.323
E1
5.00
5.60
.197
.220
e
0.65 BASIC
0.0256 BASIC
L
0.55
0.95
.022
.037
N
SEE VARIATIONS
SEE VARIATIONS
α
0°
8°
0°
8°
VARIATIONS
N
SEATING
PLANE
.10 (.004) C
28
D mm.
MIN
9.90
D (inch)
MAX
10.50
MIN
.390
MAX
.413
ICS9P935
REV H 12/1/08
Reference Doc.: JEDEC Publication 95, MO-150
10-0033
209 mil SSOP
Ordering Information
ICS9P935yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
IDTTM/ICSTM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
11
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
4.40 mm. Body, 0.65 mm. Pitch TSSOP
(173 mil)
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
(25.6 mil)
In Millimeters
COMMON DIMENSIONS
MIN
MAX
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
SEE VARIATIONS
6.40 BASIC
4.30
4.50
0.65 BASIC
0.45
0.75
SEE VARIATIONS
0°
8°
-0.10
In Inches
COMMON DIMENSIONS
MIN
MAX
-.047
.002
.006
.032
.041
.007
.012
.0035
.008
SEE VARIATIONS
0.252 BASIC
.169
.177
0.0256 BASIC
.018
.030
SEE VARIATIONS
0°
8°
-.004
VARIATIONS
N
28
D mm.
MIN
9.60
D (inch)
MAX
9.80
MIN
.378
MAX
.386
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
Ordering Information
ICS9P935yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
IDTTM/ICSTM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
ICS9P935
12
REV H 12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Revision History
Rev.
A
B
C
D
E
F
G
H
Issue Date
2/8/2007
6/4/2007
6/14/2007
Description
Final Release.
Fixed various typos.
Added TSSOP Ordering Information.
1. Updated Output Features: Max Frequency Supported.
6/20/2007 2. Updated DDRI/DDRII Max Clock Frequency.
1. Updated Supply Voltage.
8/16/2007 2. Updated Input High/Low Current Max.
9/5/2007 Updated Electrical Specifications.
11/19/2007 Updated Serial Interface Information.
12/1/2008 Updated Pin Description.
Page #
12
1
5, 8
3
3-5
9
2
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© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated
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13
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