AD AD1671JQ Complete 12-bit 1.25 msps monolithic a/d converter Datasheet

a
FEATURES
Conversion Time: 800 ns
1.25 MHz Throughput Rate
Complete: On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Low Power Dissipation: 570 mW
No Missing Codes Guaranteed
Signal-to-Noise Plus Distortion Ratio
fIN = 100 kHz: 70 dB
Pin Configurable Input Voltage Ranges
Twos Complement or Offset Binary Output Data
28-Pin DIP and 28-Pin Surface Mount Package
Out of Range Indicator
Complete 12-Bit 1.25 MSPS
Monolithic A/D Converter
AD1671
FUNCTIONAL BLOCK DIAGRAM
SHA
OUT
5k
UPO/BPO
VCC
VEE
ACOM
VLOGIC
DCOM
S/H
AIN1
RANGE
SELECT
AIN2
5k
3-BIT
FLASH
DAC
3
REF IN
REF OUT
ENCODE
X4
3-BIT
FLASH
DAC
8-BIT
LADDER
MATRIX
COARSE
4-BIT
FLASH
3
4
FINE
4-BIT
FLASH
CORRECTION LOGIC
2.5V
REF
4
8
LATCHES
AD1671
REF COM
PRODUCT DESCRIPTION
The AD1671 is a monolithic 12-bit, 1.25 MSPS analog-todigital converter with an on-board, high performance sampleand-hold amplifier (SHA) and voltage reference. The AD1671
guarantees no missing codes over the full operating temperature range. The combination of a merged high speed bipolar/
CMOS process and a novel architecture results in a combination of speed and power consumption far superior to previously available hybrid implementations. Additionally, the
greater reliability of monolithic construction offers improved
system reliability and lower costs than hybrid designs.
The fast settling input SHA is equally suited for both multiplexed systems that switch negative to positive full-scale
voltage levels in successive channels and sampling inputs at
frequencies up to and beyond the Nyquist rate. The AD1671
provides both reference output and reference input pins, allowing the on-board reference to serve as a system reference.
An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application.
The AD1671 uses a subranging flash conversion technique,
with digital error correction for possible errors introduced in
the first part of the conversion cycle. An on-chip timing generator provides strobe pulses for each of the four internal
flash cycles. A single ENCODE pulse is used to control the
converter. The digital output data is presented in twos
complement or offset binary output format. An out-of-range
signal indicates an overflow condition. It can be used with
the most significant bit to determine low or high overflow.
12
OTR
MSB
BIT 1 –12
DAV
The performance of the AD1671 is made possible by using high
speed, low noise bipolar circuitry in the linear sections and low
power CMOS for the logic sections. Analog Devices’ ABCMOS-1
process provides both high speed bipolar and 2-micron CMOS
devices on a single chip. Laser trimmed thin-film resistors are
used to provide accuracy and temperature stability.
The AD1671 is available in two performance grades and three
temperature ranges. The AD1671J and K grades are available
over the 0°C to +70°C temperature range. The AD1671A grade
is available over the –40°C to +85°C temperature range. The
AD1671S grade is available over the –55°C to +125°C temperature range.
PRODUCT HIGHLIGHTS
The AD1671 offers a complete single chip sampling 12-bit,
1.25 MSPS analog-to-digital conversion function in a 28-pin
package.
The AD1671 at 570 mW consumes a fraction of the power of
currently available hybrids.
An OUT OF RANGE output bit indicates when the input signal is beyond the AD1671’s input range.
Input signal ranges are 0 V to +5 V unipolar or ± 5 V bipolar,
selected by pin strapping, with an input resistance of 10 kΩ.
The input signal range can also be pin strapped for 0 V to +2.5 V
unipolar or ±2.5 V bipolar with an input resistance of 10 MΩ.
Output data is available in unipolar, bipolar offset or bipolar
twos complement binary format.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD1671–SPECIFICATIONS
DC SPECIFICATIONS (T
MIN
to TMAX with VCC = +5 V 6 5%, VLOGIC = +5 V 6 10%, VEE = –5 V 6 5%, unless otherwise noted)
Parameter
RESOLUTION
CONVERSION TIME
ACCURACY
Integral Nonlinearity (INL)
(S Grade)
Differential Nonlinearity (DNL)
No Missing Codes
Unipolar Offsets1 (+25°C)
Bipolar Zero1 (+25°C)
Gain Error1, 2 (+25°C)
TEMPERATURE COEFFICIENTS3
Unipolar Offset
(S Grade)
Bipolar Zero
(S Grade)
Gain Error3
(S Grade)
Gain Error4
POWER SUPPLY REJECTION5
VCC (+5 V ± 0.25 V)
(S Grade)
VLOGIC (+5 V ± 0.25 V)
(S Grade)
VEE (–5 V ± 0.25 V)
(S Grade)
ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Resistance
(0 V to +2.5 V or ± 2.5 V Range)
(0 V to +5.0 V or ± 5 V Range)
Input Capacitance
Aperture Delay
Aperture Jitter
INTERNAL VOLTAGE REFERENCE
Output Voltage
Output Current
Unipolar Mode
Bipolar Mode
LOGIC INPUTS
High Level Input Voltage, VIH
Low Level Input Voltage, VIL
High Level Input Current, IIH (VIN = VLOGIC)
Low Level Input Current, ILL (VIN = 0 V)
Input Capacitance, CIN
LOGIC OUTPUTS
High Level Output Voltage, VOH (IOH = 0.5 mA)
Low Level Output Voltage, VOL (IOL = 1.6 mA)
POWER SUPPLIES
Operating Voltages
VCC
VLOGIC
VEE
Operating Current
ICC
ILOGIC6
IEE
POWER CONSUMPTION
TEMPERATURE RANGE (SPECIFIED)
J/K
A
S
Min
12
AD1671J/A/S
Typ
Max
Min
12
AD1671K
Typ
800
± 1.5
11
11 Bits Guaranteed
0.1
± 2.5
± 3.0
±9
± 10
0.35
± 0.7
12
12 Bits Guaranteed
0.1
± 25
± 25
± 25
± 30
± 30
± 40
± 20
±4
±5
±4
±5
±4
±5
–2.5
–5.0
0
0
8
2.475
10
10
10
15
20
2.5
+2.5
+5.0
+2.5
+5.0
–2.5
–5.0
0
0
12
8
2.525
2.475
10
10
10
15
20
2.5
+2.5
+1.0
2.0
Max
800
Units
Bits
ns
± 2.5
LSB
Bits
±9
± 10
0.35
LSB
LSB
% FSR
± 25
ppm/°C
± 25
ppm/°C
± 30
ppm/°C
± 20
ppm/°C
±4
LSB
±4
LSB
±4
LSB
+2.5
+5.0
+2.5
+5.0
Volts
Volts
Volts
Volts
12
2.525
Volts
+2.5
+1.0
mA
mA
0.8
+10
+10
Volts
Volts
µA
µA
pF
2.0
0.8
+10
+10
–10
–10
–10
–10
5
5
2.4
2.4
0.4
+4.75
+4.5
–4.75
+5.25
+5.5
–5.25
55
3
–55
570
0
–40
–55
+4.75
+4.5
–4.75
68
5
–68
750
+70
+85
+125
55
3
–55
570
0
–40
–55
MΩ
kΩ
pF
ns
ps
0.4
Volts
Volts
+5.25
+5.5
–5.25
Volts
Volts
Volts
68
5
–68
750
mA
mA
mA
mW
+70
+85
+125
°C
°C
°C
NOTES
1
Adjustable to zero with external potentiometers.
2
Includes internal voltage reference error.
3
+25°C to TMIN and +25°C to TMAX
4
Excludes internal reference drift.
5
Change in gain error as a function of the dc supply voltage.
6
Tested under static conditions. See Figure 15 for typical curve of ILOGIC vs. load capacitance at maximum tC.
Specifications subject to change without notice.
–2–
REV. B
AD1671
(TMIN to TMAX with VCC = +5 V 6 5%, VLOGIC = +5 V 6 10%, VEE = –5 V 6 5%, fSAMPLE = 1 MSPS,
1
lNPUT = 1OO kHz, unless otherwise noted)
AC SPECIFICATIONS f
Parameter
Min
SIGNAL-TO-NOISE PLUS DISTORTION RATIO
(S/N + D)
–0.5 dB Input
–20 dB Input
68
EFFECTIVE NUMBER OF BITS (ENOB)
AD1671J/A/S
Typ
Max
70
50
Min
AD1671K
Typ
Max
68
11.2
Units
71
51
dB
dB
11.2
Bits
TOTAL HARMONIC DISTORTION (THD)
–80
–75
–83
–75
dB
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
–80
–77
–81
–77
dB
SMALL SIGNAL BANDWIDTH
12
12
MHz
2
2
MHz
FULL POWER BANDWIDTH
2
INTERMODULATION DISTORTION (IMD)
2nd Order Products
3rd Order Products
–80
–85
–75
–75
–80
–85
–75
–75
dB
dB
NOTES
1
fIN amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a 0 dB ( ± 5 V) input signal, unless otherwise
indicated.
2
fA = 99 kHz, fB = 100 kHz with fSAMPLE = 1 MSPS.
Specifications subject to change without notice.
(For all grades TMIN to TMAX with VCC = +5 V 6 5%, VLO61C = +5 V 6 10%,
EE = –5 V 6 5%; VIL = 0.8 V, VIH = 2.0 V, VOL = 0.4 V and VOH = 2.4 V)
SWITCHING SPECIFICATIONS V
Parameters
Symbol
Conversion Time
Sample Rate
ENCODE Pulse Width High (Figure 1a)
ENCODE Pulse Width Low (Figure 1b)
DAV Pulse Width
ENCODE Falling Edge Delay
Start New Conversion Delay
Data and OTR Delay from DAV Falling Edge
Data and OTR Valid before DAV Rising Edge
tC
FS
tENC
tENCL
tDAV
tF
tR
tDD1
tSS2
Min
20
20
150
0
0
20
20
Typ
Max
Units
800
1.25
50
ns
MSPS
ns
ns
ns
ns
ns
ns
ns
300
75
75
NOTES
1
tDD is measured from when the falling edge of DAV crosses 0.8 V to when the output crosses 0.4 V or 2.4 V with a 25 pF load capacitor on each output pin.
2
tSS is measured from when the outputs cross 0.4 V or 2.4 V to when the rising edge of DAV crosses 2.4 V with a 25 pF load capacitor on each output pin.
Specifications subject to change without notice.
t ENC
tC
ENCODE
t ENCL
tC
ENCODE
tR
t DAV
tF
DAV
t DD
BIT 1–12
MSB, OTR
DATA 0 (PREVIOUS)
DAV
t SS
t DD
DATA 1
BIT 1–12
MSB, OTR
Figure 1a. Encode Pulse HIGH
REV. B
tR
t DAV
t SS
DATA 0 (PREVIOUS)
Figure 1b. Encode Pulse LOW
–3–
DATA 1
AD1671
PIN DESCRIPTION
Symbol
Pin No.
Type
ACOM
27
P
Analog Ground.
AIN
22, 23
AI
Analog Inputs, AIN1 and AIN2. The AD1671 can be pin strapped for four input ranges:
BIT 1 (MSB)
13
Name and Function
Range
Pin Strap
Signal Input
0 to +2.5 V, ± 2.5 V
0 to +5 V, ± 5 V
Connect AIN1 to AIN2
Connect AIN1 or AIN2 to ACOM
AIN1 or AIN2
AIN1 or AIN2
DO
Most Significant Bit.
BIT 2–BIT 11 12-3
DO
Data Bits 2 through 11.
BIT 12 (LSB)
2
DO
Least Significant Bit.
BPO/UPO
26
AI
Bipolar or Unipolar Configuration Pin. See section on Input Range Connections for details.
DAV
16
DO
Data Available Output. The rising edge of DAV indicates an end of conversion and can be used
to latch current data into an external register. The falling edge of DAV can be used to latch
previous dam into an external register.
DCOM
19
P
Digital Ground.
ENCODE
17
DI
The analog input is sampled on the rising edge of ENCODE.
MSB
14
DO
Inverted Most Significant Bit. Provides twos complement output data format.
OTR
15
DO
Out of Range is Active HIGH when the analog input is out of range. See Output Data Format,
Table III.
REF COM
20
AI
REF COM is the internal reference ground pin. REF COM should be connected as indicated
in the Grounding and Decoupling Rules and Optional External Reference Connection Sections.
REF IN
24
AI
REF IN is the external 2.5 V reference input.
REF OUT
21
AO
REF OUT is the internal 2.5 V reference output.
SHA OUT
25
AO
No Connect for bipolar input ranges. Connect SHA OUT to BPO/UPO for unipolar input ranges.
VCC
28
P
+5 V Analog Power.
VEE
1
P
–5 V Analog Power.
VLOGIC
18
P
+5 V Digital Power.
TYPE: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Outputs; P = Power.
PIN CONFIGURATION
VEE
1
28 VCC
BIT 12 (LSB)
2
27
ACOM
BIT 11
3
26
BPO/UPO
BIT 10
4
25
SHA OUT
BIT 9
5
24
REF IN
BIT 8
6
23
AIN1
BIT 7
7
AD1671
22
AIN2
BIT 6
8
TOP VIEW
(Not to Scale)
21
REF OUT
BIT 5
9
20 REF COM
BIT 4 10
19 DCOM
BIT 3 11
18 VLOGIC
BIT 2 12
17 ENCODE
BIT 1 (MSB) 13
16
MSB 14
DAV
15 OTR
–4–
REV. B
AD1671
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*
Parameter
With Respect to
VCC
ACOM
VEE
ACOM
VLOGIC
DCOM
ACOM
DCOM
VCC
VLOGIC
ENCODE
DCOM
REF IN
ACOM
AIN
ACOM
BPO/UPO ACOM
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
Min
–0 5
–6.5
–0.5
–1.0
–6.5
–0.5
–0.5
–11.0
–0.5
–65
Max
+6.5
+0.5
+6.5
+1.0
+6.5
VLOGIC + 0.5
VCC + 0.5
+11.0
VCC + 0.5
+150
+150
+300
Units
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
°C
°C
°C
Model1
Linearity
Temperature
Range
Package
Option2, 3
AD1671JQ
AD1671KQ
AD1671JP
AD1671KP
AD1671AQ
AD1671AP
AD1671SQ
± 2.5 LSB
± 2 LSB
± 2.5 LSB
± 2 LSB
± 2.5 LSB
± 2.5 LSB
± 3 LSB
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
Q-28
Q-28
P-28A
P-28A
Q-28
P-28A
Q-28
NOTES
1
For details on grade and package offerings screened in accordance with
MIL-STD-883, refer to Analog Devices’ Military Products Databook or
current AD1671/883 data sheet.
2
P = Plastic Leaded Chip Carrier, Q = Cerdip.
3
Analog Devices reserves the right to ship side brazed ceramic packages in
lieu of cerdip.
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods may effect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1671 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
–5–
WARNING!
ESD SENSITIVE DEVICE
AD1671
DEFINITIONS OF SPECIFICATIONS
DYNAMIC SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
SIGNAL-TO-NOISE PLUS DISTORTION (S/ N+D) RATIO
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale.” The
point used as “zero” occurs 1/2 LSB (1.22 mV for a 10 V span)
before the first code transition (all zeros to only the LSB on).
“Full-scale” is defined as a level 1 1/2 LSB beyond the last code
transition (to all ones). The deviation is measured from the low
side transition of each particular code to the true straight line.
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components, including harmonics but excluding dc. The value for S/N+D is expressed in
decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
ENOB is calculated from the expression (S/N+D) = 6.02N +
1.76 dB, where N is equal to the effective number of bits.
DIFFERENTIAL LINEARITY ERROR (NO MISSING
CODES)
TOTAL HARMONIC DISTORTION (THD)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from the ideal value. Thus every
code has a finite width. Guaranteed no missing codes to 11- or
12-bit resolution indicates that all 2048 and 4096 codes, respectively, must be present over all operating ranges. No missing
codes to 11 bits (in the case of a 12-bit resolution ADC) also
means that no two consecutive codes are missing.
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels.
INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products
of order (m + n), at sum and difference frequencies of mfa ±
nfb, where m, n = 0, 1, 2, 3. . . . Intermodulation terms are
those for which m or n is not equal to zero. For example, the
second order terms are (fa + fb) and (fa – fb), and the third order terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (2fb – fa).
The IMD products are expressed as the decibel ratio of the rms
sum of the measured input signals to the rms sum of the distortion terms. The two signals are of equal amplitude and the peak
value of their sum is –0.5 dB from full scale. The IMD products
are normalized to a 0 dB input signal.
UNIPOLAR OFFSET
The first transition should occur at a level 1/2 LSB above analog
common. Unipolar offset is defined as the deviation of the actual from that point. This offset can be adjusted as discussed
later. The unipolar offset temperature coefficient specifies the
maximum change of the transition point over temperature, with
or without external adjustments.
BIPOLAR ZERO
In the bipolar mode the major carry transition (0111 1111 1111 to
1000 0000 0000) should occur for an analog value 1/2 LSB below analog common. The bipolar offset error and temperature
coefficient specify the initial deviation and maximum change in
the error over temperature.
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
The peak spurious or peak harmonic component is the largest
spectral component, excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a fullscale input signal.
GAIN ERROR
The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1/2 LSB below the nominal
full scale (4.9963 volts for 5.000 volts full scale). The gain error
is the deviation of the actual level at the last transition from the
ideal level. The gain error can be adjusted to zero as shown in
Figures 4 through 7.
APERTURE DELAY
Aperture delay is the difference between thc switch delay and
the analog delay of the SHA. This delay represents the point in
time, relative to the rising edge of ENCODE input, that the
analog input is sampled.
APERTURE JITTER
TEMPERATURE COEFFICIENTS
The temperature coefficients for unipolar offset, bipolar zero
and gain error specify the maximum change from the initial
(+25°C) value to the value at TMIN or TMAX.
Aperture jitter is the variation in aperture delay for successive
samples.
POWER SUPPLY REJECTION
The input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input.
FULL POWER BANDWIDTH
One of the effects of power supply error on the performance of
the device will be a small change in gain. The specifications
show the maximum full-scale change from the initial value with
the supplies at the various limits.
–6–
REV. B
AD1671
THEORY OF OPERATION
an input range that is configured with one bit of overlap with the
previous DAC. The overlap allows for errors during the flash
conversion. The first residue voltage is connected to the second
3-bit flash and to the noninverting input of a high speed, differential, gain of eight amplifier. The second flash result is passed
to the correction logic register and to the second segmented current output DAC. The output of the second DAC is connected
to the inverting input of the differential amplifier. The differential amplifier output is connected to a two-step, backend, 8-bit
flash. This 8-bit flash consists of coarse and fine flash converters. The result of the coarse 4-bit flash converter, also configured to overlap one bit of DAC 2, is connected to the correction
logic register and selects one of 16 resistors from which the fine
4-bit flash will establish its span voltage. The fine 4-bit flash is
connected directly to the output latches.
The AD1671 uses a successive subranging architecture. The
analog-to-digital conversion takes place in four independent
steps or flashes. The sampled analog input signal is subranged
to an intermediate residue voltage for the final 12-bit result by
utilizing multiple flashes with subtraction DACs (see the AD1671
functional block diagram).
The AD1671 can be configured to operate with unipolar (0 V to
+5 V, 0 V to +2.5 V) or bipolar (± 5 V, ± 2.5 V) inputs by connecting AIN (Pins 22, 23), SHA OUT (Pin 25) and BPO/UPO
(Pin 26) as shown in Figure 2.
0
TO
+2.5V
AIN1
5k
SHA
AIN2
5k
–2.5V
TO
+2.5V
AIN1
5k
AIN2
5k
SHA
SHA OUT
SHA OUT
AD1671
AD1671
BPO/UPO
BPO/UPO
REF IN
REF IN
REF OUT
REF OUT
AIN1
AIN1
5k
SHA
AIN2
SHA OUT
5k
±5V
The AD1671 is specified for dc and dynamic performance. A
sampling converter’s dynamic performance reflects both quantizer and sample-and-hold amplifier (SHA) performance. Quantizer nonlinearities, such as INL and DNL, can degrade dynamic
performance. However, a SHA is the critical element which has to
accurately sample fast slewing analog input signals. The AD1671’s
high performance, low noise, patented on-chip SHA minimizes
distortion and noise specifications. Nonlinearities are minimized
by using a fast slewing, low noise architecture and subregulation
of the sampling switch to provide constant offsets (therefore
reducing input signal dependent nonlinearities).
5k
SHA OUT
AD1671
AD1671
BPO/UPO
BPO/UPO
REF IN
REF IN
REF OUT
REF OUT
c. 0 V to +5 V Input Range
AD1671 DYNAMIC PERFORMANCE
SHA
AIN2
5k
The AD1671 will flag an out-of-range condition when the input
voltage exceeds the analog input range. OTR (Pin 15) is active
HIGH when an out-of-range high or low condition exists. Bits
1–12 are HIGH when the analog input voltage is greater than
the selected input range and LOW when the analog input is less
than the selected input range.
b. ± 2.5 V Input Range
a. 0 V to +2.5V Input Range
0
TO
+5V
The internal timing generator automatically places the SHA into
the acquire mode when DAV goes LOW. Upon completion of
conversion (when DAV is set HIGH), the SHA has acquired the
analog input to the specified level of accuracy and will remain in
the sample mode until the next ENCODE command.
d. ± 5 V Input Range
Figure 3 is a typical 2k point Fast Fourier Transform (FFT)
plot of a 100 kHz input signal sampled at 1 MHz. The fundamental amplitude is set at –0.5 dB to avoid input signal clipping
of offset or gain errors. Note the total harmonic distortion is approximately –81 dB, signal to noise plus distortion is 71 dB and
the spurious free dynamic range is 84 dB.
Figure 2. AD1671 Input Range Connections
The AD1671 conversion cycle begins by simply providing an
active HIGH level on the ENCODE pin (Pin 17). The rising
edge of the ENCODE pulse starts the conversion. The falling
edge of the ENCODE pulse is specified to operate within a window of time, less than 50 ns after the rising edge of ENCODE
or after the falling edge of DAV. The time window prevents
digitally coupled noise from being introduced during the final
stages of conversion. An internal timing generator circuit accurately controls SHA, flash and DAC timing.
SIGNAL AMPLITUDE – dB
0
Upon receipt of an ENCODE command the input voltage is
held by the front-end SHA and the first 3-bit flash converts the
analog input voltage. The 3-bit result is passed to a correction
logic register and a segmented current output DAC. The DAC
output is connected through a resistor (within the Range/Span
Select Block) to SHA OUT. A residue voltage is created by subtracting the DAC output from SHA OUT, which is less than
one eighth of the full-scale analog input. The second flash has
REV. B
–25
–50
–75
–100
0
FREQUENCY
Figure 3. AD1671 FFT Plot, fIN = 100 kHz, fSAMPLE = 1 MHz
–7–
SPURIOUS FREE DYNAMIC RANGE – dB
AD1671
Figure 4 plots both S/(N+D) and Effective Number of Bits
(ENOB) for a 100 kHz input signal sampled from 666 kHz to
1.25 MHz.
72
S/(N+D) – dB
71.5
11.50
71
70.5
70
11.25
69.5
69
68.5
68
666
714
769
833
909
1000
1111
EFFECTIVE NUMBER OF BITS
11.75
72.5
85
80
75
70
65
60
55
50
45
40
–50 –45
–40 –35 –30 –25 –20 –15 –10
–5
0
ANALOG INPUT – dB
Figure 7. Spurious Free Dynamic Range vs. Input
Amplitude, fIN = 250 kHz
11.00
1250
SAMPLING FREQUENCY – kHz
Figure 4. S/(N/D) vs. Sampling Frequency, fIN = 100 kHz
Figure 5 is a THD plot for a full-scale 100 kHz input signal with
the sample frequency swept from 666 kHz to 1.25 MHz.
–68
–70
–72
–74
THD – dB
–76
–78
–80
–82
–84
–86
666
714
769
833
909
1000
1111
1250
SAMPLING FREQUENCY – kHz
Figure 5. THD vs. Sampling Rate, fIN = 100 kHz
APPLYING THE AD1671
GROUNDING AND DECOUPLING RULES
Proper grounding and decoupling should be a primary design
objective in any high speed, high resolution system. The
AD1671 separates analog and digital grounds to optimize the
management of analog and digital ground currents in a system.
The AD1671 is designed to minimize the current flowing from
REF COM (Pin 20) by directing the majority of the current
from VCC (+5 V–Pin 28) to VEE (–5 V–Pin 1). Minimizing analog ground currents hence reduces the potential for large ground
voltage drops. This can be especially true in systems that do not
utilize ground planes or wide ground runs. REF COM is also
configured to be code independent, therefore reducing input dependent analog ground voltage drops and errors. Code dependent ground current is diverted to ACOM (Pin 27). Also critical
in any high speed digital design is the use of proper digital
grounding techniques to avoid potential CMOS “ground
bounce.” Figure 3 is provided to assist in the proper layout,
grounding and decoupling techniques.
+5V
SPURIOUS FREE DYNAMIC RANGE – dB
The AD1671’s SFDR performance is ideal for use in communication systems such as high speed modems and digital radios.
The SFDR is better than 84 dB with sample rates up to 1.11 MHz
and increases as the input signal amplitude is attenuated by approximately 3 dB. Note also the SFDR is typically better than
80 dB with input signals attenuated by up to –7 dB.
0.1µF
10µF
–5V
0.1µF
28
VCC
0.1µF
10µF
1
10µF
18
VEE VLOGIC
23 AIN1
–68
+5V
BIT 1 13
AD1671
–70
VIN (±5V)
22 AIN2
BIT 12 2
–72
20 REF COM
–74
–76
27 ACOM
AGP*
–78
–80
DGP*
–82
19 DCOM
DAV 16
25 SHA OUT
–84
OTR 15
–86
26 BPO/UPO
–88
–90
666
ENCODE 17
MSB 14
714
769
833
909
1000
SAMPLING FREQUENCY – kHz
1111
24 REF IN
1250
21 REF OUT
1µF
Figure 6. Spurious Free Dynamic Range vs. Sampling
Rate, fIN = 100 kHz
*GROUND PLANE RECOMMENDED
Figure 8. AD1671 Grounding and Decoupling
–8–
REV. B
AD1671
The gain trim is done by applying a signal 1 1/2 LSBs below the
nominal full scale (4.998 V for a 5 V range). Trim R2 to give
the last transition (1111 1111 1110 to 1111 1111 1111). This
circuit will give approximately ± 0.5% FS of adjustment range.
Table I is a list of grounding and decoupling rules that should
be reviewed before laying out a printed circuit board.
Table I. Grounding and Decoupling Guidelines
Power Supply
Decoupling
Capacitor Values
Capacitor Locations
VIN
0 TO +5V
Comment
0.1 µF (Ceramic) and 1 µF
(Tantalum) Surface Mount Chip
Capacitors Recommended to
Reduce Lead Inductance
25Ω
AIN1
5k
AIN2
5k
SHA
+5V
50k
OFFSET R1
ADJ 10k
–5V
GAIN
ADJ
R2
50Ω
SHA OUT
AD1671
Directly at Positive and Negative
Supply Pins to Common Ground
Plane
BPO/UPO
REF IN
Reference (REF OUT)
Capacitor Value
REF OUT
1µF
1 µF (Tantalum) to ACOM
Figure 9. Unipolar (0 V to +5 V) Calibration
Grounding
Analog Ground
Reference Ground
(REF COM)
Digital Ground
Ground Plane or Wide Ground
Return Connected to the Analog
Power Supply
BIPOLAR (65 V) CALIBRATION
The connections for the bipolar ± 5 V input range is shown in
Figure 10.
Critical Common Connections
Should be Star Connected to REF
COM (as Shown in Figure 8)
VIN
–5V TO +5V
25Ω
AIN1
5k
AIN2
5k
SHA
+5V
Ground Plane or Wide Ground
Return Connected to the Digital
Power Supply
50k
OFFSET R1
ADJ 10k
–5V
GAIN
ADJ
Analog and Digital Ground Connected Together Once at the
AD1671
R2
50Ω
SHA OUT
AD1671
BPO/UPO
REF IN
UNIPOLAR (0 V TO +5 V) CALIBRATION
REF OUT
The AD1671 is factory trimmed to minimize offset, gain and
linearity errors. In some applications the offset and gain errors
of the AD1671 need to be externally adjusted to zero. This is
accomplished by trimming the voltage at AIN2 (Pin 22). The
circuit in Figure 9 is recommended for calibrating offset and
gain errors of the AD1671 when configured in the 0 V to +5 V
input range. If the offset trim resistor R1 is used, it should be
trimmed as follows, although a different offset can be set for a
particular system requirement. This circuit will give approximately ± 5 mV of offset trim range. Nominally the AD1671 is
intended to have a 1/2 LSB offset so that the exact analog input
for a given code will be in the middle of that code (halfway between the transitions to the codes above it and below it). Thus,
the first transition (from 0000 0000 0000 to 0000 0000 0001)
will occur for an input level of +1/2 LSB (0.61 mV for 5 V
range).
REV. B
1µF
Figure 10. Bipolar (± 5 V) Calibration
Bipolar calibration is similar to unipolar calibration. First, a signal 1/2 LSB above negative full scale (–4.9988 V) is applied and
R1 is trimmed to give the first transition (0000 0000 0000 to
0000 0000 0001). Then a signal 1 1/2 LSB below positive full
scale (+4.9963 V) is applied and R2 is trimmed to give the last
transition (1111 1111 1110 to 1111 1111 1111).
–9–
AD1671
UNIPOLAR (0 V TO +2.5 V) CALIBRATION
The connections for the 0 V to +2.5 V input range calibration is
shown in Figure 11. Figure 11 shows an example of how the
offset error can be trimmed in front of the AD1671. The procedure for trimming the offset and gain errors is the same as for
the unipolar 5 V range.
and tSS minimum). To satisfy the requirements of the 574 type
latch the recommended logic families are S, AS, ALS, F or
BCT. New data from the AD1671 is latched on the rising edge
of the DAV (Pin 16) output pulse. Previous data can be latched
by inverting the DAV output with a 7404 type inverter.
74HC574
+15V
390Ω
VIN
0 TO +2.5V
OFFSET ADJ
R1
1kΩ
GAIN R2
ADJ 2k
AIN1
5k
AIN2
5k
AD845
SHA
10k
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
DAV
1D
2D
3D
4D
5D
6D
7D
8D
CLOCK
BIT 9
BIT 10
BIT 11
BIT 12
1D
2D
3D
4D
5D
6D
7D
8D
CLOCK
SHA OUT
10k
AD1671
BPO/UPO
REF IN
AD1671
REF OUT
1µF
BIPOLAR (62.5 V) CALIBRATION
The connections for the bipolar ± 2.5 V input range is shown in
Figure 12.
+15V
390Ω
OFFSET ADJ
R1
1kΩ
GAIN R2
ADJ 2k
AIN1
5k
AIN2
5k
AD845
SHA
10k
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
OC
3-STATE
CONTROL
Figure 13. AD1671 to Output Latches
Figure 11. Unipolar (0 V to +2.5 V) Calibration
VIN
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
OC
74HC574
1k
–2.5V TO +2.5V
DATA BUS
1k
OUT OF RANGE
An out-of-range condition exists when the analog input voltage
is beyond the input range (0 V to +2.5 V, 0 V to +5 V, ± 2.5 V,
± 5 V) of the converter OTR (Pin 15) is set low when the analog
input voltage is within the analog input range. OTR is set HIGH
and will remain HIGH when the analog input voltage exceeds
the input range by typically 1/2 LSB (OTR transition is tested to
± 6 LSBs of accuracy) from the center of the ± full-scale output
codes. OTR will remain HIGH until the analog input is within
the input range and another conversion is completed. By logical
ANDing OTR with the MSB and its complement, overrange
high or underrange low conditions can be detected. Table II is a
truth table for the over/under range circuit in Figure 14. Systems requiring programmable gain conditioning prior to the
AD1671 can immediately detect an out-of-range condition, thus
eliminating gain selection iterations.
SHA OUT
10k
AD1671
Table II. Out-of-Range Truth Table
BPO/UPO
REF IN
REF OUT
1µF
Figure 12. Bipolar (± 2.5 V) Calibration
OUTPUT LATCHES
OTR
MSB
Analog Input Is
0
0
1
1
0
1
0
1
In Range
In Range
Underrange
Overrange
MSB
OVER = "1"
Figure 13 shows the AD1671 connected to the 74HC574 octal
D-type edge-triggered latches with 3-state outputs. The latch
can drive highly capacitive loads (i.e., bus lines, I/O ports) while
maintaining the data signal integrity. The maximum setup and
hold times of the 574 type latch must be less than 20 ns (tDD
OTR
UNDER = "1"
MSB
Figure 14. Overrange or Underrange Logic
–10–
REV. B
AD1671
Table III. Output Data Format
Input
Range
Coding
Analog
Inputl
Digital
Output
OTR2
0 V to +2.5 V
Straight Binary
≤ –0.0003 V
0V
+2.5 V
≥ +2.5003 V
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
1
0
0
1
0 V to +5 V
Straight Binary
≤ –0.0006 V
0V
+5 V
≥ +5.0006 V
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
1
0
0
1
–2.5 V to +2.5 V Offset Binary
≤ –2.5006 V
–2.5 V
+2.5 V
≥ +2.4994 V
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
1
0
0
1
–5 V to +5 V
≤ –5.0012 V
–5 V
+5 V
≥ +4.9988 V
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
1
0
0
1
–2.5 V to +2.5 V Twos Complement ≤ –2.5006 V
(Using MSB)
–2.5 V
+2.5 V
≥ +2.4994 V
1000 0000 0000
1000 0000 0000
0111 1111 1111
0111 1111 1111
1
0
0
1
Twos Complement ≤ –5.0012 V
(Using MSB)
–5 V
+5 V
≥ +4.9988 V
1000 0000 0000
1000 0000 0000
0111 1111 1111
0111 1111 1111
1
0
0
1
–5 V to +5 V
Offset Binary
NOTES
1
Voltages listed are with offset and gain errors adjusted to zero.
2
Typical performance.
OUTPUT DATA FORMAT
ILOGIC VS. CONVERSION RATE
Figure 15 is the typical logic supply current vs. conversion rate
for various capacitor loads on the digital outputs.
6.5
6.0
5.5
5.0
4.5
4.0
mA
The AD1671 provides both MSB and MSB outputs, delivering
data in positive true straight binary for unipolar input ranges
and positive true offset binary or twos complement for bipolar
input ranges. Straight binary coding is used for systems that accept positive-only signals. If straight binary coding is used with
bipolar input signals, a 0 V input would result in a binary output
of 2048. The application software would have to subtract 2048
to determine the true input voltage. Host registers typically perform math on signed integers and assume data is in that format.
Twos complement format minimizes software overhead which is
especially important in high speed data transfers, such as a
DMA operation. The CPU is not bogged down performing data
conversion steps, hence the total system throughput is increased.
connected to +5 V. It is possible to connect REF OUT to +5 V
due to its output circuit implementation which shuts down the
reference.
OPTIONAL EXTERNAL REFERENCE
The AD1671 includes an onboard +2.5 V reference. The reference input pin (REF IN) can be connected to reference output
pin (REF OUT) or a standard external +2.5 V reference can be
selected to meet specific system requirements. Fast switching input dependent currents are modulated at the reference input.
The reference input voltage can be held with the use of a capacitor. To prevent the AD1671’s onboard reference from oscillating when not connected to REF IN, REF OUT must be
REV. B
–11–
3.5
CL = 50pF
3.0
2.5
2.0
CL = 30pF
1.5
CL = 0pF
1.0
0.5
1k
10k
100k
CONVERSION RATE – Hz
Figure 15. ILOGIC vs. Conversion Rate for Various
Capacitive Loads on the Digital Outputs
1M
AD1671
APPLICATIONS
AD1671 TO ADSP-2101/2102
AD1671 TO ADSP-2100A
Figure 17 is identical to the 2100A interface except the sampling clock is used to generate an interrupt (IRQ2) for the processor. Upon interrupt the ADSP-2100A starts a data memory
read by providing an address on the address (A) bus. The decode address generates OE for the D-latches and the processor
reads their output over the Data (D) bus. Reading the conversion result is thus completed within a single processor cycle.
Figure 16 demonstrates the AD1671 to ADSP-2100A interface.
The 2100A with a clock frequency of 12.5 MHz can execute an
instruction in one 80 ns cycle. The AD1671 is configured to
perform continuous time sampling. The DAV output of the
AD1671 is asserted at the end of each conversion. DAV can be
used to latch the conversion result into the two 574 octal
D-latches. The falling edge of the sampling clock is used to
generate an interrupt (IRQ3) for the processor. Upon interrupt,
the ADSP-2100A starts a data memory read by providing an
address on the DMA bus. The decoded address generates OE
for the latches and the processor reads their output over the
DMA bus. The conversion result is read within a single processor cycle.
RD
A0:13
574
8
Q0:7
ADSP-2101
8
DECODE
OE
DMA0:13 ADDRESS BUS
8
OE
DAV
DECODE
Q0:7
D0:7
DMA0:15
IRQ3
BIT1:12
574
DATA BUS
+5V
AD1671
IRQ2
OE
8
DMACK
8
SAMPLING
CLOCK
4
D0:3
8
D0:7
16
BIT1:12
574
DATA BUS
574
Q0:7
ADSP2100A
D0:15
AD1671
D0:7
16
DMRD
DAV
OE
ADDRESS BUS
4
ENCODE
Figure 17. AD1671 to ADSP-2101/ADSP-2102 Interface
4
D0:3
Q0:7
4
D0:7
SAMPLING
CLOCK
ENCODE
Figure 16. AD1671 to ADSP-2100A Interface
–12–
REV. B
AD1671
COMPONENT LIST
Parts List
Reference Designator
R1, R2
R3, R4, R5
R6
R7
R8
R9, R11
R10
R12
R13
R14
R15–R28
C1, C3, C5
C2, C4, C6, C8, C10
C7, C9, C15, C16
C11, C12, C13, C14, C17
C18
C19–C22
C23
C24
U1
U2
U3
U4–U5
U6
W1–W3
J1–J15
Type
Description
Resistor, 5%, 0.5 W, 100 Ω
Resistor, 1%, 49.9 Ω
100 Ω Trim Potentiometer
Resistor 1%, 4.99 kΩ Optional
X Ω Trim Potentiometer, Optional
Resistor, 1%, 4.99 kΩ
Resistor, 1%, 10 kΩ
Resistor, 1%, 2.49 kΩ
Resistor, 1%, 787 Ω
Resistor, 1%, 249 Ω
Resistor, 5%, 22 Ω
Cap, Tantalum, 22 µF
Cap, Ceramic, 0.01 µF
Cap, Tantalum, 10 µF
Cap, Ceramic, 0.1 µF
Cap, Ceramic, 1.0 µF
Cap, Ceramic, 0.1 µF
Cap, Mica, 100 pF
Cap, Ceramic, 0.001 µF
78L05 +5 V Regulator
79L05 –5 V Regulator
AD1671
74HC573 Drivers
AD568
BNC Jacks
Jumpers and Headers
Metal Binding Posts
Wide 28-Pin Socket
Narrow 20-Pin Socket
Narrow 24-Pin Socket
SECMA SPDT Switch
Test Point, Red
Test Point, Black
Test Point, White
40-Pin Connector Male + Hooks
S1
S2
S3
SW1–SW3
TP1, TP2, TP4–TP6
TP3, TP7, TP10, TP13
TP8, TP9, TP11, TP12, TP14
P1
REV. B
–13–
AD1671
Figure 18. AD1671/EB PCB Layout—Silkscreen Layer
–14–
REV. B
AD1671
Figure 19. AD1671/EB PCB Layout—Component Side
Figure 20. AD1671/EB PCB Layout—Solder Side
REV. B
–15–
AD1671
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C1616a–10–10/93
28-Lead PLCC (P-28A) Package
PRINTED IN U.S.A.
28-Pin Cerdip (Q-28) Package
–16–
REV. B
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