Intersil ISL59885ISZR5218 Auto-adjusting sync separator for hd and sd video Datasheet

ISL59885
®
Data Sheet
August 9, 2006
Auto-Adjusting Sync Separator for HD
and SD Video
The ISL59885 video sync separator is manufactured using
high performance analog CMOS process. This device
extracts ISL59885 sync timing information from both
standard and non-standard video input in the presence of
Macrovision pulses. It provides composite sync, vertical
sync, SD and HDTV detection, and horizontal sync outputs.
Fixed 70mV sync tip slicing provides sync edge detection
when the video input level is between 0.5VP-P and 2VP-P.
Timing is adjusted automatically for various video standards.
The composite sync output follows sync pulses and a
vertical sync pulse is output on the rising edge of the first
vertical serration following the vertical pre-equalizing string.
For non-standard vertical inputs, a default vertical pulse is
output when the vertical signal stays low for longer than the
vertical sync default delay time. The horizontal output gives
horizontal timing with pre/post equalizing pulses. ISL59885
has an auto input frequency detect feature that sets the right
timing for any input format.
The ISL59885 is available in an 8 Ld SO package and is
specified for operation over the full -40°C to +85°C
temperature range.
FN7442.5
Features
• NTSC, PAL, SECAM, HDTV, non-standard video sync
separation
• Fixed 70mV slicing of video input levels from 0.5VP-P to
2VP-P
• Single 3V to 5V supply
• Composite sync output
• Vertical output
• Horizontal output
• HDTV detection
• 81% to 90% Hsync blanking window (R5218)
• 70% to 90% Hsync blanking window (R5260)
• Macrovision compatible
• Available in 8 Ld SO package
• Pb-Free plus anneal available (RoHS compliant)
Applications
• High definition video equipment
Demo Board
Pinout
• A dedicated demo board is available
ISL59885
(8 LD SO)
TOP VIEW
COMPOSITE SYNC OUT 1
8 VDD
COMPOSITE VIDEO IN 2
7 HORIZONTAL OUTPUT
VERTICAL SYNC OUT 3
6 CSET
GND 4
5 HD
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005, 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59885
Ordering Information
PART
NUMBER
PART MARKING
PACKAGE
TAPE & REEL
PKG. DWG. #
ISL59885IS
59885IS
8 Ld SO
-
MDP0027
ISL59885IS-T7
59885IS
8 Ld SO
7”
MDP0027
ISL59885IS-T13
59885IS
8 Ld SO
13”
MDP0027
ISL59885ISZ (Note)
59885ISZ
8 Ld SO (Pb-Free)
-
MDP0027
ISL59885ISZ-T7 (Note)
59885ISZ
8 Ld SO (Pb-Free)
7”
MDP0027
ISL59885ISZ-T13 (Note)
59885ISZ
8 Ld SO (Pb-Free)
13”
MDP0027
ISL59885ISR5218
59885IS
8 Ld SO
-
MDP0027
ISL59885ISZR5218 (Note)
59885ISZ
8 Ld SO (Pb-Free)
-
MDP0027
ISL59885IS-T7R5218
59885IS
8 Ld SO
7”
MDP0027
ISL59885ISZ-T7R5218 (Note)
59885ISZ
8 Ld SO (Pb-Free)
7”
MDP0027
ISL59885IS-T13R5218
59885IS
8 Ld SO
13”
MDP0027
ISL59885ISZ-T13R5218 (Note)
59885ISZ
8 Ld SO (Pb-Free)
13”
MDP0027
ISL59885ISZR5260 (Note)
59885ISZ
8 Ld SO (Pb-Free)
-
MDP0027
ISL59885ISZ-T7R5260 (Note)
59885ISZ
8 Ld SO (Pb-Free)
7”
MDP0027
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN7442.5
August 9, 2006
ISL59885
Absolute Maximum Ratings (TA = 25°C)
VDD Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified
temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
VDD = 3.3V, TA = 25°C, CSET = 56nF, unless otherwise specified.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
IDD, Quiescent
VDD = 3.3V
1.5
2.2
4
mA
Clamp Voltage
Pin 2, ILOAD = -100µA
1.35
1.5
1.65
V
Clamp Discharge Current
Pin 2 = 2V
6
15
30
µA
Clamp Charge Current
Pin 2 = 1V
-9
-7.2
-5.2
mA
VOL Output Low Voltage
IOL = 1.6mA
0.24
0.5
V
VOH Output High Voltage
IOH = -40µA
3
3.2
V
IOH = -1.6mA
2.5
3.0
V
MIN
TYP
MAX
UNIT
Dynamic Characteristics
PARAMETER
DESCRIPTION
Comp Sync Prop Delay, tCS
See Figure 9
35
75
ns
Horizontal Sync Delay, tHS
See Figure 9
40
80
ns
Horizontal Sync Width, tHS-PW
See Figure 9
3.8
5.2
6.2
µs
Vertical Sync Width, tVS
Normal or default trigger, 50% - 50%, see
Figure 7
230
280
350
µs
Vertical Sync Default Delay, tVSD
See Figure 10
28
50
68
µs
Hsync Blanking Window
ISL59885IS-R5218 only
81
85
90
%
ISL59885ISZ-R5260 only
70
80
90
%
Input Dynamic Range
Video input amplitude to maintain slice level
spec, VDD = 3.3V
0.5
2
VP-P
Slice Level
VSLICE above VCLAMP
50
90
mV
HD Pin Level
720p, 1080i, 1080p
3
70
0
V
FN7442.5
August 9, 2006
ISL59885
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
1
COMPOSITE
SYNC OUT
Composite sync pulse output; sync pulses start on a falling edge and end on a rising edge
2
COMPOSITE
VIDEO IN
AC coupled composite video input; sync tip must be at the lowest potential (positive picture phase)
3
VERTICAL
SYNC OUT
4
GND
5
HD
6
CSET
7
HORIZONTAL
OUTPUT
8
VDD
Vertical sync pulse output; the falling edge of vert sync is the start of the vertical period
Supply ground
Low when input horizontal frequency is greater than 20kHz
(An external capacitor to ground); bypass pin for internal bias generator.
Horizontal output; falling edge active
Positive supply
Typical Performance Curves
VDD=3.3 & 5.0V
VCSET (V)
HSYNC PULSEWIDTH (ns)
VDD=3.3 & 5.0V
HSYNC (kHz)
HSYNC FREQUENCY (kHZ)
FIGURE 1. HSYNC vs VCSET (RSET = OPEN)
FIGURE 2. HSYNC PULSEWIDTH vs HSYNC FREQUENCY
(RSET = OPEN)
HSYNC BLANKING TIME (µs)
VDD=3.3 & 5.0V
VIN
0.5V/DIV
5V/DIV
HSYNC
5V/DIV
VSYNC
5V/DIV
CSYNC
100µs/DIV
VCSET (V)
FIGURE 3. HSYNC vs VCSET (RSET = OPEN)
4
FIGURE 4. MACROVISION COMPATIBILITY (NTSC)
FN7442.5
August 9, 2006
ISL59885
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.8
1.2
POWER DISSIPATION (W)
POWER DISSIPATION (W)
1.6
1.4
1.2 1.136W
1
θJ
A =1
0.8
SO
8
10
°C
0.6
/W
0.4
1
781mW
0.8
θJ
0.6
0.4
A =1
SO
8
60
°C
/W
0.2
0.2
0
0
0
25
50
75 85 100
125
150
0
25
TEMPERATURE (°C)
50
75 85 100
125
150
TEMPERATURE (°C)
FIGURE 5. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 6. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
SIGNAL 1a. COMPOSITE VIDEO INPUT, FIELD ONE
1.5µs ±0.1µs
TIME
VERTICAL BLANKING INTERVAL = 20H
3H
1
START OF
FIELD ONE
H SYNC
INTERVAL
H
3H
3H
2
3
4
H
H
PRE-EQUALIZING
PULSE INTERVAL
+63.5µs
+H
1271µs
-0µs
-H
5
6
7
8
9
0.5H
VERTICAL SYNC
PULSE INTERVAL
10
19
20
21
H
POST-EQUALIZING
PULSE INTERVAL
9 LINE VERTICAL INTERVAL
REF SUBCARRIER PHASE,
COLOR FIELD ONE
SIGNAL 1b. COMPOSITE SYNC OUTPUT, PIN 1
SIGNAL 1c. VERTICAL SYNC OUTPUT, PIN 3
tVS
SIGNAL 1d. HORIZONTAL SYNC OUTPUT, PIN 7
NOTES:
b. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay.
d. Horizontal sync output produces the true “H” pulses of nominal width of 5µs. It has the same delay as the composite sync.
FIGURE 7. TIMING DIAGRAM
5
FN7442.5
August 9, 2006
ISL59885
CONDITIONS: VDD = 3.3V/5V, TA = 25°C
WHITE LEVEL
COLOR BURST
INPUT
DYNAMIC
RANGE
0.5V-2V
VIDEO
SYNC LEVEL
SYNC IN
VSLICE
50%
SYNC
TIP
VBLANK
(BLANKING LEVEL
VOLTAGE)
SYNC
VSYNC
(SYNC TIP
VOLTAGE)
tdSYNCOUT
DEPENDS ON WIDTH OF INPUT SYNC AT 50% LEVEL
SYNC OUT
tdHOUT
HOUT
THOUT
FIGURE 8. HORIZONTAL INTERVAL 525/625 LINE COMPOSITE
PARAMETER
DESCRIPTION
CONDITIONS
TYP
(Note 1)
UNIT
tdSYNCOUT
SYNCOUT Timing Relative to Input
See Figure 8
65
ns
tdHOUT
HOUT Timing Relative to Input
See Figure 8
470
ns
THOUT
Horizontal Output Width
See Figure 8
5.2
us
NOTE:
1. Delay variation is less than 2.5ns over temperature range.
6
FN7442.5
August 9, 2006
ISL59885
SIGNAL 2a.
COMPOSITE
VIDEO INPUT
SLICE LEVEL
70mV
tCS COMP SYNC
PROP DELAY
SIGNAL 2b.
COMPOSITE
SYNC OUTPUT
tCS-VS COMP SYNC VERT SYNC DELAY
SIGNAL 2c.
VERTICAL
SYNC OUTPUT
SIGNAL 2d.
HORIZONTAL
SYNC OUTPUT
tHS
tHS-PW
FIGURE 9. STANDARD VERTICAL TIMING
LINES
2
SIGNAL 3a.
COMPOSITE
VIDEO INPUT
3
4
5
(NO VERTICAL SYNC PULSES)
tVSD
VERT SYNC
DEFAULT DELAY
SIGNAL 3b.
VERTICAL
SYNC OUTPUT
FIGURE 10. NON-STANDARD VERTICAL TIMING
7
FN7442.5
August 9, 2006
ISL59885
COMPOSITE VIDEO INPUT, BEGINNING OF FIELD ONE
START OF FIELD ONE
622
623
624
625
1
2
3
4
5
6
7
23
24
SYNCOUT OUTPUT
VOUT OUTPUT
TVS
HOUT OUTPUT
NOTES:
b. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay.
FIGURE 11. EXAMPLE OF VERTICAL INTERVAL (625)
SYNCIN
1123
1124
1125
560
561
562
1
2
3
564
565
4
5
6
567
568
7
8 ...
21
569
570 ... 583
SYNCOUT
HOUT
VOUT
SYNCIN
563
566
SYNCOUT
HOUT
VOUT
FIGURE 12. EXAMPLE OF HDTV 1080I/30 LINE COMPOSITE VIDEO: INTERLACED
8
FN7442.5
August 9, 2006
ISL59885
SYNCIN
1245
1246
1247
1248
1249
1250
620
621
622
623
624
625
1
2
3
4
5 ...
48
SYNCOUT
HOUT
VOUT
SYNCIN
626
627
628
629
630 ... 673
SYNCOUT
HOUT
VOUT
FIGURE 13. HDTV 1080I/25 LINE COMPOSITE VIDEO: INTERLACED (1250 LINES)
9
FN7442.5
August 9, 2006
ISL59885
CONDITIONS: VDD = 3.3V/5V, TA = 25°C
SYNCIN
tdSYNCOUT
SYNC OUT
tdHOUT
HOUT
THOUT
FIGURE 14. HORIZONTAL INTERVAL (HDTV) (720p)
H Timing for HDTV, No Filter (using 720p input signal)
PARAMETER
DESCRIPTION
CONDITIONS
TYP
TYP
@ 5V
@ 3.3V
(Note 1) (Note 1)
UNIT
tdSYNCOUT
SYNCOUT Timing Relative to Input
See Figure 14
56
50
ns
tdHOUT
HOUT Timing Relative to Input
See Figure 14
48
36
ns
THOUT
Horizontal Output Width
See Figure 14
1.90
1.90
us
NOTE:
1. Delay variation is less than 2.5ns over temperature range.
10
FN7442.5
August 9, 2006
ISL59885
CONDITIONS: VDD = 3.3V/5V, TA = 25°C
SYNCIN
tdSYNCOUT
SYNC OUT
tdHOUT
HOUT
THOUT
FIGURE 15. HORIZONTAL INTERVAL (HDTV) (720p)
H Timing for HDTV, With Filter (using 720p input)
PARAMETER
DESCRIPTION
CONDITIONS
TYP
TYP
@ 5V
@ 3.3V
(Note 1) (Note 1)
UNIT
tdSYNCOUT
SYNCOUT Timing Relative to Input
See Figure 15
120
110
ns
tdHOUT
HOUT Timing Relative to Input
See Figure 15
112
100
ns
THOUT
Horizontal Output Width
See Figure 15
200
200
ns
NOTE:
1. Delay variation is less than 2.5ns over temperature range.
11
FN7442.5
August 9, 2006
ISL59885
Applications Information
Video In
A simplified block diagram is shown following page.
An AC coupled video signal is input to Video In pin 2 via C1,
nominally 0.1µF. Clamp charge current will prevent the
signal on pin 2 from going any more negative than Sync Tip
Ref, about 1.5V. This charge current is nominally about 1mA.
A clamp discharge current of about 10µA is always
attempting to discharge C1 to Sync Tip Ref, thus charge is
lost between sync pulses that must be replaced during sync
pulses. The droop voltage that will occur can be calculated
from IT = CV, where V is the droop voltage, I is the discharge
current, T is the time between sync pulses (sync period sync tip width), and C is C1.
An NTSC video signal has a horizontal frequency of
15.73kHz, and a sync tip width of 4.7µs. This gives a period
of 63.6µs and a time T = 58.9µs. The droop voltage will then
be V = 5.9mV. This is less than 2% of a nominal sync tip
amplitude of 286mV. The charge represented by this droop
is replaced in a time given by T = CV/I, where I = clamp
charge current = 5.3mA. Here T = 590ns, about 12% of the
sync pulse width of 4.7µs. It is important to choose C1 large
enough so that the droop voltage does not approach the
switching threshold of the internal comparator.
Composite Sync
The Composite Sync output is simply a reproduction of the
input signal with the active video removed. The sync tip of
the Composite video signal is clamped to 1.5V at pin 2 and
then slices at 70mV above the sync tip reference. The output
signal is buffered out to pin 1. When loss of sync, the
Composite Sync output is held low.
present on the I/P signal after the true H sync will be ignored,
thus the horizontal output will not be affected by MacroVision
copy protection. When loss of sync, the Horizontal Sync
output is held high.
CSET
An external CSET capacitor connected from CSET pin 6 to
ground. CSET capacitor should be a X7R grade or better as
the Y5U general use capacitors may be too leaky and cause
faulty operation. The CSET capacitor should be very close to
the CSET pin to reduce possible board leakage. 56nF is
recommended. CSET simplified block diagram is shown in
diagram 5. The CSET capacitor rectifies 5us pulse current
and creates a voltage on CSET. The CSET voltage is
converted to bias current for HSYNC and VSYNC timing.
Chroma Filter
A chroma filter is suggested to increase the S/N ratio of the
incoming video signal. Use of the optional chroma filter is
shown in the figure below. It can be implemented very simply
and inexpensively with a series resistor of 100Ω and a
capacitor of 570pF, which gives a single pole roll-off
frequency of about 2.79MHz during NTSC or PAL. This
sufficiently attenuates the 3.58MHz (NTSC) or 4.43MHz
(PAL) color burst signal, yet passes the approximately 15kHz
sync signals without appreciable attenuation. During HDTV,
the transistor turns off and a 100pF capacitor is left to filter
any noise present at the input. A chroma filter will increase
the propagation delay from the composite input to the
outputs.
ISL59885
CHROMA FILTER
VIDEO IN
RF
0.1µF
1 CSYNC VDD
8
2
HOUT
7
3 VSYNC CSET
6
4
5
CVIN
100Ω
Vertical Sync
A low-going Vertical Sync pulse is output during the start of
the vertical cycle of the incoming video signal. The vertical
cycle starts with a pre-equalizing phase of pulses with a duty
cycle of about 93%, followed by a vertical serration phase
that has a duty cycle of about 15%. Vertical Sync is clocked
out of the ISL59885 on the first rising edge during the
vertical serration phase. In the absence of vertical serration
pulses, a vertical sync pulse will be forced out after the
vertical sync default delay time, approximately 60µs after the
last falling edge of the vertical equalizing phase.
Horizontal Sync
CF
100pF
CF2
470pF
GND
HD
10kΩ
MMBT3904
HD-Detect
High definition video is flagged by HD going low when the
input horizontal frequency is greater than 20kHz.
The horizontal circuit senses the composite sync edges and
produces the true horizontal pulses of nominal width 5.2µs.
The leading edge is triggered from the leading edge of the
input H sync, with the same propagation delay as composite
sync. The half line pulses present in the input signal during
vertical blanking are removed with an internal 2H line
eliminator circuit. This is a circuit that inhibits horizontal
output pulses until 75% of the line time is reached, then the
horizontal output operation is enabled again. Any signals
12
FN7442.5
August 9, 2006
ISL59885
Simplified Block Diagram
CLAMP
SYNC TIP REF
1.5V
C1
RF
620Ω
CF
510pF
VDD
8
VDD
5V
C2
0.1µF
COMPOSITE
VIDEO IN
2
SLICE
1.57V
0.1µF
COMP.
+
1 COMPOSITE
SYNC
GND 4
CSET
C3
56nF
6
REF
GEN
SYNC
TIP
70mV
SLICE
HD
DETECTOR
5 HD
V SYNC
3 VERTICAL
SYNC OUT
H SYNC
7 HORIZONTAL
SYNC OUT
2H
ELIMINATOR
CSET Bias Circuit
VDD
CSYNC
PULSE
5µs
VDD
CSET
56nF
13
+
IBIAS - TIMING
FN7442.5
August 9, 2006
ISL59885
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
SO-8
SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
N
8
14
16
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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14
FN7442.5
August 9, 2006
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