ON MC100EP11DT 3.3v / 5v ecl 1:2 differential fanout buffer Datasheet

MC10EP11, MC100EP11
3.3V / 5VECL 1:2
Differential Fanout Buffer
The MC10/100EP11 is a differential 1:2 fanout buffer. The device is
pin and functionally equivalent to the LVEL11 device. With AC
performance much faster than the LVEL11 device, the EP11 is ideal
for applications requiring the fastest AC performance available.
The 100 Series contains temperature compensation.
• 220 ps Typical Propagation Delay
• Maximum Clock Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
•
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MARKING DIAGRAMS*
8
8
8
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −5.5 V
Open Input Default State
1
SO−8
D SUFFIX
CASE 751
•
• Safety Clamp on Inputs
• Q Outputs Will Default LOW with Inputs Open or at VEE
HEP11
ALYW
KEP11
ALYW
1
1
8
8
8
1
TSSOP−8
DT SUFFIX
CASE 948R
HP11
ALYW
1
H = MC10
K = MC100
A = Assembly Location
KP11
ALYW
1
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Package
Shipping†
MC10EP11D
SO−8
98 Units/Rail
MC10EP11DR2
SO−8
2500 Tape & Reel
MC100EP11D
SO−8
98 Units/Rail
MC100EP11DR2
SO−8
2500 Tape & Reel
MC10EP11DT
TSSOP−8
100 Units/Rail
MC10EP11DTR2
TSSOP−8
2500 Tape & Reel
MC100EP11DT
TSSOP−8
100 Units/Rail
MC100EP11DTR2
TSSOP−8
2500 Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
 Semiconductor Components Industries, LLC, 2003
November, 2003 − Rev. 6
1
Publication Order Number:
MC10EP11/D
MC10EP11, MC100EP11
Q0
Q0
1
8
2
PIN DESCRIPTION
VCC
7
D
R1
Q1
R2
3
6
D
5
VEE
PIN
FUNCTION
D*, D**
ECL Data Inputs
Q0, Q0, Q1, Q1
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
** Pins will default to high when left open.
R1
Q1
4
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
R1
75 k
Internal Input Pullup Resistor
R2
37.5 k
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
ESD Protection
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
73
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
−6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
JA
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case)
std bd
8 SOIC
41 to 44
°C/W
JA
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case)
std bd
8 TSSOP
41 to 44
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
2. Maximum Ratings are those values beyond which device damage may occur.
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2
VI VCC
VI VEE
MC10EP11, MC100EP11
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
−40°C
Typ
25°C
Max
Min
Typ
85°C
Symbol
IEE
Characteristic
Negative Power Supply Current
Min
20
29
37
20
30
39
22
VOH
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
VIH
Input HIGH Voltage (Single−Ended)
2090
2415
2155
2480
VIL
Input LOW Voltage (Single−Ended)
1365
1690
1430
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 5)
2.0
3.3
2.0
IIH
Input HIGH Current
IIL
Input LOW Current
150
D
D
0.5
−150
Max
Min
Typ
Max
Unit
31
40
mA
2415
2540
mV
1740
mV
2215
2540
mV
1755
1490
1815
mV
3.3
2.0
3.3
V
150
A
150
0.5
−150
A
0.5
−150
NOTE:
EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
4. All loading with 50 to VCC − 2.0 V.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
−40°C
25°C
85°C
Symbol
IEE
Characteristic
Negative Power Supply Current
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
20
29
37
20
30
39
22
31
40
Unit
mA
VOH
Output HIGH Voltage (Note 7)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single−Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single−Ended)
3065
3390
3130
3455
3190
3515
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 8)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
150
D
D
0.5
−150
150
0.5
−150
A
0.5
−150
NOTE:
EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.
7. All loading with 50 to VCC − 2.0 V.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 9)
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
20
29
37
20
30
39
22
31
40
Unit
mA
Output HIGH Voltage (Note 10)
−1135
−1010
−885
−1070
−945
−820
−1010
−885
−760
mV
Output LOW Voltage (Note 10)
−1935
−1810
−1685
−1870
−1745
−1620
−1810
−1685
−1560
mV
VIH
Input HIGH Voltage (Single−Ended)
−1210
−885
−1145
−820
−1085
−760
mV
VIL
Input LOW Voltage (Single−Ended)
−1935
−1610
−1870
−1545
−1810
−1485
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 11)
0.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
Symbol
IEE
Characteristic
Negative Power Supply Current
VOH
VOL
VEE+2.0
0.0
VEE+2.0
150
D
D
0.5
−150
VEE+2.0
150
0.5
−150
NOTE:
0.0
0.5
−150
A
EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC − 2.0 V.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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3
MC10EP11, MC100EP11
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
−40°C
25°C
85°C
Symbol
IEE
Characteristic
Negative Power Supply Current
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
26
35
44
26
35
44
26
35
46
Unit
mA
VOH
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single−Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1355
1675
1355
1675
1355
1675
mV
VIHCMR
Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 14)
2.0
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
150
D
D
0.5
−150
150
0.5
−150
A
0.5
−150
NOTE:
EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
13. All loading with 50 to VCC − 2.0 V.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
−40°C
25°C
85°C
Symbol
IEE
Characteristic
Negative Power Supply Current
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
26
35
44
26
35
44
26
35
46
Unit
mA
VOH
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single−Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single−Ended)
3055
3375
3055
3375
3055
3375
mV
VIHCMR
Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 17)
2.0
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
150
D
D
0.5
−150
150
0.5
−150
A
0.5
−150
NOTE:
EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.
16. All loading with 50 to VCC − 2.0 V.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 18)
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
26
35
44
26
35
44
26
35
46
Unit
mA
Output HIGH Voltage (Note 19)
−1145
−1020
−895
−1145
−1020
−895
−1145
−1020
−895
mV
Output LOW Voltage (Note 19)
−1945
−1820
−1695
−1945
−1820
−1695
−1945
−1820
−1695
mV
VIH
Input HIGH Voltage (Single−Ended)
−1225
−880
−1225
−880
−1225
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1945
−1625
−1945
−1625
−1945
−1625
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
0.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
Symbol
IEE
Characteristic
Negative Power Supply Current
VOH
VOL
VEE+2.0
0.0
VEE+2.0
150
D
D
0.5
−150
VEE+2.0
150
0.5
−150
NOTE:
0.0
0.5
−150
A
EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 to VCC − 2.0 V.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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4
MC10EP11, MC100EP11
AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
−40°C
Symbol
Min
Characteristic
fmax
Maximum Frequency
(See Figure 2)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Typ
25°C
Max
Min
>3
Typ
85°C
Max
Min
Typ
>3
Max
>3
Unit
GHz
ps
CLK to Q, Q
200
250
Within Device Skew
Q0, Q1 (Note 22)
Device−to−Device Skew
10
tJITTER
Random Clock Jitter (RMS)
(See Figure 2)
VINPP
Input Voltage Swing Sensitivity
(Differential Configuration)
tr
tf
Output Rise/Fall Times
(20% − 80%) @ 1.0 GHz
Q, Q
140
160
220
270
15
110
15
0.2
<1
150
800
1200
70
120
170
180
240
300
20
110
20
25
120
ps
0.2
<1
0.2
<1
ps
150
800
1200
150
800
1200
mV
80
130
180
90
150
200
ps
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
100
1
JITTEROUT ps (RMS)
OUTPUT VOLTAGE AMPLITUDE (mV)
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC − 2.0 V.
22. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
ÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
0
0
1000
2000
3000
INPUT FREQUENCY (MHz)
Figure 2. Output Voltage Amplitude (VOUTPP) RMS Jitter vs. Input Clock Frequency at Ambient Temperature
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5
MC10EP11, MC100EP11
D
VINPP = VIH(CLK) − VIL(CLK)
D
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPLH
tPHL
Figure 3. AC Reference Measurement
Z0 = 50 Q
D
Receiver
Device
Driver
Device
Z0 = 50 Q
D
50 50 V TT
V TT = V CC − 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 − Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
−
ECLinPS Circuit Performance at Non−Standard VIH Levels
AN1405
−
ECL Clock Distribution Techniques
AN1406
−
Designing with PECL (ECL at +5.0 V)
AN1504
−
Metastability and the ECLinPS Family
AN1568
−
Interfacing Between LVDS and ECL
AN1650
−
Using Wire−OR Ties in ECLinPS Designs
AN1672
−
The ECL Translator Guide
AND8001
−
Odd Number Counters Design
AND8002
−
Marking and Date Codes
AND8009
−
ECLinPS Plus Spice I/O Model Kit
AND8020
−
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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6
MC10EP11, MC100EP11
PACKAGE DIMENSIONS
SO−8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751−07
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
X
S
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
8
0.010
0.020
0.228
0.244
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x
0.15 (0.006) T U
K REF
0.10 (0.004)
S
2X
L/2
8
1
PIN 1
IDENT
S
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
5
0.25 (0.010)
B
−U−
L
0.15 (0.006) T U
M
M
4
A
−V−
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
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7
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0
6
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0
6
MC10EP11, MC100EP11
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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MC10EP11/D
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