MOTOROLA DSP56156FE60

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MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
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16-bit Digital Signal Processor
The DSP56156 is a general-purpose MPU-style Digital Signal Processor (DSP). On a single semiconductor chip, the DSP56156 comprises a very efficient 16-bit digital signal processing core, program and data memories, a number of peripherals, and system support circuitry. Unique features
of the DSP56156 include a built-in sigma-delta (²ý) codec and phase-locked loop (PLL). This combination of features makes the DSP56156 a cost-effective, high-performance solution for many DSP
applications, especially speech coding, digital communications, and cellular base stations.
The central processing unit of the DSP56156 is the DSP56100 core processor. Like all DSP56100based DSPs, the DSP56156 consists of three execution units operating in parallel, allowing up to
six operations to be performed during each instruction cycle. This parallelism greatly increases the
effective processing speed of the DSP56156. The MPU-style programming model and instruction
set allow straightforward generation of efficient, compact code. The basic architectures and development tools of Motorola's 16-bit, 24-bit, and 32-bit DSPs are so similar that understanding how to
design and program one greatly reduces the time needed to learn the others.
On-Chip Emulation (OnCETM port) circuitry provides convenient and inexpensive debug facilities normally available only through expensive external hardware. Development costs are reduced and in-field testing is greatly simplified using the OnCETM port. Figure 1 illustrates the
DSP56156 in detail.
16-bit Bus
7
2
SigmaDelta
Codec
16-bit
Timer/
Event
Counter
5
15
Sync.
Serial
(SSI)
or I/O
Host
Interface
(HI)
or I/O
5
Sync.
Serial
(SSI)
or I/O
Program
Memory *
2048 × 16 RAM
Data
Memory
2048 × 16 RAM
64 × 16 ROM
(boot)
16-bit
56100 DSP
Core
PAB
XAB1
Address
Generation
Unit
XAB2
GDB
PDB
Internal
Data
Bus
Switch
External
Address
Bus
Switch
External
Data
Bus
Switch
XDB
OnCE™ Port
3
Program
Decode
Controller
Interrupt
Control
Clock
PLL Gen.
Program
Address
Generator
Program Control Unit
4 IRQ
2
Data ALU
16 x 16 + 40 —> 40-bit MAC
Two 40-bit Accumulators
16
Data
16
Control
9
* 12 k x 16 ROM replaces the program RAM on the DSP56156ROM
Figure 1 DSP56156 Block Diagram
Specifications and information herein are subject to change without notice.
OnCE is a trademark of Motorola, Inc.
 MOTOROLA INC., 1994
Bus
Control
Address
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Introduction
DSP56156 Features
DSP56156 Features
Digital Signal Processing Core
• Efficient, object code compatible, 16-bit 56100-Family DSP engine
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—
—
—
—
—
—
—
—
—
—
—
—
—
Up to 30 Million Instructions Per Second (MIPS) – 33 ns instruction cycle at 60 MHz
Up to 180 Million Operations Per Second (MOPS) at 60 MHz
Highly parallel instruction set with unique DSP addressing modes
Two 40-bit accumulators including extension byte
Parallel 16 × 16-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
Double precision 32 × 32-bit multiply with 72-bit result in 6 instruction cycles
Least Mean Square (LMS) adaptive loop filter in 2 instructions
40-bit Addition/Subtraction in 1 instruction cycle
Fractional and integer arithmetic with support for multiprecision arithmetic
Hardware support for block-floating point FFT
Hardware-nested DO loops including infinite loops
Zero-overhead fast interrupts (2 instruction cycles)
Three 16-bit internal data buses and three 16-bit internal address buses for
maximum information transfer on-chip
Memory
• On-chip Harvard architecture permitting simultaneous accesses to program
and memories
• 2048 × 16-bit on-chip program RAM and 64 × 16-bit bootstrap ROM
(or 12 k × 16-bit on-chip program ROM on the DSP56156ROM)
• 2048 × 16-bit on-chip data RAM
• External memory expansion with 16-bit address and data buses
• Bootstrap loading from external data bus, Host Interface, or
Synchronous Serial Interface
Peripheral and Support Circuits
• Byte-wide Host Interface (HI) with Direct Memory Access support
• Two Synchronous Serial Interfaces (SSI) to communicate with codecs and
synchronous serial devices
— Built in µ-law and A-law compression/expansion
— Up to 32 software-selectable time slots in network mode
• 16-bit Timer/Event Counter also generates and measures digital waveforms
• On-chip sigma-delta voice band Codec:
—
—
—
—
2
Sampling clock rates between 100 kHz and 3 MHz
Four software-programmable decimation/interpolation ratios
Internal voltage reference ( 2/5 of positive power supply)
No external components required
DSP56156 Data Sheet
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Introduction
DSP56156 Features
Documentation
• On-chip peripheral registers memory mapped in data memory space
• Double buffered peripherals
• Up to 27 general purpose I/O pins
• Two external interrupt request pins
• On-Chip Emulation (OnCE™) port for unobtrusive, processor speed-independent
debugging
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• Software-programmable, Phase-Locked Loop-based (PLL) frequency synthesizer for the
core clock
Miscellaneous Features
• Power-saving Wait and Stop modes
• Fully static, HCMOS design for operating frequencies from 40 or 60 MHz down to DC
• 112-pin Ceramic Quad Flat Pack (CQFP) surface-mount package; 20 × 20 × 3 mm
• 112-pin Plastic Thin Quad Flat Pack (TQFP) surface-mount package; 20 × 20 × 1.5 mm
• 5 V power supply
Product Documentation
This data sheet plus the two manuals listed in Table 1 are required for a complete DSP56156
description and are necessary to properly design with the part. Documentation is available
from a local Motorola distributor, a semiconductor sales office, or through a Motorola Literature Distribution Center.
Table 1 DSP56156 Documentation
Topic
Description
Order Number
DSP56100 Family Manual
Detailed description of the 56000family architecture and the 16-bit core
processor and instruction set
DSP56100FAMUM/AD
DSP56156 User’s Manual
Detailed description of memory,
peripherals, and interfaces
DSP56156UM/AD
DSP56156 Data Sheet
Pin and package descriptions, and
electrical and timing specifications
DSP56156/D
MOTOROLA
DSP56156 Data Sheet
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Introduction
Documentation
Data Sheet Contents
Related Documentation
Table 2 lists additional documentation relevant to the DSP56156.
Table 2 Related Motorola Documentation
Freescale Semiconductor, Inc...
Topic
Description
Order Number
DSP Family Brochure
Overview of all DSP product families
BR1105/D
Development Tools
Product Brief. Includes ordering
information
DSPTOOLSP/D
Fractional and Integer Arithmetic
Application Report. Includes code
APR3/D
Fast Fourier Transforms (FFTs)
Application Report. Comprehensive
FFT algorithms and code for
DSP56001, DSP56156, and
DSP96002
APR4/D
G.722 Audio Processing
Application Report. Theory and code
using SB-ADPCM
APR404/D
Dr. BuB Bulletin Board
Flyer. Motorola’s electronic bulletin
board where free DSP software is
available
BR297/D
Third Party Compendium
Brochures from companies selling
hardware and software that supports
Motorola DSPs
DSP3RDPTYPAK/D
University Support Program
Flyer. Motorola’s program that supports universities in DSP research
and education
BR382/D
Data Sheet Contents
This data sheet contains:
•
•
•
•
•
4
signal definitions and pin locations
electrical specifications and timings
package descriptions
design considerations
ordering information
DSP56156 Data Sheet
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Introduction
Pin Groupings
Pin Groupings
The DSP56156 is available in a 112-pin Ceramic Quad Flat Pack (CQFP) and a 112-pin Plastic
Thin Quad Flat Pack (TQFP). The input and output signals are organized into the functional
groups indicated in Table 3. Figure 2 illustrates the chip’s pin functions.
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Table 3 Functional Pin Groupings
Functional Group
Address
16
Data Bus
16
Bus Control
9
Host Interface (HI)
15
Synchronous Serial Interfaces (SSI)
10
Timer Interface
2
Interrupt and Mode Control
4
Phase-Locked Loop (PLL) and Clock
3
On-Chip Emulation (OnCETM Port)
4
On-Chip Codec
7
Power (VCC)
10
Ground (GND)
16
Total
NOTE:
Number of Pins
112
OVERBARS are used throughout this document to indicate a signal which is at Ground voltage (typically a TTL logic low — VIL or VOL) when the function is logically true. These signals are, likewise, at
VCC voltage (typically a TTL logic high — VIH or VOH) when the function is logically false.
MOTOROLA
DSP56156 Data Sheet
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Introduction
Pin Functions
DSP56156
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A0-A15
D0-D15
RD
WR
BR
BG
BS
TA
PS/DS
R/W
BB
Host
Interface (HI)
External
Bus
MODA/IRQA
MODB/IRQB
MODC
RESET
Interrupt/
Mode
Control
DSO
DSI/OS0
DSCK/OS1
DR
On-Chip
Emulator
(OnCE)
Port
MIC
AUX
SPKP
SPKM
BIAS
VREF
VDIV
Two
Synchronous
Serial
Interfaces
(SSI)
H0-H7*
HA0-HA2*
HR/W*
HEN*
HREQ*
HACK*
STD0*
SRD0*
SCK0*
SC00-SC10*
STD1*
SRD1*
SCK1*
SC01-SC11*
Timer/Event
Counter
TIN*
TOUT*
Clock
and
Phase-locked
Loop
(PLL)
EXTAL
CLKO
SXFC
On-Chip
Codec
112 pins
VCC
GND
* These pins have an alternate function of general purpose input/output.
Figure 2 DSP56156 Pin Functions
6
DSP56156 Data Sheet
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Pin Descriptions
Address and Data Bus
Bus Control
Pin Descriptions
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Address and Data Bus
A0-A15
(Address Bus) — three-state, active
high outputs. A0-A15 change in t0 and
specify the address for external program and data memory accesses. If
there is no external bus activity, A0-A15
remain at their previous values. A0-A15
are three-stated during hardware reset.
D0-D15
(Data Bus) — three-state, active
high, bidirectional input/outputs.
Read data is sampled on the trailing
edge of t2, while write data output is
enabled by the leading edge of t2 and
three-stated at the leading edge of t0. If
there is no external bus activity, D0-D15
are three-stated. D0-D15 are also threestated during hardware reset.
Bus Control
PS/DS (Program/Data Memory Select) —
three-state, active low output. This output is asserted only when external data
memory is referenced. PS/DS timing is
the same for the A0-A15 address lines.
PS/DS is high for program memory access and is low for data memory access. If
the external bus is not used during an instruction cycle (t0, t1, t2, t3), PS/DS goes
high in t0. PS/DS is in the high impedance state during hardware reset.
R/W (Read/Write) — three-state, active
low output. Timing is the same as the
address lines, providing an “early
write” signal. R/W (which changes in
t0) is high for a read access and is low
for a write access. If the external bus is
not used during an instruction cycle
MOTOROLA
(t0, t1, t2, t3), R/W goes high in t0. R/W
is three-stated during hardware reset.
WR (Write Enable) — three-state, active
low output. This output is asserted during external memory write cycles. When
WR is asserted in t1, the data bus pins
D0-D15 become outputs and the DSP
puts data on the bus during the leading
edge of t2. When WR is deasserted in t3,
the external data has been latched inside
the external device. When WR is asserted, it qualifies the A0-A15 and PS/DS
pins. WR can be connected directly to
the WE pin of a static RAM. WR is threestated during hardware reset or when
the DSP is not bus master.
RD (Read Enable) — three-state, active
low output. This output is asserted
during external memory read cycles.
When RD is asserted in late t0/early t1,
the data bus pins D0-D15 become inputs and an external device is enabled
onto the data bus. When RD is deasserted in t3, the external data is latched
inside the DSP. When RD is asserted, it
qualifies the A0-A15 and PS/DS pins.
RD can be connected directly to the
OE pin of a static RAM or ROM. RD is
three-stated during hardware reset or
when the DSP is not bus master.
BS (Bus Strobe) — three-state, active
low output. Asserted at the start of a
bus cycle (during t0) and deasserted at
the end of the bus cycle (during t2).
This pin provides an “early bus start”
signal which can be used as address
latch and as an “early bus end” signal
which can be used by an external bus
controller. BS is three-stated during
hardware reset.
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Pin Descriptions
Bus Control
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TA (Transfer Acknowledge) — active
low input. If there is no external bus activity, the TA input is ignored by the
DSP. When there is external bus cycle
activity, TA can be used to insert wait
states in the external bus cycle. TA is
sampled on the leading edge of the
clock. Any number of wait states from 1
to infinity may be inserted by using TA.
If TA is sampled high on the leading
edge of the clock beginning the bus cycle, the bus cycle will end 2T after the
TA has been sampled low on a leading
edge of the clock; if the Bus Control Register (BCR) value does not program
more wait states. The number of wait
states is determined by the TA input or
by the Bus Control Register (BCR),
whichever is longer. TA is still sampled
during the leading edge of the clock
when wait states are controlled by the
BCR value. In that case, TA will have to
be sampled low during the leading edge
of the last period of the bus cycle programmed by the BCR (2T before the end
of the bus cycle programmed by the
BCR) in order not to add any wait states.
TA should always be deasserted during
t3 to be sampled high by the leading
edge of T0. If TA is sampled low (asserted) at the leading edge of the t0 beginning the bus cycle, and if no wait states
are specified in the BCR register, zero
wait states will be inserted in the external bus cycle, regardless the status of
TA during the leading edge of T2.
BR (Bus Request) — active low output
when in master mode, active low input when in slave mode. After poweron reset, this pin is an input (slave
mode). In this mode, the bus request
BR allows another device such as a processor or DMA controller to become
the master of the DSP external data
bus D0-D15 and external address bus
A0-A15. The DSP asserts BG a few T
states after the BR input is asserted.
The DSP bus controller releases control
of the external data bus D0-D15, address bus A0-A15 and bus control pins
PS/DS, RD, WR, and R/W at the earliest time possible consistent with proper synchronization. These pins are then
placed in the high impedance state and
T0 T1 T2 T3 T0 T1 T2 Tw T2 T3 T0 T1 T2 T3 T0 T1 T2 Tw T2 Tw T2 T3
CLKO
TA
BS
T0 T1 T2 Tw T2 Tw T2 Tw T2 T3 T0 T1 T2 Tw T2 Tw T2 T3 T0 T1 T2
CLKO
TA
BS
Figure 3 TA Controlled Accesses
8
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Pin Descriptions
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Bus Control
the BB pin is deasserted. The DSP continues executing instructions only if internal program and data memory
resources are accessed. If the DSP requests the external bus while BR input
pin is asserted, the DSP bus controller
inserts wait states until the external bus
becomes available (BR and BB deasserted). Note that interrupts are not
serviced when a DSP instruction is
waiting for the bus controller. Note
also that BR is prevented from interrupting the execution of a read/ modify/write instruction.
If the master bit in the OMR register is
set, this pin becomes an output (Master
Mode). In this mode, the DSP is not the
external bus master and has to assert
BR to request the bus mastership. The
DSP bus controller will insert wait
states until BG input is asserted and
will then begin normal bus accesses after the rising of the clock which sampled BB high. The BR output signal will
remain asserted until the DSP no longer needs the bus. In this mode, the Request Hold bit (RH) of the Bus Control
Register (BCR) allows BR to be asserted
under software control.
During external accesses caused by an
instruction executed out of external program memory, BR remains asserted low
for consecutive external X memory accesses and continues toggling for consecutive external P memory accesses
unless the Request Hold bit (RH) is set
inside the Bus Control Register (BCR).
In the master mode, BR can also be
used for non arbitration purpose: if BG
is always asserted, BR is asserted in t0
of every external bus access. It can then
be used as a chip select to turn a exter-
MOTOROLA
nal memory device off and on between
internal and external bus accesses. BR
timing is in that case similar to A0-A15,
R/W and PS/DS; it is asserted and
deasserted during t0.
BG (Bus Grant) — active low input when
in master mode, active low output
when in slave mode. Output after
power on reset if the slave is selected,
this pin is asserted to acknowledge an
external bus request. It indicates that
the DSP will release control of the external address bus A0-A15, data bus
D0-D15 and bus control pins when BB
is deasserted. The BG output is asserted in response to a BR input. When the
BG output is asserted and BB is deasserted, the external address bus A0-A15,
data bus D0-D15 and bus control pins
are in the high impedance state. BG assertion may occur in the middle of an
instruction which requires more than
one external bus cycle for execution.
Note that BG assertion will not occur
during indivisible read-modify-write
instructions (BFSET, BFCLR, BFCHG).
When BR is deasserted, the BG output
is deasserted and the DSP regains control of the external address bus, data
bus, and bus control pins when the BB
pin is sampled high.
This pin becomes an input if the master
bit in the OMR register is set (Master
Mode). It is asserted by an external processor when the DSP may become the
bus master. The DSP can start normal
external memory access after the BB pin
has been deasserted by the previous
bus master. When BG is deasserted, the
DSP will release the bus as soon as the
current transfer is completed. The state
of BG may be tested by testing the BS bit
in the Bus Control Register. BG is ignored during hardware reset.
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Pin Descriptions
Bus Control
Interrupt and Mode Control
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BB (Bus Busy) — active low input when
not bus master, active low output
when bus master. This pin is asserted
by the DSP when it becomes the bus
master and it performs an external access. It is deasserted when the DSP releases bus mastership. BB becomes an
input when the DSP is no longer the
bus master.
Interrupt and Mode Control
MODA/IRQA
(Mode Select A/External Interrupt Request A) — input. This input has two functions:
• to select the initial chip operating
mode and,
• to allow an external device to request
a DSP interrupt after internal synchronization.
MODA is read and internally latched
in the DSP when the processor exits the
reset state. MODA and MODB select
the initial chip operating mode. Several
clock cycles after leaving the reset state,
the MODA pin changes to the external
interrupt request IRQA. The chip operating mode can be changed by software after reset.
The IRQA input is a synchronized external interrupt request which indicates that an external device is
requesting service. It may be programmed to be level sensitive or negative edge triggered. If level sensitive
triggering is selected, an external pull
up resistor is required for wired-OR
operation. If the processor is in the stop
standby state and IRQA is asserted, the
processor will exit the stop state.
10
MODB/IRQB
(Mode Select B/External Interrupt Request B) — input. This input has two functions:
• to select the initial chip operating
mode and,
• to allow an external device to request
a DSP interrupt after internal synchronization.
MODB is read and internally latched in
the DSP when the processor exits the
reset state. MODA and MODB select
the initial chip operating mode. Several
clock cycles after leaving the reset state,
the MODB pin changes to the external
interrupt request IRQB. After reset, the
chip operating mode can be changed
by software.
The IRQB input is an external interrupt
request which indicates that an external device is requesting service. It may
be programmed to be level sensitive or
negative edge triggered. If level sensitive triggering is selected, an external
pull up resistor is required for wiredOR operation.
MODC (Mode Select C) — input. This input
selects the initial bus operating mode.
When tied high, the external bus is programmed in the master mode (BR output and BG input) and when tied low
the bus is programmed in the slave
mode (BR input and BG output).
MODC is read and internally latched in
the DSP when the processor exits the
reset state. After RESET, the bus operating mode can be changed by software by
writing the MC bit of the OMR register.
RESET (Reset) — input. This input is a direct
hardware reset of the processor. When
RESET is asserted, the DSP is initialized
and placed in the reset state. A Schmitt
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Pin Descriptions
Interrupt and Mode Control
Host Interface
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trigger input is used for noise immunity.
When the reset pin is deasserted, the initial chip operating mode is latched from
the MODA and MODB pins, and the initial bus operating mode is latched from
the MODC pin. The internal reset signal
should be deasserted synchronized with
the internal clocks.
Host Interface
H0-H7 (Host Data Bus) — bidirectional. This
bidirectional data bus is used to transfer
data between the host processor and the
DSP. This bus is an input unless enabled
by a host processor read. H0-H7 may be
programmed as Port B general purpose
parallel I/O pins called PB0-PB7 when
the Host Interface (HI) is not being used.
HA0-HA2 (Host Address 0-2) — input*. These
inputs provide the address selection
for each HI register and are stable
when HEN is asserted. HA0-HA2 may
be programmed as Port B general purpose parallel I/O pins called PB8-PB10
when the HI is not being used.
HR/W (Host Read/Write) — input*. This input selects the direction of data transfer
for each host processor access. If HR/W
is high and HEN is asserted, H0-H7 are
outputs and DSP data is transferred to
the host processor. If HR/W is low and
HEN is asserted, H0-H7 are inputs and
host data is transferred to the DSP.
When HEN is asserted, HR/W is stable.
HR/W may be programmed as a general purpose I/O pin called PB11
when the HI is not being used.
HEN (Host Enable) — input*. This input enables a data transfer on the host data
bus. When HEN is asserted and HR/W
is high, H0-H7 becomes an output and
DSP data may be latched by the host
processor. When HEN is asserted and
HR/W is low, H0-H7 is an input and
host data is latched inside the DSP
when HEN is deasserted. Normally a
chip select signal derived from host address decoding and an enable clock is
connected to the Host Enable. HEN
may be programmed as a general purpose I/O pin called PB12 when the HI
is not being used.
HREQ (Host Request) — output*. This opendrain output signal is used by the HI to
request service from the host processor. HREQ may be connected to an interrupt request pin of a host processor,
a transfer request of a DMA controller,
or a control input of external circuitry.
HREQ is asserted when an enabled request occurs in the HI. HREQ is deasserted when the enabled request is
cleared or masked, DMA HACK is asserted, or the DSP is reset. HREQ may
be programmed as a general purpose
I/O pin (not open-drain) called PB13
when the HI is not being used.
HACK (Host Acknowledge) — input*. This
input has two functions:
• to provide a host acknowledge signal
for DMA transfers and,
• to control handshaking and to provide a host interrupt acknowledge
compatible with MC68000 family
processors.
If programmed as a host acknowledge
signal, HACK may be used as a data
strobe for HI DMA data transfers. If programmed as an MC68000 host interrupt
* These pins can be bidirectional when programmed as general purpose I/O.
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Pin Descriptions
16-bit Timer
SSI
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acknowledge, HACK enables the HI
Interrupt Vector Register (IVR) onto
the host data bus H0-H7 if the Host Request HREQ output is asserted. In this
case, all other HI control pins are ignored and the HI state is not affected.
HACK may be programmed as a general purpose I/O pin called PB14 when
the HI is not being used.
16-bit Timer
TIN (Timer Input) — input*. This input receives external pulses to be counted by
the on-chip 16-bit timer when external
clocking is selected. The pulses are internally synchronized to the DSP core
internal clock. TIN may be programmed as a general purpose I/O pin
called PC10 when the external event
function is not being used.
TOUT (Timer Output) — output*. This output generates pulses or toggles on a
timer overflow event or a compare
event. TOUT may be programmed as a
general purpose I/O pin called PC11
when disabled by the timer out enable
bits (TO2-TO0).
Synchronous Serial
Interfaces (SSI)
PC0 and PC5, respectively, when the
STD function is not being used.
SRD0-1 (SSI0-1 Receive Data) — input*.
These input pins receive serial data and
transfer the data to the SSI0-1 Receive
Shift Register. SRD0 and SRD1 may be
programmed as a general purpose I/O
pin called PC1 and PC6, respectively,
when the SRD function is not being
used.
SCK0-1 (SSI0-1 Serial Clock) — bidirectional. These bidirectional pins provide the
serial bit rate clock for the SSI0-1 interface. SCK0 and SCK1 may be programmed as a general purpose I/O pin
called PC2 and PC7, respectively,
when the SSI0-1 interfaces are not being used.
SC10-11 (SSI0-1 Serial Control 1) — bidirectional. These bidirectional pins are
used by the SSI0-1 serial interface as
frame sync I/O or flag I/O. SC10 and
SC11 may be programmed as a general
purpose I/O pin called PC3 and PC8,
respectively, when the SSI0-1 are not
using these pins.
SC00-01 (SSI0-1 Serial Control 0) — bidirectional. These bidirectional pins are
used by the SSI0-1 serial interface as
frame sync I/O or flag I/O. SC00 and
SC01 may be programmed as a general
purpose I/O pin called PC4 and PC9,
respectively, when the SSI0-1 are not
using these pins.
STD0-1 (SSI0-1 Transmit Data) — output*.
These output pins transmit serial data
from the SSI0-1 Transmit Shift Register.
STD0 and STD1 may be programmed
as a general purpose I/O pin called
* These pins can be bidirectional when programmed as general purpose I/O.
12
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
Pin Descriptions
OnCE
On-Chip Codec
Freescale Semiconductor, Inc...
On-Chip Emulation
(OnCETM Port)
DSI/OS0 (Debug Serial Input/Chip Status 0) —
bidirectional. The DSI/OS0 pin, when
an input, is the pin through which serial data or commands are provided to
the OnCE port controller. The data received on the DSI pin will be recognized only when the DSP has entered
the debug mode of operation. Data
must have valid TTL logic levels before
the serial clock falling edge. Data is always shifted into the OnCE serial port
most significant bit (MSB) first. When the
DSP is not in the debug mode, the DSI/
OS0 pin provides information about the
chip status if it is an output and used in
conjunction with the OS1 pin.
DSCK/OS1 (Debug Serial Clock/Chip Status 1)
— bidirectional. The DSCK/OS1 pin,
when an input, is the pin through
which the serial clock is supplied to the
OnCE port. The serial clock provides
pulses required to shift data into and
out of the OnCE serial port. Data is
clocked into the OnCE port on the falling edge and is clocked out of the
OnCE serial port on the rising edge. If
the DSCK/OS1 pin is an output and
used in conjunction with the OS0 pin, it
provides information about the chip
status when the DSP is not in the debug
mode.
DSO (Debug Serial) — output. The debug
serial output provides the data contained in one of the OnCE port controller registers as specified by the last
command received from the command
controller. When idle, this pin is high.
When the requested data is available, the
DSO line will be asserted (negative true
logic) for four T cycles (one instruction
MOTOROLA
cycle) to indicate that the serial shift register is ready to receive clocks in order to
deliver the data. When the chip enters
the debug mode due to an external debug request (DR), an internal software
debug request (DEBUG), a hardware
breakpoint occurrence or a trace/step
occurrence, this line will be asserted for
three T cycles to indicate that the chip
has entered the debug mode and is waiting for commands. Data is always shifted out the OnCE serial port with the
most significant bit first.
DR (Debug Request) — input. The debug
request input provides a means of entering the debug mode of operation.
This pin, when asserted, will cause the
DSP to finish the current instruction being executed, enter the debug mode,
and wait for commands to be entered
from the debug serial input line.
On-Chip Codec
AUX (Auxiliary) — input. This pin is selected as the analog input to the A/D converter when the INS bit is set in the
codec control register COCR. This pin
should be left floating when the codec
is not used.
BIAS (Bias current) — input. This input is
used to determine the bias current for
the analog circuitry. Connecting a resistor between BIAS and GNDA will
program the current bias generator.
This pin should be left floating when
the codec is not used.
MIC (Microphone) — input. This pin is selected as the analog input to the A/D
converter when the INS bit is cleared in
DSP56156 Data Sheet
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13
Freescale Semiconductor, Inc.
Pin Descriptions
On-Chip Codec
Power, Ground, and Clock
the codec control register COCR. This
pin should be left floating when the codec is not used.
GNDS (Synthesizer Ground) — This pin supplies a quiet ground source to the PLL
to provide greater frequency stability.
SPKP (Speaker Plus) — output. This pin is
the positive analog output from the onchip D/A converter. This pin should be
left floating when the codec is not used.
VCCA (Analog Power) — This pin is the posi-
Freescale Semiconductor, Inc...
SPKM (Speaker Minus) — output. This pin is
the negative analog output from the
on-chip D/A converter. This pin
should be left floating when the codec
is not used.
VREF (Voltage Reference) — output. This
pin is the op-amp buffer output in the
reference voltage generator. It has a
value of (2/5)VCCA. This pin should always be connected to the GNDA
through two capacitors, even when the
codec is not used.
VDIV (Voltage Division) — output. This
output pin is also the output to the onchip op-amp buffer in the reference
voltage generator. It is connected to a
resistor divider network located within
the codec block which provides a voltage equal to (2/5)VCCA. This pin should
be connected to the GND via a capacitor
when the codec is used and should be
left floating when the codec is not used.
Power, Ground, and Clock
VCC (Power) — Power pins
GND (Ground) — Ground pins
VCCS (Synthesizer Power) — This pin supplies a quiet power source to the PhaseLocked Loop (PLL) to provide greater
frequency stability.
14
tive analog supply input. It should be connected to VCC when the codec is not used.
GNDA (Analog Ground) — This pin is the analog ground return. It should be connected to digital GND when the codec
is not used.
EXTAL (External Clock) — input. This input
should be driven by an external clock or
by an external oscillator. After being
squared, the input frequency can be
used as the DSP core internal clock. In
that case, it is divided by two to produce
a four phase instruction cycle clock, the
minimum instruction time being two input clock periods. This input frequency
is also used, after division, as input
clock for the on-chip codec and the onchip PLL.
CLKO (Clock Output) — output. This pin
outputs a buffered clock signal. By programming two bits (CS1-CS0) inside
the PLL Control Register (PLCR), the
user can select between outputting a
squared version of the signal applied to
EXTAL, a squared version of the signal
applied to EXTAL divided by 2, and a
delayed version of the DSP core master
clock. The clock frequency on this pin
can be disabled by setting the Clockout
Disable bit (CD; bit 7) of the Operating
Mode Register (OMR). When disabled,
the pin can be left floating.
SXFC (External Filter Capacitor) — This pin
adds an external capacitor to the PLL
filter circuit. A low leakage capacitor
should be connected between and located very close to SXFC and VCCS.
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
Electrical Characteristics and Timing
Electrical Characteristics and Timing
CAUTION:
Exceeding maximum electrical ratings will permanently damage or
disable the chip, or impair the chip’s long term reliability.
Freescale Semiconductor, Inc...
The DSP56156 is fabricated in high density HCMOS with TTL compatible inputs and CMOS
compatible outputs.
Table 4 Maximum Electrical Ratings (GND = 0 Vdc)
Rating
Symbol
Value
Unit
Supply Voltage
VCC
-0.3 to +7.0
V
All Input Voltages
VIN
GND - 0.5 to VCC + 0.5
V
I
10
mA
Tstg
-55 to +150
°C
Current Drain per Pin excluding VCC and GND
Storage Temperature
Table 5 Operating Conditions
Supply Voltage
VCC
Junction Temperature
TJ (°C)
Min
Max
Min
Max
4.5
5.5
-40
115
Table 6 Thermal Characteristics of CQFP and TQFP Packages
Thermal Resistance
Characteristics
Value
Symbol
Rating
CQFP
TQFP
Junction to Ambient
ΘJA
40
49
°C/W
Junction to Case (estimated)
ΘJC
7
8
°C/W
NOTE: This device contains protective circuitry to guard against damage due to high static voltage or electrical
fields. However, normal precautions are advised to avoid application of any voltages higher than maximum
rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied
to an appropriate logic voltage level (e.g., either GND or VCC).
MOTOROLA
DSP56156 Data Sheet
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Freescale Semiconductor, Inc.
Electrical Characteristics and Timing
Analog I/O Characteristics
Analog I/O Characteristics
(VCCA = 5.0 V dc ± 10%, TJ = -40° to +125°C)
The analog I/O characteristics of this device are listed in Table 7.
For additional information regarding the use of analog signals, see “Design Considerations”
at the end of this document.
Freescale Semiconductor, Inc...
Table 7 Analog I/O Characteristics
Characteristic
Min
Typ
Max
Unit
46
78
1400
kΩ
Input Capacitance on MIC and AUX
—
—
10
pF
Peak Input Voltage on the MIC/AUX Input for Full Scale
Linearity (0.14 dBm0):
6 dB - MGS1 - 0 = 00
(See Note 2)
0 dB - MGS1 - 0 = 01
6 dB - MGS1 - 0 = 10
17 dB - MGS1 - 0 = 11
—
—
—
—
—
—
—
—
1.414
0.707
354
100
Vp
Vp
mVp
mVp
G - 0.83
G
G + 0.83
dB
VREF Output Voltage
1.8
2
2.2
V
VREF Output Current
—
—
±1
mA
DC Offset Between SPKP and SPKM
—
—
100
mV
Allowable Differential Load Capacitance on
SPKP and SPKM (with 1 kΩ in series)
0
—
0.05
µF
0
(See Note 3)
—
100
0.1
µF
Maximum Single-ended Signal Output Level
—
—
1
Vp
Maximum Differential Signal Output Level
—
—
2
Vp
500
—
—
Ω
Differential Load Resistance
1
—
—
kΩ
Resistance BIAS
—
10
(See
Note 4)
—
kΩ
VC - 0.83
VC
VC + 0.83
dB
Input Impedance on MIC and AUX
(See Note 1)
Internal Input Gain Variation;
G = -6 dB, 0 dB, 6 dB or 17 dB
(±0.83 dB variation due to 10% variation on VCC):
Allowable Single-ended Load Capacitance on
SPKP or SPKM (with 0.5 kΩ in series)
Single-ended Load Resistance
Internal Output Volume Control Variation
VC = -20, -15, -10, -5, 0, 6, 12, 18, 24, 30, 35 dB
(± 0.83 dB variation due to 10% variation on V CC)
NOTES: 1.
2.
3.
4.
16
Minimum value reached for a Codec clock of 3 MHz, typical for 2 MHz and maximum for 100 kHz
0 dBm0 corresponds to 3.14 dB below the input saturation level
AC coupling is necessary in single-ended mode when the load resistor is not tied to VREF
± 10%
DSP56156 Data Sheet
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Freescale Semiconductor, Inc.
Electrical Characteristics and Timing
A/D and D/A Performance
A/D and D/A Performance
(VCCA = 5.0 V dc ± 10%, TJ = -40° to +125°C)
The A/D and D/A performance of the codec section are given in Table 8 with an
example presented in Figure 4.
Freescale Semiconductor, Inc...
Table 8 A/D and D/A Performance of Codec
Characteristic
Analog to Digital Section Signal to Noise
plus Distortion Ratio (S/N+T)
Digital to Analog Section Signal to Noise
plus Distortion Ratio (S/N+T)
Level
Min
Typ
(See Note 1)
Max
Unit
0 dBm0
55
65
—
dB
-50 dBm0
15
20
—
dB
0 dB
55
65
—
dB
-50 dB
15
20
—
dB
(See Note 2)
NOTES: 1. 0 dB gain on the A/D and D/A; Codec clock at 1.538 MHz with 128 decimation/interpolation ratio and
tested at 1502 Hz
2. 0 dBm0 corresponds to -3.14 dB below the input saturation level
80
2 MHz
S/N
CODEC
Codec
÷ 6.5
70
S/N+T
13 MHz
60
COCR=$E400
1 MHz
÷÷13
13
PLL
PLL
52 MHz
50
÷(12+1)x4
÷(12+1)*4
40
30
20
10
0
S in dB in dB
Signal
Figure 4 Example: S/N and S/N+T Performance for the A/D Section
MOTOROLA
DSP56156 Data Sheet
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Freescale Semiconductor, Inc.
Electrical Characteristics and Timing
Other On-Chip Codec Characteristics
Other On-Chip Codec Characteristics
(VCCA = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
The analog I/O characteristics of this device are shown in Table 9.
Freescale Semiconductor, Inc...
Table 9 Analog I/O Characteristics of On-Chip Codec
18
Characteristic
Min
Typ
Max
Unit
Codec Master Clock
0.1
2.048
3
MHz
Codec Sampling Rate
78
16000
37000
Hz
A/D Section Group Delay
—
—
0.2
msec
D/A Section Group Delay
—
—
0.2
msec
DSP56156 Data Sheet
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DC Electrical Characteristics and Timing
DC Electrical Characteristics
(GND = 0 V dc)
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
The DC electrical characteristics of this device are shown in Table 10.
Freescale Semiconductor, Inc...
Table 10 DC Electrical Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
Input High Voltage
except EXTAL, RESET, MODA, MODB, MODC
VIH
2.0
—
VCC
V
Input Low Voltage
except EXTAL, MODA, MODB, MODC
VIL
-0.5
—
0.8
V
70% of VCC
1
—
—
VCC
VCC
-0.5
-0.5
—
—
20% of VCC
VCC-1
Input High Voltage
EXTAL DC coupled
EXTAL AC coupled (See Note 1)
VIHC
Input Low Voltage
EXTAL DC coupled
EXTAL AC coupled (See Note 1)
VILC
Input High Voltage RESET
VIHR
2.5
—
VCC
V
Input High Voltage MODA, MODB, MODC
VIHM
3.5
—
VCC
V
Input Low Voltage MODA, MODB, MODC
VILM
-0.5
—
2.0
V
100
1
µA
µA
V
V
—
IIN
Input Leakage Current
-100
-1
EXTAL
RESET, MODA, MODB, MODC, TA, DR, BR
Three-State (Off-State) Input Current
(@2.4 V/0.5 V)
TSI
-10
—
10
µA
Output High Voltage (IOH = -10 µA)
VOHC
VCC -0.1
—
—
V
Output High Voltage (IOH = -0.4 mA)
VOH
2.4
—
—
V
Output Low Voltage (IOL = 10 µA)
VOLC
—
—
0.1
V
Output Low Voltage (IOL = 3.2 mA
R/W IOL = 1.6 mA; Open Drain
HREQ IOL = 6.7 mA, TXD IOL = 6.7 mA)
VOL
—
—
0.4
V
Input Capacitance
CIN
—
10
—
pF
NOTES:
(See Note 2)
1. When EXTAL is AC coupled, VIHC - VILC Š 1 V must be true.
2. Input capacitance is periodically sampled and not 100% tested in production.
MOTOROLA
DSP56156 Data Sheet
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Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Clock Operation Timing
AC Electrical Characteristics
(GND = 0 V dc)
Freescale Semiconductor, Inc...
The timing waveforms in the AC Electrical Characteristics are tested with a VIL maximum of
0.5 V and a VIH minimum of 2.4 V for all pins, except EXTAL, RESET, MODA, MODB and
MODC. These five pins are tested using the input levels set forth in the DC Electrical Characteristics. AC timing specifications which are referenced to a device input signal are measured
in production with respect to the 50% point of the respective input signal’s transition. The
DSP56156 output levels are measured with the production test machine VOL and VOH reference levels set at 0.8 V and 2.0 V respectively.
Clock Operation Timing
The system clock to the DSP56156 must be externally supplied to EXTAL as illustrated in
Figure 6.
Table 11 Clock Operation Timing
40 MHz
Num
Characteristics
50 MHz
60 MHz
Sym
Unit
Min
Max
Min
Max
Min
Max
f
0
40
0
50
0
60
MHz
ICYC
50
×
40
×
33
×
ns
1
Frequency of Operation (EXTAL)
2
Instruction Cycle Time = 2TC
3
Wait State Time = TC = 2T
—
25
×
20
×
16.6
×
ns
4
EXTAL Cycle Period
TC
25
×
20
×
16.6
×
ns
5
EXTAL Rise Time (See Note 1)
—
4
—
3
—
3
ns
6
EXTAL Fall Time (See Note 1)
—
4
—
3
—
3
ns
7
EXTAL Width High
48-52% duty cycle
(See Notes 2, 3, 4)
TH
12
×
9.6
×
8
×
ns
8
EXTAL Width Low
48%-52% duty cycle
(See Notes 2, 3, 4)
TL
12
×
9.6
×
8
×
ns
NOTES: 1. Rise and fall time may be relaxed to 12 ns maximum if the EXTAL input frequency is less than or equal
to 20 MHz. If the EXTAL input frequency is between 20 MHz and 40 MHz, rise and fall time should
meet the specified values in the 40 MHz column (4 ns maximum).
2. The duty cycle may be relaxed to 43-57% if the EXTAL input frequency is less than or equal to 20 MHz.
If the EXTAL input frequency is between 20 MHz and 40 MHz, the duty cycle should be such that TH
and TL meet the specified values in the 40 MHz column (12 ns minimum).
3. T = ICYC / 4 is used in the electrical characteristics. The exact length of each T is affected by the duty
cycle of the external clock input.
4. Duty cycles and EXTAL widths are measured at the EXTAL input signal midpoint when AC coupled and
at VCC/2 when not AC coupled.
20
DSP56156 Data Sheet
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Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Clock Operation Timing
PLL
TH
TL
90%
EXTAL
VIHC
Midpoint
10%
7
VILC
8
6
5
4
2
Freescale Semiconductor, Inc...
Figure 5 External Clock Timing
Other Clock and PLL Operation Timing
Clock and PLL timings are listed in Table 12 and the clocking configurations are illustrated in
Figure 6.
Table 12 Clock and PLL Timing
Characteristics
Min
Max
Unit
PLL Output frequency
10
Max Fosc
(See Note 1)
MHz
EXTAL Input Clock Amplitude (See Note 2)
1
VCC
Vpp
NOTES: 1. Maximum DSP operating frequency. See Table 11.
2. An AC coupling capacitor is required on EXTAL if the levels are out of the normal CMOS level
range (VILC>20% of VCC or VIHC<70% of VCC).
10 nF
XFC
PFD
ED3-ED0
LF
VCO
÷ 1 to ÷ 16
1000 pF
PLL
÷ 6.5
GNDS
PLLE=1
÷ 1 to ÷ 16
EXTAL
0.1 µF
VCCS
SXFC
100 KΩ
0.01 µF
÷4
Fosc
PLLE=0
YD3-YD0
GSM
CS1-CS0
CODEC
CLKO
÷2
internal phase PH0 at Fosc
Figure 6 Clocking Configurations
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AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
ws = Number of wait states programmed into external bus access using BCR (WS = 0 - 31)
Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing
40 MHz
Freescale Semiconductor, Inc...
Num
50 MHz
60 MHz
Characteristics
Unit
10
RESET Assertion to Address, Data and
Control Signals High Impedance
11
Minimum Stabilization Duration
(See Note 1)
OMR bit 6=0
OMR bit 6=1
Min
Max
Min
Max
Min
Max
—
25
—
23
—
21
ns
600KT
60T
—
—
600KT
60T
—
—
600KT
60T
—
—
ns
ns
12
Asynchronous RESET Deassertion to
First External Address Output
(See Note 7)
16T
18T+20
16T
18T+17
16T
18T+15
ns
13
Synchronous Reset Setup Time from
RESET Deassertion to Rising Edge of
CLKO
7
cyc-4
6
cyc-3
5
cyc-2
ns
14
Synchronous Reset Delay Time from
CLKO High to the First External Access
(See Note 7)
16T+3
16T+20
16T+ 3
16T+18
16T+3
16T+16
ns
15
Mode Select Setup Time
22
—
20
—
18
—
ns
16
Mode Select Hold Time
0
—
0
—
0
—
ns
17
Edge-triggered Interrupt Request Width
13
—
11
—
9
—
ns
18
Delay from IRQA, IRQB Assertion to
External Data Memory Access Out Valid
- Caused by First Interrupt
Instruction Fetch
- Caused by First Interrupt
Instruction Execution
11T+4
—
11T+4
—
11T+3
—
ns
19T+4
—
19T+4
—
19T+3
—
ns
22T+4
—
22T+3
—
ns
—
5T-24
+
cyc × ws
—
5T-22
+
cyc × ws
ns
19
20
22
Delay from IRQA, IRQB Assertion to
General Purpose Output Valid Caused
by the Execution of the First Interrupt
Instruction
Delay from External Data Memory
Address Output Valid Caused by First
Interrupt Instruction Execution to Interrupt Request Deassertion for Level Sensitive Fast Interrupts (See Note 2)
—
22T+5
—
5T-26
+
cyc × ws
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Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing (continued)
40 MHz
Num
Freescale Semiconductor, Inc...
21
50 MHz
60 MHz
Characteristics
Delay from General-Purpose
Output Valid Caused by the
Execution of the First Interrupt Instruction to IRQA,
IRQB Deassertion for Level
Sensitive Fast Interrupts — If
2nd Interrupt Instruction is:
Single Cycle
(See Note 2)
Two Cycles
Unit
Min
Max
Min
Max
Min
Max
—
cyc - 29
—
cyc - 27
—
cyc - 26
ns
—
3 cyc - 29
—
3 cyc - 27
—
3 cyc - 26
ns
22
Synchronous setup time from
IRQA, IRQB assertion to
Synchronous falling edge of
CLKO (See Notes 5 and 6)
14
cyc-3
13
cyc-2
12
cyc-1
ns
23
Falling Edge of CLKO to First
Interrupt Vector Address Out
Valid after Synchronous
recovery from Wait State
(See Notes 3 and 5)
27T+3
27T+20
27T+3
27T+18
27T+3
27T+16
ns
24
IRQA Width Assertion to
Recover from Stop State
(See Note 4)
15
—
13
—
12
—
ns
25
Delay from IRQA Assertion to
Fetch of first instruction (exiting Stop)
(See Notes 1 and 3)
OMR bit 6=0
OMR bit 6=1
524303T+4
47T+4
—
—
524303T+3
47T+3
—
—
524303T+3
47T+3
—
—
ns
ns
Duration for Level Sensitive
IRQA Assertion to Cause the
Fetch of First IRQA Interrupt
Instruction (exiting Stop)
(See Notes 1 and 3)
OMR bit 6=0
OMR bit 6=1
524303T
47T
—
—
524303T
47T
—
—
524303T
47T
—
—
ns
ns
Delay from Level Sensitive
IRQA Assertion to First Interrupt Vector Address Out
Valid (exiting Stop)
(See Notes 1 and 3)
OMR bit 6=0
OMR bit 6=1
524303T+4
47T+4
—
—
524303T+3
47T+3
—
—
524303T+3
47T+3
—
—
ns
ns
28
29
MOTOROLA
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Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Freescale Semiconductor, Inc...
NOTES:
1. Circuit stabilization delay is required during reset when using an external clock in two cases:
• after power-on reset
• when recovering from Stop mode
2. When using fast interrupts, IRQA or IRQB is defined as level-sensitive, then timings 20 and 21
apply to prevent multiple interrupt service. To avoid these timing restrictions, the negative edge-triggered mode is recommended when using fast interrupts.
3. The interrupt instruction fetch is visible on the pins only in Mode 3.
4. The minimum is specified for the duration of an edge triggered IRQA interrupt required to recover
from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted.
5. Timing #22 is for all IRQx interrupts while timing #23 is only when exiting the Wait state.
6. Timing #22 triggers off T1 in the normal state and off phi1 when exiting the Wait state.
7. The instruction fetch is visible on the pins only in Mode 2 and Mode 3.
VIHR
RESET
11
D0-D15
A0-A15
PS/DS
R/W
BS
12
10
First Fetch
Figure 7 Asynchronous Reset Timing
CLKO
13
RESET
A0-A15
PS/DS
BS
R/W
14
Figure 8 Synchronous Reset Timing
24
DSP56156 Data Sheet
For More Information On This Product,
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MOTOROLA
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
VIHR
RESET
15
16
Freescale Semiconductor, Inc...
MODA
MODB
MODC
VIHM
VIH
VILM
VIL
IRQA
IRQB
Figure 9 Operating Mode Select Timing
IRQA
IRQB
17
Figure 10 External Interrupt Timing (Negative Edge-Triggered)
A0-A15
PS/DS
BS
R/W
IRQA
IRQB
First Interrupt Instruction Execution
18
20
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
IRQA
IRQB
19
21
b) General Purpose I/O
Figure 11 External Level-Sensitive Fast Interrupt Timing
MOTOROLA
DSP56156 Data Sheet
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25
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
CLKO
T0, T2
phi0
T1, T3
phi1
22
IRQA
IRQB
23
Freescale Semiconductor, Inc...
A0-A15
PD/DS
BS
R/W
First Interrupt
Instruction Fetch
Figure 12 Synchronous Interrupt from Wait State Timing
24
IRQA
25
A0-A15
PD/DS
BS
R/W
First Instruction Fetch
Not IRQA Interrupt Vector
Figure 13 Recovery from Stop State Using Asynchronous Interrupt Timing
IRQA
A0-A15
PD/DS
BS
R/W
28
29
First IRQA Interrupt
Instruction Fetch
Figure 14 Recovery from Stop State Using IRQA Interrupt Service
26
DSP56156 Data Sheet
For More Information On This Product,
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MOTOROLA
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 14 Wait and Stop Timings
40 MHz
Num
Freescale Semiconductor, Inc...
30
31
32
33
50 MHz
60 MHz
Characteristics
Unit
Min
Max
Min
Max
Min
Max
DR Asserted to CLK high (Setup
Time for Synchronous Recovery
from Wait State)
10
cyc - 4
9
cyc - 3
8
cyc - 2
ns
CLK high to DSO (ACK) Valid
(Enter Debug Mode) after Synchronous Recovery from Wait
State
18 cyc
—
18 cyc
—
18 cyc
—
ns
DR to DSO (ACK) Valid
(Enter Debug Mode)
- After Asynchronous Recovery
from Stop State
- After Asynchronous Recovery
from Wait State
29 cyc
—
29 cyc
—
29 cyc
—
ns
18 cyc
—
18 cyc
—
18 cyc
—
ns
12
10 cyc
11
10 cyc
10
10 cyc
ns
29 cyc
—
29 cyc
—
29 cyc
—
ns
262157
cyc
—
262157
cyc
—
262157
cyc
—
ns
DR Assertion Width
- to Recover from Wait/Stop
without entering debug mode
- to Recover from Wait/Stop
short wake-up and enter
debug mode
- to Recover from Stop
long wake-up and enter
debug mode
33
DR
(input)
32
DSO
(output)
Figure 15 Recovery from Wait State Using DR Pin — Synchronous Timing
MOTOROLA
DSP56156 Data Sheet
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27
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Capacitance Derating
CLKO
(output)
T0, T2
T1, T3
33
DR
(input)
Freescale Semiconductor, Inc...
30
31
DSO
(output)
Figure 16 Recovery from Wait/Stop State Using DR Pin — Asynchronous Timing
Capacitance Derating
The DSP56156 External Bus Timing Specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the External Bus pins (A0-A15, D0-D15, PS/DS, RD, BS, WR, R/W) derates linearly at 1 ns per 12 pF of
additional capacitance from 50 pF to 250 pF of loading. Port B and C pins derate linearly at 1 ns
per 5 pF of additional capacitance from 50 pF to 250 pF of loading.
When an internal memory access follows an external memory access, the PS/DS, R/W, RD
and WR strobes remain deasserted and A0-A15 do not change from their previous state.
28
DSP56156 Data Sheet
For More Information On This Product,
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MOTOROLA
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
External Bus Synchronous Timing
External Bus Synchronous Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
Table 15 lists external bus synchronous timing. Figure 17 and illustrate the bus timings
with no wait states and two wait states, respectively.
Freescale Semiconductor, Inc...
Table 15 External Bus Synchronous Timing
40 MHz
Num
50 MHz
60 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
9
ns
12
ns
34
EXTAL CLK In High to CLKO High
2.4
9
2.4
9
2.4
35
CLKO High to
a. A0-A15 Valid
4.7
12
4.7
12
4.7
4.7
14
4.7
14
4.7
4
ns
18.3
—
13.4
—
9.8
—
ns
T+3.1
T+12.4
T+3.1
T+12.4
T+3.1
T+12.4
ns
14.3
15.8
11.8
13.3
10.2
11.8
ns
b. PS/DS, R/W Valid, BS, RD Asserted
(See Note)
36
BS Width Deasserted
37
CLKO High to WR Asserted Low
38
WR and RD Deasserted High to BS
Asserted Low (2 Successive Bus Cycles)
39
<intentionally blank>
40
CLKO High to BS Deasserted
2.6
10.3
2.6
10.3
2.6
10.3
ns
41
TA Valid to CLKO High (Setup)
4.5
—
4.5
—
4.5
—
ns
42
CLKO High to TA Invalid (Hold)
0
—
0
—
0
—
ns
43
CLKO High to D0-D15 Out Valid
1.7
7.1
1.7
7.1
1.7
7.1
ns
44
CLKO High to D0-D15 Out Invalid
2.0
—
2.0
—
2.0
—
ns
45
D0-D15 In Valid to CLKO Low (Setup)
6
—
6
—
6
—
ns
46
CLKO Low to D0-D15 In Invalid (Hold)
0
—
0
—
0
—
ns
47
CLKO Low to WR, RD Deasserted
—
10
—
10
—
10
ns
48
WR, RD Hold Time from CLKO Low
2.2
—
2.2
—
2.2
—
ns
49
CLKO High to D0-D15 Three-state
0
6
0
6
0
6
ns
50
CLKO High to D0-D15 Out Active
1.2
4.2
1.2
4.2
1.2
4.2
ns
51
CLKO High to A0-A15, PS/DS, R/W Invalid
2.8
—
2.8
—
2.8
—
ns
NOTE:
MOTOROLA
10 ns CL = 25 pF
DSP56156 Data Sheet
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29
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
External Bus Synchronous Timing
T0
T1
T2
T3
T0
T1
T2
EXTAL
(Input)
CLKO
(Output)
34
35
51
Freescale Semiconductor, Inc...
A0-A15
PS/DS
R/W
(See Note)
36
35
BS
(Output)
40
37
WR
(Output)
47
35
48
RD
(Output)
47
48
41
42
41
TA
(Input)
43
D0-D15
(Output)
44
Data Out
49
50
46
45
D0-D15
(Input)
Data In
NOTE: During Read-Modify-Write instructions and internal instructions, the address lines do not change state.
Figure 17 External Bus Synchronous Timing — No Wait States
30
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
External Bus Synchronous Timing
T0
T1
T2
Tw
T2
Tw
T2
T3
T0
EXTAL
(Input)
CLKO
(Output)
34
Freescale Semiconductor, Inc...
35
51
A0-A15,
PS/DS, R/W
(Outputs)
36
35
BS
(Output)
40
37
WR
(Output)
47
48
35
RD
(Output)
47
48
41
41
42
42
TA
(Input)
44
43
D0-D15
(Output)
49
Data Out
50
46
45
D0-D15
(Input)
Data In
Figure 18 External Bus Synchronous Timing – Two Wait States
MOTOROLA
DSP56156 Data Sheet
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31
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
External Bus Asynchronous Timing
External Bus Asynchronous Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
= Clock cycle = 1/2 instruction cycle = 2 T cycles
= Number of Wait States, Determined by BCR Register (WS = 0 to 31)
= WS × cyc = 2T × WS
Freescale Semiconductor, Inc...
cyc
WS
WT
32
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
External Bus Asynchronous Timing
A0-A15,
PS/DS, R/W
(See Note)
60
59
Freescale Semiconductor, Inc...
BS
64
62
67
RD
55
53
52
68
54
66
69
WR
65
63
56
58
D0-D15
57
Data Out
61
Data In
NOTE: During Read-Modify-Write instructions and internal instructions, the address lines do not change state.
Figure 19 External Bus Asynchronous Timing
MOTOROLA
DSP56156 Data Sheet
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33
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Bus Arbitration Timing — Slave Mode
Bus Arbitration Timing — Slave Mode
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
cyc
WS
WT
WX
WP
= Clock cycle = 1/2 instruction cycle = 2 T cycles
= Number of Wait States for external X or P memory, Determined by BCR
Register (WS = 0 to 31)
= WS × cyc=2T × WS
= Number of Wait States for external X memory, Determined by BCR
Register (WS = 0 to 31)
= Number of Wait States for external P memory, Determined by BCR
Register (WS = 0 to 31)
Freescale Semiconductor, Inc...
Table 17 Slave Mode
40/50/60 MHz
Num
NOTES:
34
Characteristics
70
BR Input to CLKO low setup time
71
Delay from BR Input Assertion to
BG Output Assertion
Unit
Min
Max
0
1
ns
(See Note 1)
(See Note 2)
(See Note 3)
5T+1.9
3T+1.9
5T+1.9
ns
(See Note 4)
(See Note 5)
NA
T+1.9
9T+4.2
6T+WT+4.2
26T+4T x WX
+2T x WP+4.2
NA
3T+4.2
1.9
5.2
ns
5T-0.5
2T-0.5
3T-0.5
—
—
—
ns
72
CLKO high to BG Output Assertion
73
BG Output Deassertion Duration
74
CLKO High to Control Bus High Impedance
2.7
6.5
ns
75
CLKO High to BB Output Deassertion
3.2
7.8
ns
76
CLKO High to BB Input
3.3
8.1
ns
77
BR Input Deassertion to
BG Output Deassertion
(See Note 1)
(See Note 5)
(See Note 7)
4T+2.5
3T+3.2
3T+3.2
9T+6.4
8T+7.8
8T+8.0
ns
78
CLKO Low to BG Deassertion
CLKO High to BG Deassertion
CLKO High to BG Deassertion
(See Note 1)
(See Note 5)
(See Note 7)
2.5
3.2
3.2
6.4
7.8
8.0
ns
79
CLKO High to BB Output Active
1.3
3.6
ns
80
CLKO High to BB Output Assertion
2.3
5
ns
81
CLKO High to Address and Control Bus Active
1
3
ns
82
CLKO High to Address and Control Bus Valid
2
4.4
ns
(See Note 1)
(See Note 5)
(See Note 6)
1. With no external access from the DSP56156
2. During external read or write access
3. During external read-modify-write access
4. During Stop mode — external bus is released and BG is always low
5. During Wait mode
6. With external accesses pending by the DSP56156
7. Slave mode, when bus is still busy after bus request has been deasserted
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Bus Arbitration Timing — Slave Mode
CLKO
(Output)
70
Freescale Semiconductor, Inc...
BR
(Input)
71
72
BG
(Output)
73
75
BB
(I/O)
76
A0-A15
PS/DS
R/W
74
D0-D15
74
Figure 20 Bus Arbitration Timing — Slave Mode — Bus Release
MOTOROLA
DSP56156 Data Sheet
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35
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Bus Arbitration Timing — Slave Mode
CLKO
(Output)
70
Freescale Semiconductor, Inc...
BR
(Input)
77
78
BG
(Output)
79
BB
(I/O)
80
82
A0-A15
PS/DS
R/W
81
Figure 21 Bus Arbitration Timing — Slave Mode — Bus Acquisition
36
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Bus Arbitration Timing — Master Mode
Bus Arbitration Timing — Master Mode
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
Table 18 Master Mode
40 MHz
Freescale Semiconductor, Inc...
Num
50 MHz
60 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
85
CLKO High to BR Output Assertion
CLKO High to BR Output Deassertion
4.7
12
4.7
12
4.7
12
ns
86
BG Input Asserted/ Deasserted to CLKO
Low (Setup)
9.2
—
6.5
—
4.5
—
ns
87
CLKO Low to BG Input Invalid (Hold)
0
—
0
—
0
—
ns
88
BB Input Deasserted to CLKO Low (Setup)
9.2
—
6.5
—
4.5
—
ns
89
CLKO Low to BB Input Deasserted (Hold)
0
—
0
—
0
—
ns
90
CLKO High to BB Output Asserted
4.7
12
4.7
12
4.7
12
ns
CLKO
(Output)
85
BR
(Output)
87
BG
(Input)
86
88
BB
(I/O)
Three-state
89
90
82
A0-A15
PS/DS
R/W
81
Figure 22 Bus Arbitration Timing — Master Mode — Bus Acquisition
MOTOROLA
DSP56156 Data Sheet
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37
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Bus Arbitration Timing — Master Mode
CLKO
(Output)
85
Freescale Semiconductor, Inc...
BR
(Output)
86
87
BG
(Input)
75
BB
(I/O)
76
A0-A15
PS/DS
R/W
74
Figure 23 Bus Arbitration Timing — Master Mode — Bus Release
38
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Host Port Timing
Host Port Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
Freescale Semiconductor, Inc...
T = ICYC / 4
cyc = Clock cycle = 1/2 instruction cycle= 2 T cycle
tHSDL = Host Synchronization Delay Time (See Note 1)
tsuh = Host Processor Data Setup Time
Active low lines should be “pulled up” in a manner consistent with the AC and DC specifications.
Table 19 Host Port Timing
40 MHz
Num
50 MHz
60 MHz
Characteristic
100
tHSDL Host Synchronous Delay
(See Note 1)
101
HEN/HACK Assertion Width
• CVR, ICR, ISR Read
• Read
• Write
(See Notes 2, 4)
Unit
Min
Max
Min
Max
Min
Max
T
3T
T
3T
T
3T
2T+36
32+tsuh
32
—
—
2T+33
29+tsuh
29
—
—
2T+30
26+tsuh
26
—
—
31
—
29
—
27
—
ns
ns
ns
102
HEN/HACK Deassertion Width
(See Note 2)
103
Minimum Cycle Time Between Two
HEN Assertion for Consecutive
CVR, ICR, ISR Reads
4T+36
—
4T+33
—
4T+30
—
ns
104
Host Data Input Setup Time before
HEN/HACK Deassertion
5
—
4
—
3
—
ns
105
Host Data Input Hold Time after
HEN/HACK Deassertion
7
—
6
—
5
—
ns
106
HEN/HACK Assertion to Output
Data Active from High Impedance
0
—
0
—
0
—
ns
107
HEN/HACK Assertion to Output
Data Valid
—
32
—
29
—
26
ns
108
HEN/HACK Deassertion to Output
Data High Impedance
—
20
—
18.5
—
17
ns
109
Output Data Hold Time after
HEN/HACK Deassertion
5
—
5
—
4
—
ns
MOTOROLA
DSP56156 Data Sheet
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39
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Host Port Timing
Table 19 Host Port Timing (continued)
40 MHz
Freescale Semiconductor, Inc...
Num
50 MHz
60 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
110
HR/W Low Setup Time before HEN Assertion
6
—
5
—
4
—
ns
111
HR/W Low Hold Time after HEN Deassertion
6
—
5
—
4
—
ns
112
HR/W High Setup Time to HEN Assertion
6
—
5
—
4
—
ns
113
HR/W High Hold Time after HEN/HACK
Deassertion
5
—
4
—
3
—
ns
114
HA0-HA2 Setup Time before HEN Assertion
9
—
7.5
—
6
—
ns
115
HA0-HA2 Hold Time after HEN Deassertion
8
—
7
—
6
—
ns
116
DMA HACK Assertion to HREQ Deassertion
(See Note 3)
5
2T
+37
5
2T
+36
4
2T
+35
ns
117
DMA HACK Deassertion to HREQ
Assertion (See Note 3)
for DMA RXL Read
tHSDL
+3T+5
—
tHSDL
3T+5
—
tHSDL
+3T+4
—
ns
tHSDL
+2T+5
—
—
tHSDL
+2T+5
—
—
tHSDL
+2T+4
—
—
ns
ns
for DMA TXL Write
for All Other Cases
5
5
4
118
Delay from HEN Deassertion to HREQ
Assertion for RXL Read (See Note 3)
tHSDL
+3T+5
—
tHSDL
+3T+5
—
tHSDL
+3T+4
—
ns
119
Delay from HEN Deassertion to HREQ
Assertion for TXL Write (See Note 3)
tHSDL
+2T+5
—
tHSDL
+2T+5
—
tHSDL
+2T+4
—
ns
120
Delay from HEN Assertion to HREQ
Deassertion for RXL Read, TXL Write
(See Note 3)
5
2T
+37
5
2T
+36
5
2T
+35
ns
NOTES:
40
1. “Host Synchronization Delay (tHSDL)” is the time period required for the DSP56156 to sample any
external asynchronous input signal, determine whether it is high or low, and synchronize it to the
internal clock.
2. See Host Port Considerations.
3. HREQ is pulled up by 1 kΩ.
4. Only if two consecutive reads from one of these registers are executed.
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Host Port Timing
External
100
100
Freescale Semiconductor, Inc...
Internal
Figure 24 Host Synchronization Delay
HREQ
(Output)
103
102
101
HACK
(Input)
113
112
HR/W
(Input)
107
108
109
106
H0-H7
(Output)
Data
Valid
Figure 25 Host Interrupt Vector Register (IVR) Read
MOTOROLA
DSP56156 Data Sheet
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41
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Host Port Timing
120
HREQ
(Output)
118
103
HEN
(Input)
RXH
Read
RXL
Read
101
102
114
Freescale Semiconductor, Inc...
HA0-HA2
(Input)
115
Address
Valid
Address
Valid
112
113
HR/W
(Input)
107
108
106
109
Data
Valid
Data
Valid
H0-H7
(Output)
Figure 26 Host Read Cycle (Non-DMA Mode)
HREQ
(Output)
120
119
103
HEN
(Input)
TXH
Write
101
TXL
Write
102
114
HA0-HA2
(Input)
115
Address
Valid
Address
Valid
110
111
HR/W
(Input)
104
H0-H7
(Input)
105
Data
Valid
Data
Valid
Figure 27 Host Write Cycle (Non-DMA Mode)
42
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Host Port Timing
HREQ
(Output)
116
117
102
101
RXH
Read
Freescale Semiconductor, Inc...
HACK
(Input)
RXL
Read
107
108
106
109
H0-H7
(Output)
Data
Valid
Data
Valid
Figure 28 Host Read Cycle (DMA Mode)
HREQ
(Output)
116
117
101
HACK
(Input)
102
TXH
Write
TXL
Write
104
105
H0-H7
(Input)
Data
Valid
Data
Valid
Figure 29 Host Write Cycle (DMA Mode)
MOTOROLA
DSP56156 Data Sheet
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43
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
SSI Timing
Synchronous Serial Interfaces (SSI) Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to + 125°C, CL = 50 pF + 1 TTL Load)
ICYC / 4
Serial Clock Pin
SCx0 Pin
SCx1 Pin
Internal Clock
External Clock
Internal Clock, Asynchronous Mode (Asynchronous
implies that FSR and FST are two different frame syncs)
i ck s = Internal Clock, Synchronous Mode (Synchronous implies
that only one frame sync FS is used)
bl = bit length
wl = word length
Freescale Semiconductor, Inc...
T
SCK
FST (Transmit Frame Sync)
FSR (Receive Frame Sync)
i ck
x ck
i ck a
=
=
=
=
=
=
=
Table 20 Synchronous Serial Interfaces Timing
40/50/60 MHz
Num
Characteristic
Min
Max
Case
Unit
130
Clock Cycle (See Note)
100
—
—
ns
131
Clock High Period
45
—
—
ns
132
Clock Low Period
45
—
—
ns
133
Output Clock Rise/Fall Time
—
7
—
ns
134
SCK Rising Edge to FSR Out
(bl) High
—
—
32
18
x ck
i ck a
ns
135
SCK Rising Edge to FSR Out
(bl) Low
—
—
32
15
x ck
i ck a
ns
136
SCK Rising Edge to FSR Out
(wl) High
—
—
32
15
x ck
i ck a
ns
137
SCK Rising Edge to FSR Out
(wl) Low
—
—
32
15
x ck
i ck a
ns
138
Data In Setup Time before SCK
Falling Edge
30
40
—
—
x ck
i ck
ns
139
Data In Hold Time after SCK
Falling Edge
25
12
—
—
x ck
i ck
ns
NOTE: All the timings for the SSI are given for a non-inverted serial clock polarity (SCKP=0 in CRB) and a noninverted frame sync (FSI=0 in CRB). If the polarity of the clock and/or the frame sync have been inverted,
all the timings remain valid by inverting the clock signal SCK and/or the frame sync FSR/FST in the tables
and in the figures.
44
DSP56156 Data Sheet
For More Information On This Product,
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MOTOROLA
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Freescale Semiconductor, Inc...
SSI Timing
MOTOROLA
DSP56156 Data Sheet
For More Information On This Product,
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45
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
SSI Timing
Table 20 Synchronous Serial Interfaces Timing (continued)
40/50/60MHz
Freescale Semiconductor, Inc...
Num
46
Characteristic
Min
Max
Case
Unit
140
FSR Input (bl) High before SCK
Falling Edge
7
15
—
—
x ck
i ck a
ns
141
FSR Input (wl) High before SCK
Falling Edge
7
15
—
—
x ck
i ck a
ns
142
FSR Input Hold Time after SCK
Falling Edge
15
7
—
—
x ck
i ck a
ns
143
Flags Input Setup before SCK
Falling Edge
7
15
—
—
x ck
i ck
ns
144
Flags Input Hold Time after SCK
Falling Edge
15
7
—
—
x ck
i ck
ns
145
SCK Rising Edge to FST Out
(bl) High
—
—
33
15
x ck
i ck
ns
146
SCK Rising Edge to FST Out
(bl) Low
—
—
30
15
x ck
i ck
ns
147
SCK Rising Edge to FST Out
(wl) High
—
—
30
15
x ck
i ck
ns
148
SCK Rising Edge to FST Out
(wl) Low
—
—
33
15
x ck
i ck
ns
149
SCK Rising Edge to Data Out
Enable from High Impedance
—
—
30
12
x ck
i ck
ns
150
SCK Rising Edge to Data Out Valid
—
—
30
12
x ck
i ck
ns
151
SCK Rising Edge to Data Out High
Impedance
—
—
30
20
x ck
i ck
ns
152
FST Input (bl) Setup Time before SCK
Falling Edge
6
16
—
—
x ck
i ck
ns
153
FST Input (wl) to Data Out Enable from
High Impedance
—
36
—
ns
154
FST Input (wl) Setup Time before SCK
Falling Edge
8
17
—
—
x ck
i ck
ns
155
FST Input Hold Time after SCK
Falling Edge
15
4
—
—
x ck
i ck
ns
156
Flag Output Valid after SCK
Rising Edge
—
—
32
15
x ck
i ck
ns
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
SSI Timing
130
131
Freescale Semiconductor, Inc...
133
132
SCK
(Input/Output)
134
135
FSR (Bit)
Out
136
137
FSR (Word)
Out
138
139
First
Data In
140
Bit
Last Bit
142
FSR (Bit)
In
141
142
143
144
FSR (Word)
In
Flags In
Figure 30 SSI Receiver Timing
MOTOROLA
DSP56156 Data Sheet
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47
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Timer Timing
130
131
133
132
SCK
(Input/Output)
Freescale Semiconductor, Inc...
145
146
FST (Bit)
Out
147
148
FST (Word)
Out
150
150
151
149
Data Out
First Bit
Last Bit
152
155
FST (Bit)
In
153
154
155
FST (Word)
In
156
(See Note)
Flags Out
Figure 31 SSI Transmitter Timing
NOTE: In the Network mode, output flag transitions can occur at the start of each time slot within the frame.
In the Normal mode, the output flag state is asserted for the entire frame period.
48
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
OnCE Port Timing
Timer Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
Table 21 Timer Timing
40/50/60 MHz
Freescale Semiconductor, Inc...
Num
Characteristic
Unit
Min
Max
170
TIN Valid to CLKO Low (Setup time)
6
—
ns
171
CLKO Low to TIN Invalid (Hold time)
0
—
ns
172
CLKO High to TOUT Asserted
3.5
14
ns
173
CLKO High to TOUT Deasserted
5.1
20.7
ns
174
TIN Period
8T
—
ns
175
TIN High/Low Period
4T
—
ns
CLKO
(Output)
170
TIN
(Input)
172
TOUT
(Output)
173
171
Figure 32 Timer Timing
MOTOROLA
DSP56156 Data Sheet
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49
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
OnCE Port Timing
OnCETM Port Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
Table 22 OnCE Port Timing
40/50/60 MHz
Freescale Semiconductor, Inc...
Num
Unit
Min
Max
180
DSCK High to DSO Valid
—
37
ns
181
DSI Valid to DSCK Low (Setup)
5.2
—
ns
182
DSCK Low to DSI Invalid (Hold)
0
—
ns
183
DSCK High
(See Note 1)
2Tc
—
ns
184
DSCK Low
(See Note 1)
2Tc
—
ns
185
DSCK Cycle Time
(See Note 1)
4Tc
—
ns
186
CLKO High to OS0-OS1 Valid
14.5
ns
187
CLKO High to OS0-OS1 Invalid
—
—
ns
188
Last DSCK High to OS0-OS1
Last DSCK High to ACK Active (data)
Last DSCK High to ACK Active (command)
10T+Td+14.5
10T+Td+13.5
21T+Td+13.5
—
—
ns
189
DSO (ACK) Asserted to OS0-OS1 Three-state
—
0
ns
190
DSO (ACK) Asserted to First DSCK High
3Tc
—
ns
191
DSO (ACK) Width Asserted:
• when entering debug mode
• when acknowledging command/data transfer
3T-2
2Tc+0.5
3T-5
2Tc+3
ns
ns
6Tc
—
ns
Td+11.2
—
ns
11T+19.5
—
ns
192
Last DSCK High of Read Register to First
DSCK High of Next Command
193
DSCK High to DSO Invalid
194
DR asserted to DSO (ACK) Asserted
NOTES:
50
Characteristic
(See Note 2)
(See Note 2)
(See Note 2)
(See Note 2)
1. 45%-55% duty cycle
2. Td = DSCK High (Timing #183)
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
OnCE Port Timing
183
DSCK
(Input)
184
Freescale Semiconductor, Inc...
185
Figure 33 OnCE Port Serial Clock Timing
DR
(Input)
194
DSO
(Output)
ACK
Figure 34 OnCE Port Acknowledge Timing
DSCK
(Input)
(Last)
(OS1)
(See Note)
180
193
DSO
(Output)
(ACK)
DSI
(Input)
(OS0)
181
182
188
NOTE: Three-state, external pull-down resistor
Figure 35 OnCE Port Data I/O To Status Timing
MOTOROLA
DSP56156 Data Sheet
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51
Freescale Semiconductor, Inc.
Pin-out and Package
Top View
85
Freescale Semiconductor, Inc...
D1
D0
A15
A14
GND3
A13
A12
A11
GNDQ1
VCC2
A10
GND2
A9
A8
A7
A6
VCCQ1
GND1
A5
A4
VCC1
A3
A2
GND0
A1
A0
MODC
MODB/IRQB
Pin-out and Package Information
1
Orientation Mark
(Top View)
57
MODA/IRQA
RESET
STD0/PC0
SRD0/PC1
SCK0/PC2
SC10/PC3
SC00/PC4
TIN/PC10
VCC7
TOUT/PC11
HA0/PB8
GND10
HA1/PB9
HA2/PB10
HR/W/PB11
HEN/PB12
HACK/PB14
HREQ/PB13
H0/PB0
H1/PB1
STD1/PC5
SRD1/PC6
H4/PB4
H3/PB3
H2/PB2
VCC6
H5/PB5
H6/PB6
MIC
AUX
BIAS
BG
VCCQ0
BR
BB
VCC5
WR
GND8
RD
PS/DS
BS
R/W
DSO
DSCK/OS1
DSI/OS0
CLKO
GNDQ0
GNDS
SXFC
VCCS
EXTAL
SC01/PC9
GND9
SC11/PC8
SCK1/PC7
H7/PB7
29
GND4
D2
D3
VCC3
D4
D5
GND5
D6
D7
D8
D9
GND6
D10
D11
VCC4
D12
D13
GND7
D14
D15
TA
DR
VCCA
SPKP
SPKM
GNDA
VDIV
VREF
NOTE: An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
Figure 39 Top View of the DSP56156 112-pin Plastic (FC) and Ceramic (FE) Quad Flat Packages
52
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
Pin-out and Package
85
1
Orientation Mark
(on Top side)
(Bottom View)
57
GND4
D2
D3
VCC3
D4
D5
GND5
D6
D7
D8
D9
GND6
D10
D11
VCC4
D12
D13
GND7
D14
D15
TA
DR
VCCA
SPKP
SPKM
GNDA
VDIV
VREF
29
MODA/IRQA
RESET
STD0/PC0
SRD0/PC1
SCK0/PC2
SC10/PC3
SC00/PC4
TIN/PC10
VCC7
TOUT/PC11
HA0/PB8
GND10
HA1/PB9
HA2/PB10
HR/W/PB11
HEN/PB12
HACK/PB14
HREQ/PB13
H0/PB0
H1/PB1
STD1/PC5
SRD1/PC6
H4/PB4
H3/PB3
H2/PB2
VCC6
H5/PB5
H6/PB6
H7/PB7
SCK1/PC7
SC11/PC8
GND9
SC01/PC9
EXTAL
VCCS
SXFC
GNDS
GNDQ0
CLKO
DSI/OS0
DSCK/OS1
DSO
R/W
BS
PS/DS
RD
GND8
WR
VCC5
BB
BR
VCCQ0
BG
BIAS
AUX
MIC
Freescale Semiconductor, Inc...
MODB/IRQB
MODC
A0
A1
GND0
A2
A3
VCC1
A4
A5
GND1
VCCQ1
A6
A7
A8
A9
GND2
A10
VCC2
GNDQ1
A11
A12
A13
GND3
A14
A15
D0
D1
Bottom View
NOTE: An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
Figure 40 Bottom View of the DSP56156 112-pin Plastic (FC) and Ceramic (FE) Quad Flat Packages
MOTOROLA
DSP56156 Data Sheet
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53
Freescale Semiconductor, Inc.
Pin-out and Package
General Purpose I/O
Table 23 DSP56156 General Purpose I/O Pin Identification
Freescale Semiconductor, Inc...
112-pin
Package
Pin #
NOTES:
DSP56156
Primary Pin
Function
DSP56156
General
Purpose I/O
ID
66
H0
PB0
65
H1
PB1
60
H2
PB2
61
H3
PB3
62
H4
PB4
58
H5
PB5
57
H6
PB6
56
H7
PB7
74
HA0
PB8
72
HA1
PB9
71
HA2
PB10
70
HR/W
PB11
69
HEN
PB12
67
HREQ
PB13
68
HACK
PB14
82
STD0
PC0
81
SRD0
PC1
80
SCK0
PC2
79
SC10
PC3
78
SC00
PC4
64
STD1
PC5
63
SRD1
PC6
55
SCK1
PC7
54
SC11
PC8
52
SC01
PC9
77
TIN
PC10
75
TOUT
PC11
1. In Tables 23, 24, and 25, OVERBAR indicates the signal is asserted when the voltage = ground (active low).
2. For more information on power and ground, see Table 26 under Design Considerations.
54
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
Pin-out and Package
Freescale Semiconductor, Inc...
Pin Number
MOTOROLA
DSP56156 Data Sheet
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55
Freescale Semiconductor, Inc.
Pin-out and Package
Signal Name
Table 24 DSP56156 Pin Identification by Pin Number
Freescale Semiconductor, Inc...
112-pin
Package
Pin #
56
Signal Name
112-pin
Package
Pin #
Signal Name
112-pin
Package
Pin #
Signal Name
1
GND4
39
RD
76
VCC7
2
D2
40
PS/DS
77
TIN/PC10
3
D3
41
BS
78
SC00/PC4
4
VCC3
42
R/W
79
SC10/PC3
5
D4
43
DSO
80
SCK0/PC2
6
D5
44
DSCK/OS1
81
SRD0/PC1
7
GND5
45
DSI/OS0
82
STD0/PC0
8
D6
46
CLKO
83
RESET
9
D7
47
GNDQ0
84
MODA/IRQA
10
D8
48
GNDS
85
MODB/IRQB
11
D9
49
SXFC
86
MODC
12
GND6
50
VCCS
87
A0
13
D10
51
EXTAL
88
A1
14
D11
52
SC01/PC9
89
GND0
15
VCC4
53
GND9
90
A2
16
D12
54
SC11/PC8
91
A3
17
D13
55
SCK1/PC7
92
VCC1
18
GND7
56
H7/PB7
93
A4
19
D14
57
H6/PB6
94
A5
20
D15
58
H5/PB5
95
GND1
21
TA
59
VCC6
96
VCCQ1
22
DR
60
H2/PB2
97
A6
23
VCCA
61
H3/PB3
98
A7
24
SPKP
62
H4/PB4
99
A8
25
SPKM
63
SRD1/PC6
100
A9
26
GNDA
64
STD1/PC5
101
GND2
27
VDIV
65
H1/PB1
102
A10
28
VREF
66
H0/PB0
103
VCC2
29
MIC
67
HREQ/PB13
104
GNDQ1
30
AUX
68
HACK/PB14
105
A11
31
BIAS
69
HEN/PB12
106
A12
32
BG
70
HR/W/PB11
107
A13
33
VCCQ0
71
HA2/PB10
108
GND3
34
BR
72
HA1/PB9
109
A14
35
BB
73
GND10
110
A15
36
VCC5
74
HA0/PB8
111
D0
37
WR
75
TOUT/PC11
112
D1
38
GND8
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
Pin-out and Package
Freescale Semiconductor, Inc...
Signal Name
MOTOROLA
DSP56156 Data Sheet
For More Information On This Product,
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57
Freescale Semiconductor, Inc.
Pin-out and Package
Table 25 DSP56156 Pin Identification by Signal Name
Freescale Semiconductor, Inc...
112-pin
Package
Pin #
58
Signal Name
112-pin
Package
Pin #
Signal Name
112-pin
Package
Pin #
Signal Name
87
A0
6
D5
47
GNDQ0
88
A1
8
D6
104
GNDQ1
90
A2
9
D7
48
GNDS
91
A3
10
D8
66
H0
93
A4
11
D9
65
H1
94
A5
13
D10
60
H2
97
A6
14
D11
61
H3
98
A7
16
D12
62
H4
99
A8
17
D13
58
H5
100
A9
19
D14
57
H6
102
A10
20
D15
56
H7
105
A11
22
DR
74
HA0
106
A12
44
DSCK
72
HA1
107
A13
45
DSI
71
HA2
109
A14
43
DSO
68
HACK
110
A15
51
EXTAL
69
HEN
30
AUX
89
GND0
70
HR/W
35
BB
95
GND1
67
HREQ
32
BG
101
GND2
84
IRQA
31
BIAS
108
GND3
85
IRQB
34
BR
1
GND4
29
MIC
41
BS
7
GND5
84
MODA
46
CLKO
12
GND6
85
MODB
111
D0
18
GND7
86
MODC
112
D1
38
GND8
45
OS0
2
D2
53
GND9
44
OS1
3
D3
73
GND10
66
PB0
5
D4
26
GNDA
65
PB1
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Pin-out and Package
MOTOROLA
DSP56156 Data Sheet
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59
Freescale Semiconductor, Inc.
Pin-out and Package
Table 25 DSP56156 Pin Identification by Signal Name (continued)
Freescale Semiconductor, Inc...
112-pin
Package
Pin #
60
Signal Name
112-pin
Package
Pin #
Signal Name
112-pin
Package
Pin #
Signal Name
60
PB2
55
PC7
64
STD1
61
PB3
54
PC8
49
SXFC
62
PB4
52
PC9
21
TA
58
PB5
77
PC10
77
TIN
57
PB6
75
PC11
75
TOUT
56
PB7
40
PS/DS
92
VCC1
74
PB8
42
R/W
103
VCC2
72
PB9
39
RD
4
VCC3
71
PB10
83
RESET
15
VCC4
70
PB11
78
SC00
36
VCC5
69
PB12
52
SC01
59
VCC6
67
PB13
79
SC10
76
VCC7
68
PB14
54
SC11
23
VCCA
82
PC0
80
SCK0
33
VCCQ0
81
PC1
55
SCK1
96
VCCQ1
80
PC2
25
SPKM
50
VCCS
79
PC3
24
SPKP
27
VDIV
78
PC4
81
SRD0
28
VREF
64
PC5
63
SRD1
37
WR
63
PC6
82
STD0
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
Pin-out and Package
Freescale Semiconductor, Inc...
112 CQFP
MOTOROLA
DSP56156 Data Sheet
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61
Freescale Semiconductor, Inc.
Pin-out and Package
TOP
VIEW
S
0.20 (0.008) M T L-M S N S
A
0.20 (0.008) M T L-M S N S
PIN 1
Identifier
112
J1
85
28
S
N
S
-L-, -M-, -NVIEW Y
3 Place
M
T L-M
S
S
V
P
0.20 (0.008)
B
T L-M
-M-
0.20 (0.008)
Freescale Semiconductor, Inc...
-L-
M
84
VIEW Y
N
J1
1
PLATING
F
57
B1
J
29
56
-N-
BASE
METAL
D
C
0.127 (0.005)
VIEW P
E
M
T L-M
S
N
S
SECTION J1-J1
112 Place
VIEW ROTATED 90°
DATUM
-H- PLANE
W
0.15 (0.006)
-T- SEATING
G 108 Place
PLANE
Case 915-01
A1
θ1
R R1
DATUM -HPLANE
MILLIMETERS
MIN
MAX
18.880 20.400
18.880 20.400
2.740
3.450
0.220
0.380
2.340
3.060
0.220
0.330
INCHES
MIN
MAX
0.743
0.803
0.743
0.803
0.108
0.135
0.009
0.015
0.092
0.120
0.009
0.013
J
0.650 BSC
0.130
0.230
0.0256 BSC
0.005
0.009
K
0.650
0.026
DIM
A
R R2
θ2
B
C
D
E
F
G
K
C1
P
VIEW P
NOTES:
S
V
1. Dimensioning and tolerancing per ANSI Y14.5M, 1982.
2. Controlling dimension: millimeter.
3. Datum plane -H- is coincident with the bottom of the lead
where the lead exits the ceramic body.
4. Datums -L-, -M- and -N- to be determined at datum plane -H-.
5. Dimensions S and V to be determined at seating plane -T-.
6. Dimensions A and B define maximum ceramic body dimensions
including glass protrusion and mismatch.
W
A1
B1
C1
R1
R2
θ1
θ2
0.950
0.037
0.325 BSC
22.950 23.450
0.0128 BSC
0.904
0.923
22.950
0.300
23.450
0.904
0.012
0.200
0.600
0.120
0.132
1.800 REF
0.200 REF
0.008
0.0047
0.200 REF
8°
0°
8°
0°
0.923
0.024
0.0052
0.070 REF
0.008 REF
0.008 REF
8°
0°
8°
0°
NOTE: BSC = Between Statistical Center
(i.e., typical)
Figure 41 DSP56156 112-pin Ceramic Quad Flat Pack (CQFP) Mechanical Information
62
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
Pin-out and Package
Freescale Semiconductor, Inc...
112 TQFP
MOTOROLA
DSP56156 Data Sheet
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63
Freescale Semiconductor, Inc.
Pin-out and Package
0.200 (0.008) H L-M N
4x
PIN 1
Identifier
J1
0.200 (0.008) T L-M N
4x 28 TIPS
85
112
4x P
-L-, -M-, -N-
J1
1
84
VIEW Y
108x G
-M-
-L-
VIEW Y
B
V
J
AA
Freescale Semiconductor, Inc...
B1 V1
28
29
0.13 (0.005)
56
TOP
VIEW
-NA1
BASE
METAL
F
D
57
M
T L -M
M
C
M
SECTION J1-J1
(VIEW ROTATED 90° COUNTER CLOCKWISE)
S1
A
S
C2
0.050 (0.002)
C
θ2
S
0.100 (0.004)
-H-
-T- SEATING
PLANE
θ3
θ
R2
0.25 (0.010)
R1
GAGE PLANE
K
C1
E
Y
θ1
Z
VIEW AB
NOTES:
Case 987-01
VIEW AB
1. Dimensioning and tolerancing per ANSI Y14.5M, 1982.
2. Controlling dimension: Millimeter.
3. Datum plane -H- is located at bottom of lead and is coincident with the lead
where the lead exits the plastic body at the bottom of the parting line.
4. Datums -L-, -M- and -N- to be determined at datum plane -H-.
5. Dimensions S and V to be determined at seating plane -T-.
6. Dimensions A and B do not include mold protrusion. Allowable protrusion is
0.25 (0.010) per side. Dimensions A and B do include mold mismatch and are
determined at datum plane -H-.
7. Dimension D does not include dambar protrusion. Allowable dambar
protrusion shall not cause the D dimension to exceed 0.43 (0.017).
MILLIMETERS
DIM
A
A1
INCHES
MIN
MAX
20.000 BSC
10.000 BSC
MIN
MAX
0.790 BSC
0.395 BSC
B
20.000 BSC
0.790 BSC
B1
10.000 BSC
0.395 BSC
C
C1
1.400
0.050
1.600
0.150
0.055
0.002
0.063
0.006
C2
1.350
1.450
0.053
0.057
D
0.270
0.370
0.011
0.014
E
0.450
0.750
0.018
0.030
F
G
0.270
0.330
0.650 BSC
0.011
0.013
0.0256 BSC
J
0.115
0.006
0.175
0.007
K
0.500 BSC
0.020 BSC
P
R1
0.325 BSC
0.100
0.200
0.013 BSC
0.004
0.008
R2
0.100
0.004
0.200
0.008
S
22.000 BSC
0.866 BSC
S1
V
11.000 BSC
22.000 BSC
0.433 BSC
0.866 BSC
V1
11.000 BSC
0.433 BSC
Y
0.250 REF
0.010 REF
Z
AA
1.000 REF
0.115
0.135
0.039 REF
0.004
0.005
θ
θ1
0°
3°
8°
7°
0°
3°
8°
7°
θ2
11°
13°
11°
13°
θ3
11°
13°
11°
13°
NOTE: BSC = Between Statistical Center
(i.e., typical)
Figure 42 DSP56156 112-pin Plastic Thin Quad Flat Pack (TQFP) Mechanical Information
64
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
Design Considerations
Heat Dissipation
Power, Ground, and Noise
Design Considerations
Heat Dissipation
The average chip junction temperature, TJ, in
°C, can be obtained from:
TJ = TA + (PD × ΘJA)
(1)
Freescale Semiconductor, Inc...
Where:
TA = ambient temperature, °C
ΘJA = package thermal resistance,
junction-to-ambient, °C/W
PD = PINT + PI/O
PINT = ICC × VCC watts — chip internal
power
PI/O = power dissipation on input and
output pins — user determined
For most applications PI/O < PINT and PI/O can
be neglected. An appropriate relationship between PD and TJ (if PI/O is neglected) is:
PD = K/(TJ + 273)
ΘJC is device-related and cannot be influenced by the user. However, ΘCA is user-dependent and can be minimized by such
thermal management techniques as heat
sinks, ambient air cooling, and thermal convection. Thus, good thermal management on
the part of the user can significantly reduce
ΘCA so that ΘJA approximately equals ΘJC.
Substitution of ΘJC for ΘJA in equation (1) will
result in a lower semiconductor junction
temperature. Values for thermal resistance
presented in this document, unless estimated, were derived using the procedure described in Motorola Reliability Report 7843,
“Thermal Resistance Measurement Method
for MC68XX Microcomponent Devices”, and
are provided for design purposes only. Thermal measurements are complex and dependent on procedure and setup. User-derived
values for thermal resistance may differ.
(2)
Solving equations (1) and (2) for K gives:
K = PD × (TA + 273) + PD × ΘJA
(3)
Where K is a constant pertaining to the particular package. K can be determined from
equation (2) by measuring PD (at equilibrium) for a known TA. Using this value of K, the
values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any
value of TA. The total thermal resistance of a
package (ΘJA) can be separated into two components, ΘJC and ΘCA, representing the barrier
to heat flow from the semiconductor junction
to the package (case) surface (ΘJC) and from
the case to the outside ambient (ΘCA). These
terms are related by the equation:
ΘJA = ΘJC + ΘCA
60
(4)
Power, Ground, and
Noise
Each DSP56156 VCC pin should be provided
with a low-impedance path to +5 volts. Each
DSP56156 GND pin should likewise be provided with a low-impedance path to ground.
The power supply pins drive distinct groups
of logic on chip as shown in Table 26.
The VCC power supply should be bypassed to GND ground using at least six
0.01 – 0.1 µF bypass capacitors located either underneath the chip’s socket or as close
as possible to the four sides of the package.
The capacitor leads and the associated
printed circuit traces connecting to chip VCC
and GND should be kept to less than 0.5” per
DSP56156 Data Sheet
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Freescale Semiconductor, Inc.
Design Considerations
Freescale Semiconductor, Inc...
Power, Ground, and Noise
device loads as well as parasitic capacitances due to PCB traces. Attention to proper
PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the VCC and
GND circuits.
capacitor lead. The use of at least a four layer board is recommended, employing two
inner layers as VCC and GND planes. All
output pins on this DSP have fast rise and
fall times. Printed Circuit Board (PCB)
trace length should be minimized in order
to minimize undershoot and reflections
caused by these fast output switching
times. This recommendation particularly
applies to the address and data buses as
well as the PS/DS, BS, RD, WR, R/W, interrupt, and HEN pins. Maximum PCB trace
lengths on the order of 6" are recommended.
Capacitance calculations should consider all
Clock signals should not be run across
many signals and should be kept away
from analog power and ground traces as
well as any analog signals. See Figure 44 for
more details.
Table 26 Power and Ground Connections
Power
Circuitry
Ground
Signal
Name
Pin #
Address Bus Buffers
VCC1
VCC2
92
103
GND0
GND1
GND2
GND3
89
95
101
108
Data Bus Buffers
VCC3
VCC4
4
15
GND4
GND5
GND6
GND7
1
7
12
18
Bus Control Buffers
VCC5
36
GND8
38
Codec
VCCA
23
GNDA
26
Digital Peripherals
VCC6
VCC7
59
76
GND9
GND10
53
73
Internal logic
VCCQ0
VCCQ1
33
96
GNDQ0
GNDQ1
47
104
Phase-Locked Loop (PLL)
VCCS
50
GNDS
MOTOROLA
Signal
Name
DSP56156 Data Sheet
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Pin #
48
61
Freescale Semiconductor, Inc.
Design Considerations
Power Consumption
Power Consumption
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
Freescale Semiconductor, Inc...
The DC electrical characteristics of this device are shown in Table 27. Power consumption is
application dependant. The data in Table 27 is collected by running the following code using
internal memory after having programmed all pins of port B and C as input and after having
three-stated the data bus (MC = 0 in OMR) and pulled high:
loop
move
move
move
move
clr
move
move
rep
mac
move
move
jmp
#0,r0
#0,r3
#$100,r2
#$00ff,m0
a
x:(r0)+,a
a1,a0
#30
x0,y0,a
a,p:(r2)
#0,r3
loop
;initial value to accumulator
x:(r3)+,x0
;mac on typical data
;store the mac result
Table 27 DC Electrical Characteristics
Typical
Conditions
Symbol
40
MHz
50
MHz
60
MHz
Unit
Digital current with Codec and PLL disabled
ICC
91
112
133
mA
Digital current Wait Mode with Codec
and PLL disabled
ICC
12
14
17
mA
Digital current Wait Mode with Codec Enabled
and PLL disabled
ICC
92
113
134
mA
Stop mode with PLL and CLKO disabled
ICC
—
250
—
µA
Digital current drawn by the PLL when active
ICC
—
1
—
mA
Digital current drawn by CLKO when active
ICC
—
3.6
—
mA
Analog current with Codec enabled
ICCA
—
12
—
mA
Analog current with Codec disabled
ICCA
—
70
—
µA
To minimize the power dissipation, all unused digital input pins should be tied inactive to
ground or power; and all unused I/O pins should be tied inactive through a 10K¾ resistor to
ground or power. When the codec is not used, GNDA should be connected to GND; and VCCA
should be connected to VCC. Also, all codec pins should be left floating, except VREF which
should still be decoupled.
62
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
Design Considerations
Host Port Considerations
Freescale Semiconductor, Inc...
Host Port
Considerations
Careful synchronization is required when
reading multi-bit registers that are written by
another asynchronous system. This is a common problem when two asynchronous systems are connected. The situation exists in
the host interface. The considerations for
proper operation are discussed below.
Host Programming
Considerations
1. Unsynchronized Reading of
Receive Byte Registers
When reading receive byte registers,
RXH or RXL, the host program should
use interrupts or poll the RXDF flag
which indicates that data is available.
This assures that the data in the receive
byte registers will be stable.
2. Overwriting Transmit Byte Registers
The host program should not write to the
transmit byte registers, TXH or TXL, unless the TXDE bit is set indicating that the
transmit byte registers are empty. This
guarantees that the transmit byte registers will transfer valid data to the HRX
register.
3. Synchronization of Status Bits from
DSP to Host
HC, HREQ, DMA, HF3, HF2, TRDY,
TXDE, and RXDF status bits are set or
cleared from inside the DSP and read by
the host processor (refer to DSP56156 User’s Manual, I/O Interface section, Host/
DMA Interface Programming Model for
descriptions of these status bits). The
host can read these status bits very quickly without regard to the clock rate used
MOTOROLA
by the DSP, but the possibility exists that
the state of the bit could be changing during the read operation. This is generally
not a system problem, since the bit will
be read correctly in the next pass of any
host polling routine.
However, if the host asserts HEN for
more than timing number 101 (T101),
with a minimum cycle time of timing
number 103 (T103), then these status bits
are guaranteed to be stable. Care must
be exercised when reading status bits
HF3 and HF2 as an encoded pair. If the
DSP changes HF3 and HF2 from 00 to 11,
there is a small probability that the host
could read the bits during the transition
and receive 01 or 10 instead of 11. If the
combination of HF3 and HF2 has significance, the host could read the wrong
combination. Therefore, read the bits
twice and check for consensus.
4. Overwriting the Host Vector
The host program should change the
Host Vector register only when the Host
Command bit (HC) is clear. This change
will guarantee that the DSP interrupt
control logic will receive a stable vector.
5. Cancelling a Pending Host Command
Exception
The host processor may elect to clear the
HC bit to cancel the host command exception request at any time before it is
recognized by the DSP. Because the host
does not know exactly when the exception will be recognized (due to exception
processing synchronization and pipeline
delays), the DSP may execute the host
command exception after the HC bit is
cleared. For these reasons, the HV bits
must not be changed at the same time
that the HC bit is cleared.
DSP56156 Data Sheet
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Freescale Semiconductor, Inc.
Design Considerations
DSP Programming Considerations
Bus Operation
DSP Programming
Considerations
2. Reading HF0 and HF1 as an
Encoded Pair
1. Synchronization of Status Bits
from Host to DSP
Care must be exercised when reading
status bits HF0 and HF1 as an encoded pair, i.e., the four combinations 00,
01, 10, and 11 each have significance.
A very small probability exists that
the DSP will read the status bits synchronized during transition. Therefore, HF0 and HF1 should be read
twice and checked for consensus.
Freescale Semiconductor, Inc...
DMA, HF1, HF0, and HCP, HTDE,
and HRDF status bits are set or
cleared by the host processor side of
the interface. These bits are individually synchronized to the DSP clock.
(Refer to the DSP56156 User’s Manual,
I/O Interface section, Host/DMA Interface Programming Model for descriptions of these status bits.)
Bus Operation
Figure 43 depicts the operation of the external memory interface with multiple wait states.
T0 T1
T2 Tw T2
Tw
T2 Tw
T2
T3
T0 T1
T2
Tw
T2
Tw
T2 Tw T2
T3 T0
T1
T
CLKO
BS
PS/DS
A0-A15
R/W
WR
RD
D0-D15
Data in
Data out
Figure 43 Read and Write Bus Operation (3 Wait States)
64
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
Design Considerations
Analog I/O Considerations
Analog I/O Considerations
MGS1-0 bits
1 µF
5.6 KΩ
VREF
600 Ω
-6 dB
6 dB
MIC
5.6 KΩ
VREF
0.001 µF
600 Ω
INS bit
MUX
Freescale Semiconductor, Inc...
Figure 44 describes the recommended analog I/O and power supply configurations. The two
analog inputs are electrically identical. When one is not used, it can be left floating. When
used, an AC coupling capacitor is required. The value of the capacitor along with the input
impedance of the pin determine the cut off frequency of a high pass filter. The input impedance of the MIC and AUX varies as a function of the sigma-delta (²ý) modulator master clock.
78 kΩ is a typical value at 2 MHz. An AC capacitor of 1µF defines a high pass filter pole of 2
Hz. A smaller capacitor value will move this pole higher in frequency.
VCCA
AUX
Σ∆
modulator
1 µF
0.001 µF
RBias
(to microphone)
+
15 µF
Bias
17 dB
GNDA
10 KΩ
(≤ ±1mA)
VREF
2.0 V ±10%
(2/5 VCC)
0.1 µF
VDIV
GNDA
Š10 µF
54 KΩ
36 KΩ
SPKP
ð50 nF
3 POLE
2 ZERO
Low Pass
Filter (LPF)
Š1 KΩ
SPKM
VC3-VC0
+5 dB
digital VCC
digital GND
0.01 µF
15 µF
220 µF
+
GND
External
GND
VCCA
Single trace
+
+5 V
External Supply
GNDA
GNDA
0.1 µF
Analog Decoupling
near DSP
Single trace
Figure 44 Recommended Analog I/O Configuration
MOTOROLA
DSP56156 Data Sheet
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65
Freescale Semiconductor, Inc.
Design Considerations
Analog I/O Considerations
Figure 45 shows three possible single-ended output configurations. Configuration (a) is highly
recommended. For configurations (b) and (c), an AC coupling capacitor is required since the
load resistor is tied to GNDA.
47 K¾
VREF
VCCA
SPKP
Freescale Semiconductor, Inc...
+
-
0 < C ð 100 nF
SPKP
0 < C ð 100 nF
SPKP
47 K¾
Š 500 Ω
Š 500 Ω
47 K¾
SPKM
GNDA
NC
SPKM
0 < C ð 100 nF
SPKM
Š 500 Ω
47 K¾
(a)
(b)
(c)
Figure 45 Single-ended Output Configurations
Figure 46 shows a recommended layout for power and ground planes.
57
1
28
29
112
85
56
84
Digital Ground and
Power planes
Analog Ground and
Power planes
Figure 46 Ground and Power planes
66
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
Design Considerations
Analog I/O Considerations
A four level board is recommended. The top layer (directly under the parts) and the bottom
layer should be interconnect layers. The two center layers should be power and ground.
Ground and power planes should be completely separated. The digital and analog power/
ground planes should not overlap. All codec pins should be over the analog planes. The analog planes should not encompass any digital pins. All codec signal traces should be over the
analog planes.
Freescale Semiconductor, Inc...
Figure 47 shows that 0.1 µF bypass caps should be located as close to the pins being bypassed
as possible. The ground side of these caps should be connected as close as possible to the VCCA
pin. The ground side of the bypass cap should be connected to the VCCA pin by short traces.
VREF
VDIV
VCCA
SPKM
SPKP
GNDA
BIAS
AUX
MIC
29
28
0.1 µF
10 kΩ
0.1 µF
65 µF
Š10 µF
25 µF
Figure 47 Suggested Top Layer Bypassing
The pins with 0.1 µF bypass caps are VREF and GNDA. The largest size practical bypass
caps should also be added for each of these pins as well as for the VDIV pin; 10 µF bypass
caps should be considered a minimum value for the larger caps (65 µF on VDIV may be
used). These caps should be near the package but do not have to be right next to the pins.
The DAC outputs (SPKP and SPKM) should be run right next to each other as shown on Figure 48.
MOTOROLA
DSP56156 Data Sheet
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Freescale Semiconductor, Inc.
Design Considerations
Analog I/O Considerations
Freescale Semiconductor, Inc...
VREF
VDIV
VCCA
SPKM
SPKP
MIC IN
MIC
28
47 kΩ
0.25 µF
AUX
29
GNDA
BIAS
1nF
5.6 kΩ
47 kΩ
47 kΩ
Copper Fill of unused board space
should be connected to the analog ground plane.
47 kΩ
SPK OUT
Figure 48 Suggested Bottom Layer Routing
The output should be used differentially if at all possible. Analog signal traces should be
shielded by running traces connected to analog ground next to them. Unused board area on
both interconnect levels should be copper filled and connected to analog ground. The copper
fill is only shown on this page for clarity and simplicity. The ADC input anti-aliasing should
be done with respect to VREF.
Figure 49 presents four options for good power supply connections.
68
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc.
Design Considerations
Analog I/O Considerations
VDIV
VREF
GNDA
SPKP
SPKM
VCCA
VDIV
VREF
BIAS
AUX
MIC
28
28
Voltage
Regulator
Voltage
Regulator
Ideal Choice — Two separate power supplies.
Second Choice — One power supply.
Ground planes connected with a single trace as
close as possible to the V CCA pin on the codec.
Two regulators, one for the digital supply, one for
the analog supply. Ground planes connected with
a 10 ¾ resistor as close as possible to the VCCA
pin on the codec.
10Ω
10Ω
GNDA
SPKP
SPKM
VCCA
VDIV
VREF
GNDA
SPKP
SPKM
VCCA
VDIV
VREF
BIAS
AUX
MIC
29
BIAS
AUX
MIC
29
Freescale Semiconductor, Inc...
29
29
BIAS
AUX
MIC
GNDA
SPKP
SPKM
VCCA
10Ω
28
28
Voltage
Regulator
Third Choice — One power supply.
One regulator for the analog supply. Digital supplies driven directly by voltage source. Ground
planes connected with a 10 ¾ resistor as close as
possible to the VCCA pin on the codec.
Fourth Choice — One power supply. Ground
planes connected at source. Ground planes
connected with a 10 ¾ resistor as close as possible to the VCCA pin on the codec.
Figure 49 Four Possible Power Supply Connections
MOTOROLA
DSP56156 Data Sheet
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Freescale Semiconductor, Inc.
Ordering Information
Ordering Information
Table 28 lists information for ordering parts.
Table 28 DSP56156 Ordering Information
Freescale Semiconductor, Inc...
Supply
Voltage
5V
5V
70
Package Type
Pin Count
Ceramic Quad Flat
Pack (CQFP)
112
Plastic Thin Quad
Flat Pack (TQFP)
112
Frequency
(MHz)
Order Number
40
DSP56156FE40
60
DSP56156FE60
40
DSP56156FV40
60
DSP56156FV60
DSP56156 Data Sheet
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MOTOROLA
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume
any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights
of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal
injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and M are registered trademarks of Motorola, Inc. Motorola, Inc.
is an Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers:
USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
EUROPE: Motorola Ltd.; European Literature Center; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.
JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan.
ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbor Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T.,
Hong Kong.
MOTOROLA
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