Mitsubishi M5M512R88DJ-10 1048576-bit (131072-word by 8-bit) cmos static ram Datasheet

MITSUBISHI LSIs
1998.6.18 Ver.A
M5M512R88DJ-10,-12,-15
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M512R88DJ is a family of 131072-word by 8-bit
static RAMs, fabricated with the high performance CMOS
A0 1
A1 2
inputs
application.
A2 3
A3 4
These devices operate on a single 3.3V supply, and are chip select
S 5
input
directly TTL compatible. They include a power down
inputs/ DQ1 6
data
DQ2 7
feature as well.
outputs
(3.3V) VCC 8
(0V) GND 9
FEATURES
data
DQ3 10
•Fast access time
M5M512R88DJ-10 ... 10ns(max)
inputs/
DQ4 11
M5M512R88DJ-12 ... 12ns(max)
outputs
M5M512R88DJ-15 ... 15ns(max)
write control W 12
input
•Low power dissipation
Active .................... 297mW(typ)
A4 13
address
A5 14
inputs
•Single +3.3V power supply
A6 15
•Fully static operation : No clocks, No refresh
A7 16
•Common data I/O
•Easy memory expansion by S
•Three-state outputs : OR-tie capability
Outline
•OE prevents data contention in the I/O bus
•Directly TTL compatible : All inputs and outputs
A16
A
inputs
30 A14
29 A13 output enable
28 OE input
data
27 DQ8
inputs/
26 DQ7
outputs
25 GND (0V)
24 VCC (3.3V)
data
23 DQ6
inputs/
22 DQ5
outputs
21 A12
20 A11
address
19
A10
inputs
18 A9
17 A8
32
silicon gate process and designed for high speed
address
31
15
address
32P0K
PACKAGE
APPLICATION
M5M512R88DJ
High-speed memory units
: 32pin 400mil SOJ
BLOCK DIAGRAM
A0
1
A1
A2
2
A3
address
inputs
6
3
MEMORY ARRAY
512 ROWS
2048 COLUMNS
4
A4 13
A5 14
A6 15
A7 16
A8 17
DQ1
7
DQ2
10
DQ3
11
DQ4
22
DQ5
23
DQ6
26
DQ7
27
DQ8
data
inputs/
outputs
COLUMN I/O CIRCUITS
S
W
5
12
COLUMN
COLUMNADDRESS
DECODERS
ADDRESS
DECODERS
COLUMN INPUT BUFFERS
OE 28
8
24
9
25
VCC (3.3V)
GND (0V)
18 19 20 21 29 30 31 32
A9 A10 A11 A12 A13 A14 A15 A16
address
inputs
MITSUBISHI
ELECTRIC
1
MITSUBISHI LSIs
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M512R88DJ is determined by
a combination of the device control inputs S, W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W
overlaps with the low level S. The address must be set-up
before the write cycle and must be stable during the entire
cycle.
The data is latched into a cell on the trailing edge of W or
S, whichever occurs first, requiring the set-up and hold time
relative to these edge to be maintained. The output enable
input OE directly controls the output stage. Setting the OE at
a high level, the output stage is in a high impedance state,
and the data bus
contention problem in the write cycle is eliminated.
A read cycle is excuted by setting W at a high level and
OE at a low level while S are in an active state (S=L).
When setting S at high level, the chip is in a nonselectable mode in which both reading and writing are
disable. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips and
memory expansion by S.
Signal-S controls the power-down feature. When S goes
high, power dissapation is reduced extremely. The access
time from S is equivalent to the address access time.
FUNCTION TABLE
S
H
W
X
OE
X
L
L
X
L
H
L
L
H
H
Mode
Non selection
DQ
High-impedance
Icc
Stand by
Write
Din
Active
Read
Dout
Active
High-impedance
Active
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
V cc
Supply voltage
VI
Input voltage
VO
Output voltage
Pd
Power dissipation
T opr
Operating temperature
Conditions
With respect to GND
Ta=25°C
Ratings
Unit
- 2.0 *~ 4.6
- 2.0*~ VCC+0.5
V
- 2.0*~ VCC
V
V
1000
mW
0 ~ 70
°C
Tstg(bias) Storage temperature(bias)
- 10 ~ 85
°C
T stg
- 65 ~ 150
°C
* Pulse
Storage temperature
width≤5ns, In case of DC: - 0.5V
DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70°C, Vcc=3.3V
Symbol
VIH
VIL
VOH
VOL
II
Parameter
+10%
- 5%
,unless otherwise noted)
Limits
Condition
Min
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input current
Typ
2.0
I OZ
I OH = - 4mA
IOL = 8mA
VI= 0 ~ Vcc
VI(S)=VIH
Output current in off-state VI/O= 0 ~ Vcc
I CC1
Active supply current
(TTL level)
Max
0.4
2
V
V
V
V
uA
2
uA
Vcc+0.3
0.8
2.4
VI(S)=VIL
other inpus=VIH or VIL
Output-open(duty 100%)
I CC2
Stand by current
(TTL level)
VI(S)=VIH
I CC3
Stand by current
VI(S)=Vcc≥0.2V
other inputs VI≤0.2V
or VI ≥Vcc - 0.2V
10ns cycle
AC 12ns cycle
15ns cycle
DC
10ns cycle
AC 12ns cycle
15ns cycle
DC
90
Unit
180
170
160
100
60
55
50
30
10
mA
mA
mA
Note 1: Direction for current flowing into an IC is positive (no mark).
MITSUBISHI
ELECTRIC
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MITSUBISHI LSIs
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
CAPACITANCE (Ta=0~70°C, Vcc=3.3V
Symbol
Parameter
+10%
-5%
,unless otherwise noted)
Test Condition
Min
Limit
Typ
Max
Unit
CI
Input capacitance
V I =GND, V I =25mVrms,f=1MHz
6
pF
CO
Output capacitance
V O=GND, V O=25mVrms,f=1MHz
8
pF
Note 2: CI,CO are periodically sampled and are not 100% tested.
AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V
+10%
-5%
,unless otherwise noted)
(1)MEASUREMENT CONDITION
Input pulse levels .................................... VIH=3.0V, VIL=0.0V
Input rise and fall time .................................................... 3ns
Input timing reference levels ........................ VIH=1.5V, VIL=1.5V
Output timing reference levels ................. VOH =1.5V, VOL=1.5V
Output loads ........................................................ Fig.1,Fig.2
5.0V
OUTPUT
Z0=50Ω
480Ω
DQ
DQ
255Ω
RL=50Ω
5pF
(including
scope and JIG)
VL=1.5V
Fig.1 Output load
Fig.2 Output load for ten , t dis
MITSUBISHI
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MITSUBISHI LSIs
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
(2)READ CYCLE
Limits
Symbol
Parameter
M5M512R88DJ -10
Min
Max
M5M512R88DJ -12
Min
Max
M5M512R88DJ -15
Min
Unit
Max
tCR
Read cycle time
ta(A)
Address access time
10
12
15
ns
ta(S)
Chip select access time
10
12
15
ns
ta(OE)
Output enable access time
5
6
7
ns
tdis(S)
Output disable time after S high
0
5
0
6
0
7
ns
tdis(OE)
Output disable time after OE high
0
5
0
6
0
7
ns
ten(S)
Output enable time after S low
4
ten(OE)
Output enable time after OE low
tv(A)
10
15
12
ns
4
ns
3
4
3
3
ns
Data valid time after address change
4
4
4
ns
tPU
Power-up time after chip selection
0
0
0
ns
tPD
Power-down time after chip selection
12
10
15
ns
(3)WRITE CYCLE
Limits
Symbol
Parameter
M5M512R88DJ -10
Min
Max
M5M512R88DJ -12
Min
Max
M5M512R88DJ -15
Min
Unit
Max
10
12
15
ns
Write pulse width
9
10
12
ns
tsu(A)1
Address setup time(W)
0
0
0
ns
tsu(A)2
Address setup time(S)
0
0
0
ns
tsu(S)
Chip select setup time
9
10
12
ns
tsu(D)
Data setup time
5
6
7
ns
th(D)
Data hold time
0
0
0
ns
trec(W)
Write recovery time
0
0
0
ns
tdis(W)
Output disable time after W low
0
5
0
6
0
7
ns
tdis(OE)
Output disable time after OE high
0
5
0
6
0
7
ns
ten(W)
Output enable time after W high
0
0
0
ns
ten(OE)
Output enable time after OE low
0
0
0
ns
9
10
12
ns
tCW
Write cycle time
tw
tsu(A-WH) Address to W High
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MITSUBISHI LSIs
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle 1
A 0~16
t CR
VIH
VIL
ta(A)
tv(A)
DQ1~8
VOH
tv(A)
PREVIOUS DATA VALID
VOL
UNKNOWN
DATA VALID
W=H
S=L
OE=L
Read cycle 2 (Note 3)
t CR
VIH
S
VIL
ta(S)
VOH
UNKNOWN
DATA VALID
VOL
tPU
ICC1
Icc
(Note 4)
(Note 4)
ten(S)
DQ1~8
tdis(S)
tPD
50%
ICC2
50%
W=H
OE=L
Note 3. Addresses valid prior to or coincident with S transition low.
4. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 5)
t CR
VIH
OE
VIL
ta(OE)
(Note 4)
DQ1~8
VOH
tdis(OE)
(Note 4)
ten(OE)
UNKNOWN
DATA VALID
VOL
W=H
S=L
Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
MITSUBISHI
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MITSUBISHI LSIs
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle (W control mode)
t CW
A 0~16
VIH
VIL
S
VIH
VIL
tsu(S)
(Note 6)
(Note 6)
tsu(A-WH)
OE
VIH
VIL
tsu(A)
W
tw(W)
trec(W)
VIH
VIL
tsu(D)
DQ1~8
(Input Data)
VIH
VIL
th(D)
DATA STABLE
tdis(W)
(Note 4)
ten(OE)
ten(W)
tdis(OE)
DQ1~8
(Output Data)
VOH
VOL
(Note 4)
Hi-Z
Write cycle(S control)
t CW
A 0~16
VIH
VIL
S
VIH
VIL
tsu(A)
tsu(S)
trec(W)
tw(W)
W
VIH
VIL
(Note 6)
(Note 6)
tsu(D)
DQ1~8
(Input Data)
VIH
VIL
DATA STABLE
ten(S)
DQ1~8
(Output Data)
VOH
VOL
th(D)
(Note 4)
tdis(W)
(Note 4)
Hi-Z
(Note 7)
Note 6: Hatching indicates the state is don't care.
7: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance.
8: ten,tdis are periodically sampled and are not 100% tested.
MITSUBISHI
ELECTRIC
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