Cypress CY2273APVC-1 Pentiumâ®/ii, 6x86, k6 clock synthesizer/driver for desktop pcs with intel 82430tx, 82440lx or ali iv/iv, agp and 3 dimm Datasheet

CY2273A
Pentium®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs
with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs
Features
• Mixed 2.5V and 3.3V operation
• Complete clock solution for Pentium®, Pentium® II,
Cyrix, and AMD processor-based motherboards
— Four CPU clocks at 2.5V or 3.3V
— Up to twelve 3.3V SDRAM clocks
— Seven synchronous PCI clocks, one free-running
— One 3.3V 48 MHz USB clock
— One 2.5V IOAPIC clock (-3 option only)
— Two AGP clocks at 60 or 66.6MHz (-2 option only)
— One 3.3V Ref. clock at 14.318 MHz
• I2C™ Serial Configuration Interface
• Factory-EPROM programmable output drive and slew
rate for EMI customization
• Factory-EPROM programmable CPU clock frequencies
for custom configurations
• Power-down, CPU stop and PCI stop pins
• Available in space-saving 48-pin SSOP package
Functional Description
The CY2273A is a clock synthesizer/driver for a Pentium, Pentium II, Cyrix, or AMD processor-based PC using Intel’s
82430TX, 82440LX, ALI Aladdin IV or Aladdin IV+ chipsets.
The CY2273A-1 outputs four CPU clocks at 2.5V or 3.3V with
up to 83.3MHz operation. There are seven PCI clocks, running
at 30 and 33.3MHz. One of the PCI clocks is free-running.
Additionally, the part outputs up to twelve 3.3V SDRAM clocks,
one 3.3V USB clock at 48 MHz, and one 3.3V reference clock
at 14.318 MHz. The CY2273A-2 is similar, except that
PCICLK4 and PCICLK5 are now AGP clocks. The CY2273A-3
is more suited to Pentium II systems, as it outputs one 2.5V
IOAPIC clock. Finally, the CY2273A-4 is similar to the
CY2273A-1 except that is supports 0-ns CPU-PCI delay.
Logic Block Diagram
The CY2273A possesses power-down, CPU stop, and PCI
stop pins for power management control. These inputs are
multiplexed with SDRAM clock outputs, and are selected when
the MODE pin is driven low. Additionally, the signals are synchronized on-chip, and ensure glitch-free transitions on the
outputs. When the CPU_STOP input is asserted, the CPU
clock outputs are driven LOW. When the PCI_STOP input is
asserted, the PCI clock outputs (except the free-running PCI
clock) are driven LOW. When the PWR_DWN pin is asserted,
the reference oscillator and PLLs are shut down, and all outputs are driven LOW.
The CY2273A outputs are designed for low EMI emissions.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate enable optimal configurations for EMI control.
CY2273A Selector Guide
Clocks Outputs
-1
-2
-3
-4
CPU (60, 66.6, 75,
83.3 MHz)
4
4
--
4
CPU (60, 66.6 MHz)
--
--
4
--
SDRAM
9/12
9/12
9/12
9/12
PCI (30, 33.3MHz)
7[1]
5[1]
7[1]
7[1]
USB/IR (48MHz)
1
1
1
1
AGP (60 or 66MHz)
--
2
--
--
IOAPIC (14.318MHz)
--
--
1
--
1
1
Ref (14.318MHz)
CPU-PCI delay
1–5.5 ns 1–5.5 ns
1
1
0 ns
0 ns
Note:
1. One free-running PCI clock.
CY2273A-3 only
IOAPIC
VDDQ2
XTALIN
XTALOUT
REF0 (14.318 MHz)
14.318
MHz
OSC.
STOP
LOGIC
CPU
PLL
CPUCLK [0-3]
VDDCPU
SEL0
SEL1
SDRAM5/PWR_DWN
SDRAM [0-4],[8-11]
EPROM
CY2273A-1,-2,-4 only
SDRAM6/CPU_STOP
MODE
SYS PLL
Delay (-1,-2 option)
SDRAM7/PCI_STOP
/1 or /1.25
CY2273A-2 only
AGP [0,1]
/1 or /2
SCLK
SDATA
STOP
LOGIC
PCI [0-5], PCI [0-3]
PCICLK_F
SERIAL
INTERFACE
CONTROL
LOGIC
USBCLK (48 MHz)
Intel and Pentium are registered trademarks of Intel Corporation. I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 12, 1998
CY2273A
Pin Configurations
CY2273A-1,-4
CY2273A-2
CY2273A-3
SSOP
Top View
SSOP
Top View
SSOP
Top View
1
48
VDDQ3
AVDD
1
48
VDDQ3
2
3
47
46
USBCLK
REF0
2
3
47
46
USBCLK
4
4
SEL1
VSS
5
6
43
PCICLK_F
7
42
CPUCLK1
VDDCPU
PCICLK0
VSS
8
41
CPUCLK2
9
10
11
12
40
39
38
CPUCLK3
14
15
37
36
35
34
SDRAM1
VDDQ3
SDRAM2
16
33
SDRAM11
SDRAM10
17
32
18
31
VDDQ3
SDRAM9
19
30
20
SDRAM8
VSS
SDATA
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDQ3
PCICLK5
VSS
SCLK
13
CY2273A-1,-4
XTALOUT
VDDQ3
45
44
CPUCLK0
VSS
SDRAM0
SDRAM3
VSS
VSS
XTALIN
XTALOUT
VDDQ3
5
6
43
PCICLK_F
7
42
CPUCLK1
VDDCPU
PCICLK0
VSS
8
41
CPUCLK2
9
10
11
12
40
CPUCLK3
39
38
VSS
14
15
37
36
35
34
SDRAM1
VDDQ3
SDRAM2
16
33
PCICLK1
PCICLK2
PCICLK3
AGP0
VDDQ3
AGP1
VSS
13
SDRAM4
SDRAM5/PWR_DWN
SDRAM11
SDRAM10
17
32
18
31
VDDQ3
SDRAM6/CPU_STOP
VDDQ3
SDRAM9
19
30
29
20
21
28
SDRAM7/PCI_STOP
22
27
SDRAM8
VSS
23
24
26
25
VSS
SEL0
MODE
SEL1
VSS
45
44
CY2273A-2
VSS
XTALIN
CPUCLK0
SDRAM0
SDRAM3
VSS
USBCLK
1
48
VDDQ2
REF0
2
3
47
46
IOAPIC
4
VSS
XTALIN
SEL0
VSS
XTALOUT
VDDQ3
5
45
44
6
43
PCICLK_F
7
42
CPUCLK1
VDDCPU
PCICLK0
VSS
8
41
CPUCLK2
9
10
11
12
40
CPUCLK3
39
38
VSS
14
15
37
36
35
34
SDRAM1
VDDQ3
SDRAM2
16
33
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDQ3
PCICLK5
VSS
13
CY2273A-3
AVDD
REF0
CPUCLK0
SDRAM0
SDRAM3
VSS
SDRAM4
SDRAM5/PWR_DWN
SDRAM11
SDRAM10
17
32
18
31
VDDQ3
SDRAM6/CPU_STOP
VDDQ3
SDRAM9
19
30
29
20
29
VDDQ3
SDRAM6/CPU_STOP
21
28
SDRAM7/PCI_STOP
28
SDRAM7/PCI_STOP
27
22
27
SDATA
23
26
VSS
SEL0
SDRAM8
VSS
21
22
AVDD
23
26
VSS
MODE
SCLK
24
25
MODE
SDATA
24
25
SCLK
2
SDRAM4
SDRAM5/PWR_DWN
CY2273A
Pin Summary
Pins (-1, -4)
Pins (-2)
VDDQ3
Name
6, 14, 19, 30, 36,
48
6, 14, 19, 30, 36,
48
6, 14, 19, 30, 36
Pins (-3)
3.3V Digital voltage supply
Description
VDDQ2
N/A
N/A
48
IOAPIC Digital voltage supply, 2.5V
VDDCPU
42
42
42
CPU Digital voltage supply, 2.5V or 3.3V
AVDD
1
1
23
Analog voltage supply, 3.3V
VSS
3, 9, 16, 22, 27,
33, 39, 45
3, 9, 16, 22, 27,
33, 39, 45
3, 9, 16, 22, 27,
33, 39, 45
Ground
XTALIN[2]
4
4
4
Reference crystal input
XTALOUT[2]
5
5
5
Reference crystal feedback
SDRAM7/
PCI_STOP
28
28
28
SDRAM clock output. Also, active low control input
to stop PCI clocks, enabled when MODE is LOW.
SDRAM6/
CPU_STOP
29
29
29
SDRAM clock output. Also, active low control input
to stop CPU clocks, enabled when MODE is LOW.
SDRAM5/
PWR_DWN
31
31
31
SDRAM clock output. Also, active low control input
to power down device, enabled when MODE is LOW.
SDRAM[0:4],
[8:11]
38, 37, 35, 34,
38, 37, 35, 34,
38, 37, 35, 34,
SDRAM clock outputs
32, 21, 20, 18, 17 32, 21, 20, 18, 17 32, 21, 20, 18, 17
SEL0
26
26
46
CPU frequency select input, bit 0 (See table below.)
SEL1
46
46
N/A
CPU frequency select input, bit 0 (See table below.)
CPUCLK[0:3]
44, 43, 41, 40
44, 43, 41, 40
44, 43, 41, 40
CPU clock outputs
PCICLK[0:5] or
PCICLK[0:3]
8, 10, 11, 12, 13,
15
8, 10, 11, 12
8, 10, 11, 12, 13,
15
PCI clock outputs, at 30 or 33.33 MHz
PCICLK_F
7
7
7
Free-running PCI clock output
AGPCLK[0:1]
N/A
13, 15
N/A
AGP clock outputs at 60 or 66.66 MHz
IOAPIC
N/A
N/A
47
IOAPIC clock output
REF0
2
2
2
3.3V Reference clock output
USBCLK
47
47
1
USB Clock output at 48 MHz
SDATA
23
23
24
Serial data input for serial configuration port
SCLK
24
24
25
Serial clock input for serial configuration port
MODE
25
25
26
Mode Select pin for enabling power management
features
Note:
2. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
Function Table (-1, -2 and -4)
CPU/PCI
Ratio
CPUCLK[0:3]
SDRAM[0:11]
PCICLK[0:5]
PCICLK_F
AGP
(-2 Only)
REF0
IOAPIC
SEL1
SEL0
0
0
2
60.0 MHz
30.0 MHz
60.0 MHz
14.318 MHz
48 MHz
USBCLK
0
1
2
66.67 MHz
33.33 MHz
66.66 MHz
14.318 MHz
48 MHz
1
0
2.5
75.0 MHz
30.0 MHz
60.0 MHz
14.318 MHz
48 MHz
1
1
2.5
83.33 MHz
33.33 MHz
66.66 MHz
14.318 MHz
48 MHz
Function Table (-3)
SEL0
CPU/PCI Ratio
CPUCLK[0:3]/SDRAM[0:11]
PCICLK[0:5],PCICLK_F
0
2
60.0 MHz
30.0 MHz
14.318 MHz
48 MHz
1
2
66.67 MHz
33.33 MHz
14.318 MHz
48 MHz
3
REF0/IOAPIC
USBCLK
CY2273A
Actual Clock Frequency Values
Target
Frequency
(MHz)
Clock Output
Actual
Frequency
(MHz)
PPM
CPUCLK
66.67
66.654
–195
CPUCLK
60.0
60.0
0
CPUCLK
75.0
75.0
0
CPUCLK
83.33
83.138
–1947
USBCLK
48.0
48.008
167
• Output impedance: 25Ω (typical) measured at 1.5V
Power Management Logic[3] - Active when MODE pin is held ‘LOW’
CPUCLK
PCICLK
PCI_STOP PWR_DWN
X
X
0
Low
Low
Stopped
Stopped
Off
0
0
1
Low
Low
Running
Running
Running Running
0
1
1
Low
33/30 MHz
Running
Running
Running Running
1
0
1
60/66/75/83 MHz Low
Running
Running
Running Running
1
1
1
60/66/75/83 MHz 30/33/30/33 MHz
Running
Running
Running Running
Serial Configuration Map
Bit
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”.
• I2C Address for the CY2273 is:
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
----
Osc.
PLLs
Off
Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
A6
PCICLK_F
Other
Clocks
CPU_STOP
Pin #
Description
Bit 7 --
(Reserved) drive to ‘0’
Bit 6 --
(Reserved) drive to ‘0’
Bit 5 --
(Reserved) drive to ‘0’
Bit 4 --
(Reserved) drive to ‘0’
Bit 3 --
(Reserved) drive to ‘0’
Bit 2 --
(Reserved) drive to ‘0’
Bit 1 -Bit 0
Bit 1
1
1
0
0
Bit 0
1 - Three-State
0 - N/A
1 - Testmode
0 - Normal Operation
Select Functions
Outputs
Functional Description
CPU
PCI, PCI_F
SDRAM
-2 only
Ref
IOAPIC
USBCLK
AGP
Three-State
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Test Mode[5]
TCLK/2[4]
TCLK/4
TCLK/2
TCLK
TCLK
TCLK/2
TCLK/2
Notes:
3. AGP clocks are driven on PCICLK5 and PCICLK4 on -2 option. These clocks behave similar to the PCICLK_F output, in that they are free-running and stop
only when the PWR_DWN pin is asserted. The frequency of the AGP clocks is as shown in the Function Table.
4. TCLK supplied on the XTALIN pin in Test Mode.
5. Valid only for SEL1=0.
4
CY2273A
Byte 1: CPU Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Byte 2: PCI Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Description
Bit 7
47 (-1,-2, and -4)
1 (-3 only)
USBCLK
Bit 6
N/A
(Reserved) drive to ‘0’
Bit 5
N/A
(Reserved) drive to ‘0’
Bit 4
N/A
Not used - drive to ‘0’
Bit 3
40
CPUCLK3 (Active/Inactive)
Bit 2
41
CPUCLK2 (Active/Inactive)
Bit 1
43
CPUCLK1 (Active/Inactive)
Bit 0
44
CPUCLK0 (Active/Inactive)
Bit
Byte 3: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
SDRAM7 (Active/Inactive)
Bit 6 29
SDRAM6 (Active/Inactive)
Bit 5 31
SDRAM5 (Active/Inactive)
Bit 4 32
SDRAM4 (Active/Inactive)
Bit 3 34
SDRAM3 (Active/Inactive)
Bit 2 35
SDRAM2 (Active/Inactive)
Bit 1 37
SDRAM1 (Active/Inactive)
Bit 0 38
SDRAM0 (Active/Inactive)
Pin #
N/A
(Reserved) drive to ‘0’
Bit 6
N/A
(Reserved) drive to ‘0’
Bit 5
N/A
(Reserved) drive to ‘0’
Bit 4
47
IOAPIC (Active/Inactive) (-3 only)
Bit 3
N/A
(Reserved) drive to ‘0’
Bit 2
N/A
(Reserved) drive to ‘0’
Bit 1
N/A
(Reserved) drive to ‘0’
Bit 0
2
REF0 (Active/Inactive)
--
(Reserved) drive to ‘0’
Bit 6
7
PCICLK_F (Active/Inactive)
Bit 5
15
PCICLK5 (Active/Inactive) (-1,-3 and -4)
AGP1 (Active/Inactive) (-2 only)
Bit 4
13
PCICLK4 (Active/Inactive) (-1,-3 and -4)
AGP0 (Active/Inactive) (-2 only)
Bit 3
12
PCICLK3 (Active/Inactive)
Bit 2
11
PCICLK2 (Active/Inactive)
Bit 1
10
PCICLK1 (Active/Inactive)
Bit 0
8
PCICLK0 (Active/Inactive)
Pin #
Description
Bit 7
N/A
Not used - drive to ‘0’
Bit 6
N/A
Not used - drive to ‘0’
Bit 5
N/A
Not used - drive to ‘0’
Bit 4
N/A
Not used - drive to ‘0’
Bit 3
17
SDRAM11
Bit 2
18
SDRAM10
Bit 1
20
SDRAM9
Bit 0
21
SDRAM8
Byte 6: Reserved, for future use
Description
Bit 7
Bit 7
Bit
Byte 5: Peripheral Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Description
Byte 4: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Description
Bit 7 28
Pin #
5
CY2273A
Storage Temperature (Non-Condensing) ... –65°C to +150°C
Maximum Ratings
Max. Soldering Temperature (10 sec) ...................... +260°C
(Above which the useful life may be impaired. For user guidelines, not tested.)
Junction Temperature ............................................... +150°C
Supply Voltage ..................................................–0.5 to +7.0V
Package Power Dissipation .............................................. 1W
Input Voltage .............................................. –0.5V to VDD+0.5
Static Discharge Voltage ........................................... >2000V
(per MIL-STD-883, Method 3015, like VDD pins tied together)
Operating Conditions[6]
Parameter
Description
Min.
Max.
Unit
AVDD, V DDQ3
Analog and Digital Supply Voltage
3.135
3.465
V
VDDCPU
CPU Supply Voltage
2.375
3.135
2.9
3.465
V
VDDQ2
IOAPIC Supply Voltage
2.375
2.9
V
TA
Operating Temperature, Ambient
0
70
°C
CL
Max. Capacitive Load on
CPUCLK, USBCLK, IOAPIC
PCICLK, AGP(-2 only), SDRAM
REF0
10
30, 20
20
20
30
45
f(REF)
Reference Frequency, Oscillator Nominal Value
14.318
14.318
pF
MHz
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min. Max. Unit
VIH
High-level Input Voltage
VIL
Low-level Input Voltage
Except Crystal Inputs
0.8
V
VILiic
Low-level Input Voltage
I2C inputs only
0.7
V
VOH
High-level Output Voltage VDDCPU = VDDQ2 = 2.375V
VOL
Low-level Output Voltage
VOH
High-level Output Voltage VDDQ3, AVDD, V DDCPU = 3.135V
Except Crystal Inputs
2.0
IOH = 16 mA CPUCLK
V
2.0
V
IOH = 18 mA IOAPIC
VDDCPU = VDDQ2 = 2.375V
IOL = 27 mA CPUCLK
0.4
V
IOL = 29 mA IOAPIC
IOH = 16 mA CPUCLK
2.4
V
IOH = 36 mA SDRAM
IOH = 32 mA PCICLK
IOH = 26 mA USBCLK
IOH = 36 mA REF0
VOL
Low-level Output Voltage
VDDQ3, AVDD, V DDCPU = 3.135V
IOL = 27 mA CPUCLK
0.4V
V
+10
µA
10
µA
IOL = 29 mA SDRAM
IOL = 26 mA PCICLK
IOL = 21 mA USBCLK
IOL = 29 mA REF0
IIH
Input High Current
VIH = V DD
IIL
Input Low Current
VIL = 0V
–10
IOZ
Output Leakage Current
Three-state
IDD
Power Supply Current[7]
IDD
Power Supply Current[7]
VDD = 3.465V, V IN = 0 or VDD, Loaded Outputs, CPU = 66.67 MHz
VDD = 3.465V, V IN = 0 or VDD, Unloaded Outputs
–10
IDDS
Power-down Current
Current draw in power-down state
Notes:
6. Electrical parameters are guaranteed with these operating conditions.
7. Power supply current will vary with number of outputs which are running.
6
+10
µA
300
mA
120
mA
500
µA
CY2273A
Switching Characteristics for CY2273A-1, CY2273A-2[8]Over the Operating Range
Parameter
Output
Description
Test Conditions
Min.
Typ.
45
50
Max.
Unit
t1
All
Output Duty Cycle
t1 = t1A ÷ t1B
55
%
t2
CPUCLK
CPU Clock Rising and
Falling Edge Rate[10]
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.75
4.0
V/ns
t2
SDRAM, PCI,
REF0, USB
SDRAM, PCI, REF0
Clock Rising and Falling Edge Rate[10]
Between 0.4V and 2.4V
0.85
4.0
V/ns
t2
AGP (-2 only)
AGP Rising and Falling
Edge Rate
Between 0.4V and 2.4V
0.85
4.0
V/ns
t3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.4
0.5
2.13
2.67
ns
t4
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V
Between 2.4V and 0.4V, VDDCPU = 3.3V
0.4
0.5
2.13
2.67
ns
t5
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V, VDDCPU = 2.5V
Measured at 1.5V, VDDCPU = 3.3V
100
250
ps
t6
CPUCLK,
PCICLK
CPU-PCI Clock Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
3.0
5.5
ns
t7
CPUCLK,
SDRAM
CPU-SDRAM Clock
Skew[10]
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
650
ps
t8
PCICLK,
PCICLK
PCI-PCI Clock Skew
Measured at 1.5V
500
ps
t9
PCICLK,
AGP (-2 only)
PCICLK-AGP Clock
Skew (-2 only)
Measured at 1.5V
500
ps
t10
CPUCLK,
SDRAM
Cycle-Cycle Clock
Jitter[10]
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
250
ps
t10
PCICLK,
AGP (-2 only)
Cycle-Cycle Clock
Jitter[10]
Measured at 1.5V
500
ps
t11
CPUCLK,
PCICLK,
AGP (-2 only),
SDRAM
Power-up Time
CPU, PCI, AGP, and SDRAM clock stabilization from power-up
3
ms
[9, 10]
Notes:
8. All parameters specified with loaded outputs.
9. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDDCPU = 2.5V, CPUCLK duty cycle is measured at 1.25V.
10. Measured at CPU=66.6 MHz, SDRAM=66.6 MHz, PCI=33.3 MHz, AGP=66.6 MHz.
7
1.0
CY2273A
Switching Characteristics for CY2273A-3[8]Over the Operating Range
Parameter
Output
Description
[9]
Test Conditions
t1 = t1A ÷ t1B
Min.
Typ.
Max.
Unit
45
50
55
%
0.75
1.0
4.0
V/ns
4.0
V/ns
4.0
V/ns
t1
All
Output Duty Cycle
t2
CPUCLK,
IOAPIC
CPU and IOAPIC Clock
Rising and Falling Edge
Rate
t2
REF0
USBCLK
REF0 and USBCLK Ris- Between 0.4V and 2.4V
ing and Falling Edge Rate
1.0
t2
SDRAM
PCI
SDRAM and PCI Clock
Rising and Falling Edge
Rate
Between 0.4V and 2.4V
0.85
t3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.4
0.5
2.13
2.67
ns
t4
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V
Between 2.4V and 0.4V, VDDCPU = 3.3V
0.4
0.5
2.13
2.67
ns
t5
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V, VDDCPU = 2.5V
Measured at 1.5V, VDDCPU = 3.3V
300
ps
t6
CPUCLK,
PCICLK
CPU-PCI Clock Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
900
ps
t7
CPUCLK,
SDRAM
CPU-SDRAM Clock
Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
600
ps
t8
PCICLK,
PCICLK
PCI-PCI Clock Skew
Measured at 1.5V
500
ps
t10
CPUCLK,
SDRAM
Cycle-Cycle Clock Jitter
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
750
ps
t10
PCICLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
500
ps
t11
CPUCLK,
PCICLK,
SDRAM
Power-up Time
CPU, PCI, AGP, and SDRAM clock stabilization from power-up
3
ms
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
8
1.0
100
CY2273A
Switching Characteristics for CY2273A-4[8]Over the Operating Range
Parameter
Output
Description
[9]
Test Conditions
Min.
t1 = t1A ÷ t1B
Typ.
Max.
Unit
t1
All
Output Duty Cycle
45
50
55
%
t2
CPUCLK
CPU Clock Rising and
Falling Edge Rate
Between 0.4V and 2.0V, VDDCPU = 2.5V
0.75
1.0
4.0
V/ns
t2
SDRAM
PCI, REF0,
USB
SDRAM, PCI, REF0,
USB Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V
0.85
1.0
4.0
V/ns
t3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V
0.4
2.13
ns
t4
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V
0.4
2.13
ns
t5
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V
250
ps
t6
CPUCLK,
PCICLK
CPU-PCI Clock Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
1200
ps
t7
CPUCLK,
SDRAM
CPU-SDRAM Clock
Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
650
ps
t8
PCICLK,
PCICLK
PCI-PCI Clock Skew
Measured at 1.5V
500
ps
t10
CPUCLK,
Cycle-Cycle Clock Jitter
Measured at 1.25V, VDDCPU = 2.5V
650
ps
t10
SDRAM
Cycle-Cycle Clock Jitter
Measured at 1.5V
650
ps
t10
PCICLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
1200
ps
t11
CPUCLK,
PCICLK,
SDRAM
Power-up Time
CPU, PCI, AGP, and SDRAM clock stabilization from power-up
3
ms
100
Timing Requirement for the I2C Bus
Parameter
Description
t12
SCLK Clock Frequency
t13
Time the bus must be free before a new transmission can start
t14
Hold time start condition. After this period the first clock pulse is generated.
t15
The Low period of the clock.
t16
The High period of the clock.
t17
Set-up time for start condition. (Only relevant for a repeated start condition.)
t18
Hold time DATA
for CBUS compatible masters.
for I2C devices
t19
DATA input set-up time
Min.
Max.
Unit
0
100
kHz
4.7
µs
4
µs
4.7
µs
4
µs
4.7
µs
µs
5
0
250
ns
t20
Rise time of both SDATA and SCLK inputs
1
µs
t21
Fall time of both SDATA and SCLK inputs
300
ns
t22
Se-up time for stop condition
4.0
Switching Waveforms
Duty Cycle Timing
t1A
t1B
9
µs
CY2273A
Switching Waveforms (continued)
All Outputs Rise/Fall Time
VDD
0V
OUTPUT
t2
t3
t2
t4
CPU-CPU Clock Skew
CPUCLK
CPUCLK
t5
CPU-SDRAM Clock Skew
CPUCLK
SDRAM
t7
CPU-PCI Clock Skew
CPUCLK
PCICLK
t6
PCI-PCI Clock Skew
PCICLK
PCICLK
t8
AGP-PCI Clock Skew (-2 only)
AGPCLK
PCICLK
t9
10
CY2273A
Switching Waveforms (continued)
CPU_STOP[11, 12]
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
CPU_STOP
CPUCLK
(External)
PCI_STOP[13, 14]
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
PCI_STOP
PCICLK
(External)
PWR_DOWN
CPUCLK
(Internal)
PCICLK
(Internal)
PWR_DWN
CPUCLK
(External)
PCICLK
(External)
VCO
Crystal
Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Timing Requirements for the I2C Bus
SDA
t13
t20
t21
t14
SCL
t14
t15
t18
t16
t19
Notes:
11. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles.
12. CPU_STOP may be applied asynchronously. It is synchronized internally.
13. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK.
14. PCI_STOP may be applied asynchronously. It is synchronized internally.
11
t17
t22
CY2273A
Application Information
Clock traces must be terminated with either series or parallel termination, as they are normally done.
Application Circuit
Summary
• A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of
this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different
CLOAD is used. Footprints must be laid out for flexibility.
• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF.
In some cases, smaller value capacitors may be required.
• The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance
of the trace, R out is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating
resistor.
Rseries > R trace – Rout
• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor
as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.
• A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers
greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout
and Termination Techniques for Cypress Clock Generators” for more details.
• If a Ferrite Bead is used, a 10 µF– 22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor
prevents power supply droop during current surges.
12
CY2273A
Test Circuit
VDDQ3
1
VDDQ3
0.1 µF
VDDQ2
23
48
48
0.1 µF
0.1 µF
3
0.1 µF
3
45
45
VDDCPU
6
42
0.1 µF
VDDCPU
6
42
0.1 µF
0.1 µF
9
9
16
0.1 µF
36
39
14
0.1 µF
0.1 µF
33
19
30
22
27
0.1 µF
0.1 µF
OUTPUTS
CY2273A-3
14
CY2273A-1, -2, -4
39
0.1 µF
36
16
33
19
30
22
27
OUTPUTS
CLOAD
Note: All Capacitors must be placed as close to the pins as is possible
Ordering Information
Package
Name
0.1 µF
0.1 µF
CLOAD
Ordering Code
0.1 µF
Operating
Range
Package Type
CY2273APVC–1
O48
48-Pin SSOP
Commercial
CY2273APVC–2
O48
48-Pin SSOP
Commercial
CY2273APVC–3
O48
48-Pin SSOP
Commercial
CY2273APVC–4
O48
48-Pin SSOP
Commercial
Document #: 38–00615–D
13
CY2273A
Package Diagram
48-Lead Shrunk Small Outline Package O48
51-85061-B
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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