ON MC74LCX138DR2 Low-voltage cmos 3-to-8 decoder/demultiplexer with 5 v−tolerant input Datasheet

MC74LCX138
Low−Voltage CMOS 3−to−8
Decoder/Demultiplexer
With 5 V−Tolerant Inputs
T h e M C 7 4 L C X 1 3 8 i s a h i g h p e r f o r m a n c e , 3 −t o −8
decoder/demultiplexer operating from a 2.3 to 3.6 V supply. High
impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
MC74LCX138 inputs to be safely driven from 5 V devices. The
MC74LCX138 is suitable for memory address decoding and other
TTL level bus−oriented applications.
The MC74LCX138 high−speed 3−to−8 decoder/demultiplexer
accepts three binary weighted inputs (A0, A1, A2) and, when enabled,
provides eight mutually exclusive active−LOW outputs (O0−O7). The
LCX138 features three Enable inputs, two active−LOW (E1, E2) and
one active−HIGH (E3). All outputs will be HIGH unless E1 and E2 are
LOW, and E3 is HIGH. This multiple enabled function allows easy
parallel expansion of the device to a 1−of−32 (5 lines to 32 lines)
decoder with just four LCX138 devices and one inverter (see
Figure 1). The LCX138 can be used as an 8−output demultiplexer by
using one of the active−LOW Enable inputs as the data input and the
other Enable inputs as strobes. The Enable inputs which are not used
must be permanently tied to their appropriate active−HIGH or
active−LOW state.
Current drive capability is 24 mA at the outputs.
Features
•
•
•
•
•
•
MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
16
1
Designed for 2.3 V to 3.6 V VCC Operation
5 V Tolerant Inputs − Interface Capability With 5 V TTL Logic
LVTTL Compatible
16
1
TSSOP−16
DT SUFFIX
CASE 948F
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current (10 A) Substantially Reduces
System Power Requirements
Latchup Performance Exceeds 500 mA
Human Body Model >2000 V
Machine Model >200 V
Pb−Free Packages are Available*
LCX
138
ALYW
1
16
SOEIAJ−16
M SUFFIX
CASE 966
74LCX138
ALYW
1
1
A
L, WL
Y
W, WW
LVCMOS Compatible
LCX138
AWLYWW
1
16
16
•
• ESD Performance:
•
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=
=
=
=
Assembly Location
Wafer Lot
Year
Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
 Semiconductor Components Industries, LLC, 2005
January, 2005 − Rev. 5
1
Publication Order Number:
MC74LCX138/D
MC74LCX138
A2
3
VCC
O0
O1
O2
O3
O4
O5
O6
16
15
14
13
12
11
10
9
7
8
1
2
3
4
5
6
A0
A1
A2
E1
E2
E3
A1
2
A0
1
E1
E2
4
E3
5
6
O7 GND
Figure 1. Pinout: 16−Lead (Top View)
7
O7
9
O6
1
O50
1
O41
12
O3
13
O2
1
O14
1
O05
Figure 2. Logic Diagram
PIN NAMES
Pins
Function
A0−A2
Address Inputs
E1−E2
Enable Inputs
E3
Enable Input
O0−O7
Outputs
TRUTH TABLE
Inputs
Outputs
E1
E2
E3
A0
A1
A2
O0
O1
O2
O3
O4
O5
O6
O7
H
X
X
X
H
X
X
X
L
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
H
L
L
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
L
L
H
L
L
H
L
L
H
H
L
H
L
L
H
L
H
H
L
L
H
H
H
H
H = High Voltage Level
L = Low Voltage Level
X = High or Low Voltage Level and Transitions are Acceptable
For ICC reasons, DO NOT FLOAT Inputs
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2
MC74LCX138
A0
A1
A2
‘04
A3
A4
H
123
A0 A1 A2
123
E
O0 O1 O2 O3 O4 O5 O6 O7
A0 A1 A2
123
123
E
A0 A1 A2
O0 O1 O2 O3 O4 O5 O6 O7
E
A0 A1 A2
O0 O1 O2 O3 O4 O5 O6 O7
E
O0 O1 O2 O3 O4 O5 O6 O7
O0
O31
Figure 3. Expansion to 1−of−32 Decoding
ORDERING INFORMATION
Package
Shipping†
MC74LCX138DR2
SOIC−16
2500 Tape & Reel
MC74LCX138DR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
Device
MC74LCX138DT
TSSOP−16*
96 Units / Rail
MC74LCX138DTR2
TSSOP−16*
2500 Tape & Reel
MC74LCX138MEL
SOEIAJ−16
2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
VCC
DC Supply Voltage
−0.5 to +7.0
V
VI
DC Input Voltage
−0.5 ≤ VI ≤ +7.0
V
VO
DC Output Voltage
IIK
DC Input Diode Current
−50
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
+50
VO > VCC
mA
−0.5 ≤ VO ≤ VCC + 0.5
Output in HIGH or LOW State (Note 1)
V
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
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MC74LCX138
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Operating Data Retention Only
Min
Typ
Max
Unit
2.0
1.5
2.5, 3.3
2.5, 3.3
3.6
3.6
V
0
5.5
V
0
VCC
V
VCC
Supply Voltage
VI
Input Voltage
VO
Output Voltage
(HIGH or LOW State) (3−State)
IOH
HIGH Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
VCC = 2.3 V − 2.7 V
−24
−12
−8
mA
IOL
LOW Level Output Voltage
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
VCC = 2.3 V − 2.7 V
+24
+12
+8
mA
TA
Operating Free−Air Temperature
t/V
Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V
−40
+85
°C
0
10
ns/V
DC ELECTRICAL CHARACTERISTICS
TA = −40°C to +85°C
Symbol
Characteristic
Condition
VIH
HIGH Level Input Voltage (Note 2)
VIL
LOW Level Input Voltage (Note 2)
VOH
VOL
Min
2.3 V ≤ VCC ≤ 2.7 V
1.7
2.7 V ≤ VCC ≤ 3.6 V
2.0
0.7
2.7 V ≤ VCC ≤ 3.6 V
0.8
LOW Level Output Voltage
VCC − 0.2
VCC = 2.3 V; IOH = −8 mA
1.8
VCC = 2.7 V; IOH = −12 mA
2.2
VCC = 3.0 V; IOH = −18 mA
2.4
VCC = 3.0 V; IOH = −24 mA
2.2
Unit
V
2.3 V ≤ VCC ≤ 2.7 V
2.3 V ≤ VCC ≤ 3.6 V; IOH = −100 A
HIGH Level Output Voltage
Max
V
V
2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 A
0.2
VCC = 2.3 V; IOL = 8 mA
0.6
VCC = 2.7 V; IOL = 12 mA
0.4
VCC = 3.0 V; IOL = 16 mA
0.4
VCC = 3.0 V; IOL = 24 mA
0.55
V
II
Input Leakage Current
2.3 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 5.5 V
±5
A
ICC
Quiescent Supply Current
2.3 ≤ VCC ≤ 3.6 V; VI = GND or VCC
10
A
2.3 ≤ VCC ≤ 3.6 V; 3.6 ≤ VI or VO ≤ 5.5 V
±10
ICC
Increase in ICC per Input
2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V
2. These values of VI are used to test DC electrical characteristics only.
500
A
AC CHARACTERISTICS tR = tF = 2.5 ns; RL = 500 Limits
TA = −40°C to +85°C
Symbol
Parameter
VCC = 3.3 V ± 0.3 V
VCC = 2.7 V
CL = 50 pF
CL = 50 pF
VCC = 2.5 V ± 0.2 V
CL = 30 pF
Waveform
Min
Max
Min
Max
Min
Max
Unit
tPLH
tPHL
Propagation Delay
An to On
1, 2
1.5
1.5
6.0
6.0
1.5
1.5
7.0
7.0
1.5
1.5
7.2
7.2
ns
tPLH
tPHL
Propagation Delay
E1, E2 to On
2
1.5
1.5
6.5
6.5
1.5
1.5
7.5
7.5
1.5
1.5
8.4
8.4
ns
tPLH
tPHL
Propagation Delay
E3 to On
1
1.5
1.5
6.0
6.0
1.5
1.5
7.0
7.0
1.5
1.5
7.2
7.2
ns
tOSHL
tOSLH
Output−to−Output Skew
(Note 3)
1.0
1.0
ns
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
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MC74LCX138
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Condition
Typical
Unit
7
pF
VCC = 3.3 V, VI = 0 V or VCC
8
pF
10 MHz, VCC = 3.3 V, VI = 0 V or VCC
25
pF
CIN
Input Capacitance
VCC = 3.3 V, VI = 0 V or VCC
COUT
Output Capacitance
CPD
Power Dissipation Capacitance
VCC
Vmi
An, E3
Vmi
0V
tPHL
tPLH
VOH
Vmo
Vmo
On
VOL
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS
2.7 V
An, E1, E2
Vmi
Vmi
0V
tPHL
tPLH
VOH
On
Vmo
Vmo
VOL
WAVEFORM 2: PROPAGATION DELAYS FOR NON−INVERTING OUTPUTS
Vcc
Symbol
3.3 V + 0.3 V
2.7 V
2.5 V + 0.2 V
Vmi
1.5 V
1.5 V
Vcc/2
Vmo
1.5 V
1.5 V
Vcc/2
Figure 4. AC Waveforms
VCC
PULSE
GENERATOR
DUT
RT
CL =
CL =
RL =
RT =
CL
RL
50 pF at VCC = 3.3 + 0.3 V or equivalent (includes jig and probe capacitance)
30 pF at VCC = 2.5 + 0.2 V or equivalent (includes jig and probe capacitance)
R1 = 500 or equivalent
ZOUT of pulse generator (typically 50 )
Figure 5. Test Circuit
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MC74LCX138
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
DIM
A
B
C
D
F
G
J
K
M
P
R
F
X 45 C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.229
0.244
0.010
0.019
S
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
S
V
S
S
K
ÉÉ
ÇÇ
ÇÇ
ÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
−V−
M
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
D
DETAIL E
G
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6
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
−−−
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
MC74LCX138
PACKAGE DIMENSIONS
SOEIAJ−16
M SUFFIX
CASE 966−01
ISSUE O
16
LE
9
Q1
M
E HE
1
8
L
DETAIL P
Z
D
e
VIEW P
A
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
c
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.10 (0.004)
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7
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 0
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 0
0.028
0.035
−−−
0.031
MC74LCX138
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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