Intersil ACTS112MS Radiation hardened dual j-k flip-flop Datasheet

ACTS112MS
Radiation Hardened
Dual J-K Flip-Flop
January 1996
Features
Pinouts
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96714 and Intersil’s QM Plan
16 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835, DESIGNATOR CDIP2-T16,
LEAD FINISH C
TOP VIEW
• 1.25 Micron Radiation Hardened SOS CMOS
-10
• Single Event Upset (SEU) Immunity: <1 x 10
(Typ)
Errors/Bit/Day
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
K1 2
15 R1
J1 3
14 R2
S1 4
13 CP2
MEV-cm2/mg
Q1 5
12 K2
RAD (Si)/s, 20ns Pulse
Q1 6
11 J2
Q2 7
10 S2
GND 8
9 Q2
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100
11
16 VCC
CP1 1
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 26ns (Max), 16ns (Typ)
Description
The Intersil ACTS112MS is a Radiation Hardened Dual J-K Flip-Flop
with Set and Reset. The output change states on the negative transition
of the clock (CP1N or CP2N).
16 PIN CERAMIC FLATPACK
MIL-STD-1835, DESIGNATOR CDFP4-F16,
LEAD FINISH C
TOP VIEW
CP1
1
16
VCC
K1
2
15
R1
J1
3
14
R2
S1
4
13
CP2
Q1
5
12
K2
Q1
6
11
J2
Q2
7
10
S2
GND
8
9
Q2
The ACTS112MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS112MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or
a Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
5962F9671401VEC
-55oC to +125oC
MIL-PRF-38535 Class V
16 Lead SBDIP
5962F9671401VXC
-55oC to +125oC
MIL-PRF-38535 Class V
16 Lead Ceramic Flatpack
ACTS112D/Sample
25oC
Sample
16 Lead SBDIP
ACTS112K/Sample
25oC
Sample
16 Lead Ceramic Flatpack
ACTS112HMSR
25oC
Die
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number
File Number
518825
3570.1
ACTS112MS
Functional Diagram
5 (9)
CL
Q
P
3(11)
J
CL
N
P
CL
N
P
CL
N
P
6 (7)
CL
N
CL
2(12)
CL
Q
CL
K
4(10)
S
15(14)
R
1(13)
CL
CP
CL
TRUTH TABLE
INPUTS
OUTPUTS
S
R
CP
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H (Note 2)
H (Note 2)
H
H
L
L
H
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
Toggle
H
H
X
X
No Change
H
No Change
NOTE:
1. H = High Steady State, L = Low Steady State, X = Immaterial,
= High-to-Low Transition
2. Output States Unpredictable if S and R Go High Simultaneously after Both being Low at the
Same Time
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number
2
518825
ACTS112MS
Die Characteristics
DIE DIMENSIONS:
88 mils x 88 mils
2.24mm x 2.24mm
METALLIZATION:
Type: AlSi
Metal 1 Thickness: 7.125kÅ ±1.125kÅ
Metal 2 Thickness: 9kÅ ±1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 105A/cm2
BOND PAD SIZE:
110µm x 110µm
4.3 mils x 4.3 mils
Metallization Mask Layout
ACTS112MS
K1
(2)
CP1
(1)
VCC
(16)
R1
(15)
J1 (3)
(14) R2
S1 (4)
(13) CP2
Q1 (5)
(12) K2
Q1 (6)
(11) J2
(7)
Q2
(8)
GND
(9)
Q2
(10)
S2
Spec Number
3
518825
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