MOTOROLA MC12202D

SEMICONDUCTOR TECHNICAL DATA
The MC12202 is a 1.1GHz Bipolar monolithic serial input phase locked
loop (PLL) synthesizer with pulse–swallow function. It is designed to
provide the high frequency local oscillator signal of an RF transceiver in
handheld communication applications.
Motorola’s advanced Bipolar MOSAIC V technology is utilized for
low power operation at a minimum supply voltage of 2.7V. The device is
designed for operation over 2.7 to 5.5V supply range for input frequencies
up to 1.1GHz with a typical current drain of 6.5mA. The low power
consumption makes the MC12202 ideal for handheld battery operated
applications such as cellular or cordless telephones, wireless LAN or
personal communication services. A dual modulus prescaler is integrated
to provide either a 64/65 or 128/129 divide ratio.
For additional applications information, two InterActiveApNote
documents containing software (based on a Microsoft Excel
spreadsheet) and an Application Note are available. Please order
DK305/D and DK306/D from the Motorola Literature Distribution Center.
MECL PLL COMPONENTS
Serial Input PLL
Frequency Synthesizer
16
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
• Low Power Supply Current of 5.8mA Typical for ICC and 0.7mA Typical
for IP
• Supply Voltage of 2.7 to 5.5V
• Dual Modulus Prescaler With Selectable Divide Ratios of 64/65 or
16
128/129
1
• On–Chip Reference Oscillator/Buffer
M SUFFIX
PLASTIC SOIC PACKAGE
CASE 966–01
• Programmable Reference Divider Consisting of a Binary 14–Bit
Programmable Reference Counter
• Programmable Divider Consisting of a Binary 7–Bit Swallow Counter
and an 11–Bit Programmable Counter
• Phase/Frequency Detector With Phase Conversion Function
20
1
• Balanced Charge Pump Outputs
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
• Dual Internal Charge Pumps for Bypassing the First Stage of the Loop
Filter to Decrease Lock Time
• Outputs for External Charge Pump
• Operating Temperature Range of –40°C to +85°C
• Space Efficient Plastic Surface Mount SOIC or TSSOP Packages
• The MC12202 Is Pin Compatible With the Fujitsu MB1502 or MB1511
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
Power Supply Voltage, Pin 4 (Pin 5 in 20–lead package)
–0.5 to +6.0
VDC
VP
Power Supply Voltage, Pin 3 (Pin 4 in 20–lead package)
VCC to +6.0
VDC
Tstg
Storage Temperature Range
–65 to +150
°C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
MOSAIC V, Mfax and InterActiveApNote are trademarks of Motorola, Inc.
1/97
 Motorola, Inc. 1997
1
REV 4
MC12202
φR
φP
16
15
fOUT BISW
14
13
FC
LE
DATA
CLK
12
11
10
9
Pinout: 16–Lead Packages (Top View)
1
2
3
OSCin OSCout VP
φR
NC
φP
20
19
18
4
5
6
7
8
VCC
Do
GND
LD
fIN
FC
LE
DATA
NC
CLK
15
14
13
12
11
fOUT BISW
17
16
Pinout: 20–Lead Package (Top View)
1
OSCin
2
3
NC OSCout
4
5
6
7
8
9
10
VP
VCC
Do
GND
LD
NC
fIN
PIN NAMES
16–Lead Pkg
Pin No.
20–Lead Pkg
Pin No.
Oscillator input. A crystal is connected between OSCin and OSCout. An external
source can be AC coupled into this input
1
1
O
Oscillator output. Pin should be left open if external source is used
2
3
VP
—
Power supply for charge pumps (VP should be greater than or equal to VCC) VP
provides power to the Do, BISW and φP outputs
3
4
VCC
—
Power supply voltage input. Bypass capacitors should be placed as close as
possible to this pin and be connected directly to the ground plane.
4
5
Do
O
Internal charge pump output. Do remains on at all times
5
6
GND
—
Ground
6
7
LD
O
Lock detect, phase comparator output
7
8
fIN
I
Prescaler input. The VCO signal is AC–coupled into this pin
8
10
CLK
I
Clock input. Rising edge of the clock shifts data into the shift registers
9
11
DATA
I
Binary serial data input
10
13
LE
I
Load enable input (with internal pull up resistor). When LE is HIGH or OPEN, data
stored in the shift register is transferred into the appropriate latch (depending on
the level of control bit). Also, when LE is HIGH or OPEN, the output of the second
internal charge pump is connected to the BISW pin
11
14
FC
I
Phase control select (with internal pull up resistor). When FC is LOW, the
characteristics of the phase comparator and charge pump are reversed. FC also
selects fp or fr on the fOUT pin
12
15
BISW
O
Analog switch output. When LE is HIGH or OPEN (“analog switch is ON”) the
output of the second charge pump is connected to the BISW pin. When LE is LOW,
BISW is high impedance
13
16
fOUT
O
Phase comparator input signal. When FC is HIGH, fOUT=fr, programmable
reference divider output; when FC is LOW, fOUT=fp, programmable divider output
14
17
φP
O
Output for external charge pump. Standard CMOS output level
15
18
φR
O
Output for external charge pump. Standard CMOS output level
16
20
NC
—
No connect
—
2, 9, 12, 19
Pin
I/O
Function
OSCin
I
OSCout
MOTOROLA
2
HIPERCOMM
BR1334 — Rev 4
MC12202
15–BIT SHIFT REGISTER
15
15–BIT LATCH
14
1
PROGRAMMABLE REFERENCE DIVIDER
OSCin
CRYSTAL
OSCILLATOR
OSCout
fr
14–BIT REFERENCE COUNTER
LD
PHASE/FREQUENCY
DETECTOR
FC
φP
φR
CHARGE
PUMP 1
Do
CHARGE
PUMP 2
BISW
LE
LE
CONTROL
BIT
DATA
DATA
18–BIT SHIFT REGISTER
7
CLK
11
7–BIT
LATCH
7
fIN
PRESCALER
64/65 or 128/129
DIVIDER
OUTPUT MUX
11–BIT LATCH
fOUT
11
PROGRAMMABLE DIVIDER
7–BIT
SWALLOW
A–COUNTER
11–BIT
PROGRAMMABLE
N–COUNTER
fp
CONTROL LOGIC
Figure 1. MC12202 Block Diagram
HIPERCOMM
BR1334 — Rev 4
3
MOTOROLA
MC12202
DATA ENTRY FORMAT
The three wire interface of DATA pin, CLK (clock) pin and LE (load enable) pin controls the serial data input of the 14–bit
programmable reference divider plus the prescaler setting bit, and the 18–bit programmable divider. A rising edge of the clock
shifts one bit of serial data into the internal shift registers. Depending upon the level of the control bit, stored data is transferred
into the latch when load enable pin is HIGH or OPEN.
Control bit:
“H” = data is transferred into 15–bit latch of programmable reference divider
“L” = data is transferred into 18–bit latch of programmable divider
WARNING: Switching CLK or DATA after the device is programmed may generate noise on the charge pump outputs which will
affect the VCO.
PROGRAMMABLE REFERENCE DIVIDER
16–bit serial data format for the programmable reference counter, “R–counter”, and prescaler select bit (SW) is shown below. If
the control bit is HIGH, data is transferred from the 15–bit shift register into the 15–bit latch which specifies the R divide ratio (8 to
16383) and the prescaler divide ratio (SW=0 for ÷128/129, SW=1 for ÷64/65). An R divide ratio less than 8 is prohibited.
For Control bit (C) = HIGH:
SETTING BIT FOR PRESCALER DIVIDE RATIO (FIRST BIT)
MSB
CONTROL BIT (LAST BIT)
LSB
S
R
R
R
R
R
R
R
R
R
R
R
R
R
R
W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C
SETTING BITS FOR DIVIDE RATIO OF PROGRAMMABLE
REFERENCE COUNTER (R–COUNTER)
DIVIDE RATIO OF PROGRAMMABLE REFERENCE (R) COUNTER
Divide
Ratio R
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
8
0
0
0
0
0
0
0
0
0
0
1
0
0
0
9
0
0
0
0
0
0
0
0
0
0
1
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PRESCALER SELECT BIT
MOTOROLA
Prescaler Divide Ratio P
SW
128/129
0
64/65
1
4
HIPERCOMM
BR1334 — Rev 4
MC12202
PROGRAMMABLE DIVIDER
19–bit serial data format for the programmable divider is shown below. If the control bit is LOW, data is transferred from the 18–bit
shift register into the 18–bit latch which specifies the swallow A–counter divide ratio (0 to 127) and the programmable N–counter
divide ratio (16 to 2047). An N–counter divide ratio less than 16 is prohibited.
For Control bit (C) = LOW:
MSB (FIRST BIT)
CONTROL BIT (LAST BIT)
LSB
N
N
N
N
N
N
N
N
N
N
N
A
A
A
A
A
A
A
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SETTING BITS FOR
DIVIDE RATIO OF
PROGRAMMABLE N–COUNTER
C
SETTING BITS FOR
DIVIDE RATIO OF
SWALLOW A–COUNTER
DIVIDE RATIO OF PROGRAMMABLE N–COUNTER
DIVIDE RATIO OF SWALLOW A–COUNTER
Divide
Ratio N
N
18
N
17
N
16
N
15
N
14
N
13
N
12
N
11
N
10
N
9
N
8
Divide
Ratio A
A
7
A
6
A
5
A
4
A
3
A
2
A
1
16
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
17
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2047
1
1
1
1
1
1
1
1
1
1
1
127
1
1
1
1
1
1
1
DIVIDE RATIO SETTING
fvco = [(P•N)+A]•fosc ÷ R with A<N
fvco: Output frequency of external voltage controlled oscillator (VCO)
N:
Preset divide ratio of binary 11–bit programmable counter (16 to 2047)
A:
Preset divide ratio of binary 7–bit swallow counter (0 to 127, A<N)
fosc: Output frequency of the external frequency oscillator
R:
Preset divide ratio of binary 14–bit programmable reference counter (8 to 16383)
P:
Preset mode of dual modulus prescaler (64 or 128)
DATA
N18:MSB
N17
N8
A7
A1
C = CONTROL BIT (LAST BIT)
(SW:MSB)
(R14)
(R7)
(R6)
(R1)
(C = CONTROL BIT (LAST BIT))
CLK
LE
ts(C→LE)
ts(D)
th(D)
tCW
tEW
NOTES:Programmable reference divider data shown in parenthesis. Data shifted into register on rising edge of CLK.
ts(D) = Setup Time DATA to CLK
ts(D) ≥ 10ns
th(D) = Hold Time DATA to CLK
th(D) ≥ 20ns
tCW = CLK Pulse Width
tCW ≥ 30ns
tEW = LE Pulse Width
tEW ≥ 20ns
ts(C→LE) = Setup Time CLK to LE
ts(C→LE) ≥ 30ns
Figure 2. Serial Data Input Timing
HIPERCOMM
BR1334 — Rev 4
5
MOTOROLA
MC12202
PHASE CHARACTERISTICS/VCO CHARACTERISTICS
The phase comparator in the MC12202 is a high speed digital phase frequency detector circuit. The circuit determines the “lead”
or “lag” phase relationship and time difference between the leading edges of the VCO (fp) signal and the reference (fr) input.
Since these edges occur only once per cycle, the detector has a range of ±2π radians. The phase comparator outputs are
standard CMOS rail–to–rail levels (VP to GND for φP and VCC to GND for φR), designed for up to 20MHz operation into a 15pF
load. These phase comparator outputs can be used along with an external charge pump to enhance the PLL characteristics.
The operation of the phase comparator is shown in Figures 3 and 5. The phase characteristics of the phase comparator are
controlled by the FC pin. The polarity of the phase comparator outputs, φR and φP, as well as the charge pump output Do can be
reversed by switching the FC pin.
H
fr
L
H
fp
L
H
LD
L
Source
Z
Sink
Do (FC = H)
BISW (LE = H or Open)
H
φR (FC = H)
L
H
φP (FC = H)
L
Source
Z
Sink
Do (FC = L)
BISW (LE = H or Open)
H
φR (FC = L)
L
H
φP (FC = L)
L
NOTES: Do and BISW are current outputs.
Phase difference detection range: –2π to +2π
Spike difference depends on charge pump characteristics. Also, the spike is output in order to diminish dead band.
When fr > fp or fr < fp, spike might not appear depending upon charge pump characteristics.
Internal Charge Pump Gain
[
Ť
)
Isource Isink
4p
Ť+
4mA
4p
Figure 3. Phase/Frequency Detector, Internal Charge Pump and Lock Detect Waveforms
MOTOROLA
6
HIPERCOMM
BR1334 — Rev 4
MC12202
For FC = HIGH:
fr lags fp in phase OR fp>fr in frequency
When the phase of fr lags that of fp or the frequency of fp is greater than fr, the φP output will remain in a HIGH state while the φR
output will pulse from LOW to HIGH. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition.
The signal on φR indicates to the VCO to decrease in frequency to bring the loop into lock.
fr leads fp in phase OR fp<fr in frequency
When the phase of fr leads that of fp or the frequency of fp is less than fr, the φR output will remain in a LOW state while the φP
output pulses from HIGH to LOW. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition.
The signal on φP indicates to the VCO to increase in frequency to bring the loop to lock.
fr = fp in phase and frequency
When the phase and frequency of fr and fp are equal, the output φP will remain in a HIGH state and φR will remain in a LOW state
except for voltage spikes when signals are in phase. This situation indicates that the loop is in lock and the phase comparator will
maintain the loop in its locked state.
When FC = LOW, the operation of the phase comparator is reversed from the above explanation.
For FC = LOW:
fr lags fp in phase OR fp>fr in frequency
When the phase of fr lags that of fp or the frequency of fp is greater than fr, the φR output will remain in a LOW state while the φP
output will pulse from HIGH to LOW. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition.
The signal on φP indicates to the VCO to increase in frequency to bring the loop into lock.
fr leads fp in phase OR fp<fr in frequency
When the phase of fr leads that of fp or the frequency of fp is less than fr, the φP output will remain in a HIGH state while the φR
output pulses from LOW to HIGH. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition.
The signal on φR indicates to the VCO to decrease in frequency to bring the loop to lock.
fr = fp in phase and frequency
When the phase and frequency of fr and fp are equal, the output φP will remain in a HIGH state and φR will remain in a LOW state
except for voltage spikes when signals are in phase. This situation indicates that the loop is in lock and the phase comparator will
maintain the loop in its locked state.
The FC pin controls not only the phase characteristics, but also controls the fOUT test pin. The FC pin permits the user to monitor
either of the phase comparator input signals, fr or fp, at the fOUT output providing a test mode where the programming of the
dividers and the output of the counters can be checked. When FC is HIGH, fOUT = fr, the programmable reference divider output.
When FC is LOW, fOUT = fp, the programmable divider output.
Hence,
If VCO characteristics are like (1), FC should be set HIGH or OPEN. fOUT = fr
If VCO characteristics are like (2), FC should be set LOW.
fOUT = fp
VCO OUTPUT FREQUENCY
(1)
FC = HIGH or OPEN
FC = LOW
Do
φR
φP
fOUT
Do
φR
φP
fOUT
fp < fr
H
L
L
fr
L
H
H
fp
fp > fr
L
H
H
fr
H
L
L
fp
fp = fr
Z
L
H
fr
Z
L
H
fp
NOTE: Z = High impedance
When LE is HIGH or Open, BISW has the same characteristics
as Do.
(2)
VCO INPUT VOLTAGE
Figure 5. Phase Comparator, Internal Charge Pump, and
fOUT Characteristics
Figure 4. VCO Characteristics
HIPERCOMM
BR1334 — Rev 4
7
MOTOROLA
MC12202
fr
UP
0
φP
R
1
fp
PHASE
FREQUENCY
DETECTOR
0
DOWN
φR
V
1
LD
PHASE COMPARATOR
CHARGE
PUMP 1
Do
CHARGE
PUMP 2
BISW
FC
LE
Figure 6. Detailed Phase Comparator Block Diagram
LOCK DETECT
The Lock Detect (LD) output pin provides a LOW pulse when fr and fp are not equal in phase or frequency. The output is normally
HIGH. LD is designed to be the logical NORing of the phase frequency detector’s outputs UP and DOWN. See Figure 6. In typical
applications the output signal drives external circuitry which provides a steady LOW signal when the loop is locked. See Figure 9.
OSCILLATOR INPUT
For best operation, an external reference oscillator is recommended. The signal should be AC–coupled to the OSCin pin through
a coupling capacitor. In this case, no connection to OSCout is required. The magnitude of the AC–coupled signal must be
between 500 and 2200 mV peak–to–peak. To optimize the phase noise of the PLL when used in this mode, the input signal
amplitude should be closer to the upper specification limit. This maximizes the slew rate of the signal as it switches against the
internal voltage reference.
The device incorporates an on–chip reference oscillator/buffer so that an external parallel–resonant fundamental crystal can be
connected between OSCin and OSCout. External capacitor C1 and C2 as shown in Figure 10 are required to set the proper
crystal load capacitance and oscillator frequency. The values of the capacitors are dependent on the crystal chosen (up to a
maximum of 30 pF each including parasitic and stray capacitance).
DUAL INTERNAL CHARGE PUMPS (“ANALOG SWITCH”)
Due to the pure Bipolar nature of the MC12202 design, the “analog switch” function is implemented with dual internal charge
pumps. The loop filter time constant can be decreased by bypassing the first stage of the loop filter with the charge pump output
BISW as shown in Figure 7 below. This enables the VCO to lock in a shorter amount of time.
When LE is HIGH or OPEN (“analog switch is ON”), the output of the second internal charge pump is connected to the BISW pin,
and the Do output is ON. The charge pump 2 output on BISW is essentially equal to the charge pump 1 output on Do. When LE is
LOW, BISW is in a high impedance state and Do output is active.
CHARGE
PUMP 1
CHARGE
PUMP 2
Do
LPF–1
LPF–2
VCO
BISW
LE
Figure 7. “Analog Switch” Block Diagram
MOTOROLA
8
HIPERCOMM
BR1334 — Rev 4
MC12202
ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5V; TA = –40 to +85°C)
Symbol
ICC
Parameter
Min
Supply Current for VCC
IP
Supply Current for VP
FIN
Operating Frequency
FOSC
VIN
fINmax
fINmin
Typ
Max
Unit
5.8
9.0
mA
7.2
10.5
0.7
1.1
0.8
1.3
mA
Note 4
MHz
Note 5
20
MHz
Crystal Mode
40
MHz
External Reference Mode
fIN
200
1000
mVP–P
OSCin
500
2200
mVP–P
VIH
Input HIGH Voltage
CLK, DATA, LE, FC
VIL
Input LOW Voltage
CLK, DATA, LE, FC
IIH
Input HIGH Current (DATA and CLK)
IIL
Input LOW Current (DATA and CLK)
IOSC
Input Current (OSCin)
IIH
Input HIGH Current (LE and FC)
IIL
Input LOW Current (LE and FC)
–75
–60
ISource6
ISink6
Charge Pump Output Current
–2.6
–2.0
–1.4
Do and BISW
+1.4
+2.0
+2.6
IHi–Z
0.7VCC
V
0.3VCC
V
VCC = 5.5V
2.0
µA
VCC = 5.5V
–5.0
µA
VCC = 5.5V
130
–310
µA
OSCin = VCC
OSCin = VCC – 2.2V
1.0
–10
1.0
Output HIGH Voltage (LD, φR, φP, fOUT)
µA
mA
VDo = VP/2; VP = 2.7V
VBISW = VP/2; VP = 2.7V
+15
nA
0.5 < VDO < VP–0.5
0.5 < VBISW < VP–0.5
4.4
V
VCC = 5.0V
2.4
V
VCC = 3.0V
0.4
V
VCC = 5.0V
0.4
V
VCC = 3.0V
Output LOW Voltage (LD, φR, φP, fOUT)
VOL
µA
2.0
–15
VOH
Note 3
100
12
VOSC
Note 1
Note 2
1100
Operating Frequency (OSCin)
Input Sensitivity
Condition
IOH
Output HIGH Current (LD, φR, φP, fOUT)
–1.0
IOL
Output LOW Current (LD, φR, φP, fOUT)
1.0
1. VCC = 3.3V, all outputs open.
2. VCC = 5.5V, all outputs open.
3. VP = 3.3V, all outputs open.
mA
mA
4. VP = 6.0V, all outputs open.
5. AC coupling, FIN measured with a 1000pF capacitor.
6. Source current flows out of the pin and sink current flows into the pin.
VP
VCC
10kΩ
φP
12kΩ
100kΩ
33kΩ
LD
EXTERNAL CHARGE
PUMP OUTPUT
φR
LOCK DETECT
OUTPUT
0.01µF
12kΩ
10kΩ
10kΩ
Figure 8. Typical External Charge Pump Circuit
HIPERCOMM
BR1334 — Rev 4
Figure 9. Typical Lock Detect Circuit
9
MOTOROLA
MC12202
C1
1
2
16
φR
OSCin
15
φP
OSCout
VCO
CHARGE PUMP SELECTION
(INTERNAL OR EXTERNAL)
C2
VP
3
100pF
LOW PASS
FILTER
(SEE FIGURE 11)
EXTERNAL
CHARGE PUMP
(SEE FIGURE 8)
VP
FOUT
VCC
BISW
14
0.1µF
VCC
4
100pF
0.1µF
5
6
LOCK
DETECT
LOCK DETECT
CIRCUIT
(SEE FIGURE 9)
7
13
MC12202
Do
FC
GND
LE
LD
12
11
10
DATA
47kΩ
8
fin
FROM
CONTROLLER
9
CLK
1000pF
47kΩ
C1, C2: Dependent on Crystal Oscillator
Figure 10. Typical Applications Example (16–Pin Package)
BISW
Do OR EXTERNAL
CHARGE PUMP
VCO
R
C
Figure 11. Typical Loop Filter
MOTOROLA
10
HIPERCOMM
BR1334 — Rev 4
MC12202
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
1
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
DIM
A
B
C
D
F
G
J
K
M
P
R
F
R X 45°
C
–T
SEATING
–
J
M
PLANE
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
M SUFFIX
PLASTIC SOIC PACKAGE
CASE 966–01
ISSUE O
16
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5 THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
9
Q1
M_
E HE
L
8
1
DETAIL P
Z
D
e
VIEW P
A
c
A1
b
0.13 (0.005)
HIPERCOMM
BR1334 — Rev 4
M
0.10 (0.004)
11
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10
0_
_
0.70
0.90
--0.78
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.031
MOTOROLA
MC12202
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X
0.15 (0.006) T U
K REF
0.10 (0.004)
S
M
T U
S
V
S
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
2X
L/2
20
11
B
L
J J1
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
NOTES:
6 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
7 CONTROLLING DIMENSION: MILLIMETER.
8 DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
9 DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
10 DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
11 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
12 DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
M
A
–V–
N
F
DETAIL E
–W–
C
G
D
H
DETAIL E
0.100 (0.004)
–T– SEATING
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
PLANE
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
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Literature Distribution Centers:
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MOTOROLA
◊
CODELINE TO BE PLACED HERE
12
*MC12202/D*
HIPERCOMM
MC12202/D
BR1334 — Rev 4