MOTOROLA MC14097BCP

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14067B
MC14097B
Analog
Multiplexers/Demultiplexers
The MC14067 and MC14097 multiplexers/demultiplexers are digitally
controlled analog switches featuring low ON resistance and very low
leakage current. These devices can be used in either digital or analog
applications.
The MC14067 is a 16–channel multiplexer/demultiplexer with an inhibit
and four binary control inputs A, B, C, and D. These control inputs select
1–of–16 channels by turning ON the appropriate analog switch (see
MC14067 truth table.)
The MC14097 is a differential 8–channel multiplexer/demultiplexer with an
inhibit and three binary control inputs A, B, and C. These control inputs
select 1 of 8 pairs of channels by turning ON the appropriate analog switches
(see MC14097 truth table).
•
•
•
•
•
•
•
L SUFFIX
CERAMIC
CASE 623
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
Low OFF Leakage Current
Matched Channel Resistance
Low Quiescent Power Consumption
Low Crosstalk Between Channels
Wide Operating Voltage Range: 3 to 18 V
Low Noise
Pin for Pin Replacement for CD4067B and CD4097B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
TA = – 55° to 125°C for all packages.
MC14097B
Dual 8–Channel Analog
Multiplexer/Demultiplexer
MC14067B
16–Channel Analog
Multiplexer/Demultiplexer
CONTROLS
SWITCHES
IN/OUT
15
10
11
14
13
9
8
7
6
5
4
3
2
23
22
21
20
19
18
17
16
INHIBIT
A
B
C
D
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
X
Plastic
Ceramic
SOIC
CONTROLS
13
10
11
14
INHIBIT
A
B
C
SWITCHES
IN/OUT
9
8
7
6
5
4
3
2
23
22
21
20
19
18
16
15
X0
X1
X2
X3
X4
X5
X6
X7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
COMMON
1
OUT/IN
VDD = PIN 24
VSS = PIN 12
X
1
COMMONS
OUT/IN
Y
17
REV 3
1/94
MOTOROLA
Motorola, Inc. 1995
CMOS LOGIC DATA
MC14067B MC14097B
1
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MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Vin, Vout
Input or Output Voltage (DC or Transient)
Value
Unit
– 0.5 to + 18.0
V
– 0.5 to VDD + 0.5
V
mA
Iin
Input Current (DC or Transient),
per Control Pin
± 10
Isw
Switch Through Current
± 25
mA
PD
Power Dissipation, per Package†
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
260
_C
TL
Lead Temperature (8–Second Soldering)
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
v
v
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
MC14067 TRUTH TABLE
Control Inputs
MC14097 TRUTH TABLE
Control Inputs
A
B
C
D
Inh
Selected
Channel
A
B
C
Inh
X
0
1
0
X
0
0
1
X
0
0
0
X
0
0
0
1
0
0
0
None
X0
X1
X2
X
0
1
0
X
0
0
1
X
0
0
0
1
0
0
0
X0
X1
X2
Y0
Y1
Y2
1
0
1
0
1
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
X3
X4
X5
X6
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
X7
X8
X9
X10
1
0
1
0
1
1
0
0
1
1
0
1
1
1
1
0
0
0
0
0
X3
X4
X5
X6
X7
Y3
Y4
Y5
Y6
Y7
1
0
1
0
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
X11
X12
X13
X14
X15
INHIBIT
A
B
C
D
X
IN/OUT
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
MC14067B MC14097B
2
None
X = Don’t Care
MC14067 FUNCTIONAL DIAGRAM
CONTROL
INPUTS
Selected
Channels
MC14097 FUNCTIONAL DIAGRAM
CONTROL
INPUTS
1–OF–16 DECODER
X
IN/OUT
X
OUT/IN
Y
IN/OUT
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
1–OF–8 DECODER
X
OUT/IN
Y
OUT/IN
MOTOROLA CMOS LOGIC DATA
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ELECTRICAL CHARACTERISTICS
25_C
– 55°C
Characteristic
Symbol
VDD
Test Conditions
125_C
Min
Max
Min
Typ #
Max
Min
Max
Unit
3.0
18
3.0
—
18
3.0
18
V
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µA
SUPPLY REQUIREMENTS (Voltages Referenced to VSS)
Power Supply Voltage
Range
VDD
—
Quiescent Current Per
Package
IDD
5.0
10
15
Control Inputs: Vin =
VSS or VDD,
Switch I/O: VSS
VI/O
VDD, and
∆Vswitch 500 mV**
ID(AV)
5.0
10
15
TA = 25_C only (The
channel component,
(Vin – Vout)/Ron, is
not included.)
Total Supply Current
(Dynamic Plus
Quiescent,
Per Package
µA
(0.07 µA/kHz) f + IDD
(0.20 µA/kHz) f + IDD
(0.36 µA/kHz) f + IDD
Typical
CONTROL INPUTS — INHIBIT, A, B, C, D (Voltages Referenced to VSS)
Low–Level Input Voltage
VIL
5.0
10
15
Ron = per spec,
Ioff = per spec
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
V
High–Level Input Voltage
VIH
5.0
10
15
Ron = per spec,
Ioff = per spec
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
V
Input Leakage Current
Iin
15
Vin = 0 or VDD
—
± 0.1
—
± 0.00001
± 0.1
—
1.0
µA
Input Capacitance
Cin
—
—
—
—
5.0
7.5
—
—
pF
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y (Voltages Referenced to VSS)
Recommended Peak–to–
Peak Voltage Into or
Out of the Switch
VI/O
—
Channel On or Off
0
VDD
0
—
VDD
0
VDD
Vp–p
Recommended Static or
Dynamic Voltage
Across the Switch’*
(Figure 1)
∆Vswitch
—
Channel On
0
600
0
—
600
0
300
mV
Output Offset Voltage
VOO
—
Vin = 0 V, No Load
—
—
—
10
—
—
—
µV
ON Resistance
Ron
5.0
10
15
∆Vswitch
500 mV**,
Vin = VIL or VIH
(Control), and Vin
0 to VDD (Switch)
—
—
—
800
400
220
—
—
—
250
120
80
1050
500
280
—
—
—
1300
550
320
Ω
∆Ron
5.0
10
15
—
—
—
70
50
45
—
—
—
25
10
10
70
50
45
—
—
—
135
95
65
Ω
Ioff
15
Vin = VIL or VIH
(Control) Channel to
Channel or Any One
Channel
—
± 100
—
± 0.05
± 100
—
± 1000
nA
Capacitance, Switch I/O
CI/O
—
Inhibit = VDD
—
—
—
10
—
—
—
pF
Capacitance, Common O/I
CO/I
—
Inhibit = VDD
(MC14067B)
(MC14097B)
—
—
—
—
—
—
100
60
—
—
—
—
—
—
—
—
—
0.47
—
—
—
∆ON Resistance Between
Any Two Channels
in the Same Package
Off–Channel Leakage
Current (Figure 2)
Capacitance, Feedthrough
(Channel Off)
CI/O
—
—
Pins Not Adjacent
Pins Adjacent
pF
pF
Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
** For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e.
the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.)
MOTOROLA CMOS LOGIC DATA
MC14067B MC14097B
3
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD – VSS
Vdc
Typ #
Max
tPLH, tPHL
Propagation Delay Times
Channel Input–to–Channel Output (RL = 200 kΩ)
MC14067B
(Figure 3)
MC14097B
Control Input–to–Channel Output
Channel Turn–On Time (RL = 10 kΩ)
MC14067B/097B
tPZH, tPZL
Channel Turn–Off Time (RL = 300 kΩ)
MC14067B/097B
tPHZ, tPLZ
(Figure 4)
(Figure 4)
ns
5.0
10
15
35
15
12
90
40
30
5.0
10
15
25
10
7
65
25
18
5.0
10
15
240
115
75
600
290
190
ns
5.0
10
15
250
120
75
625
300
190
ns
5.0
10
15
280
115
85
700
290
215
(Figure 10)
5.0
10
15
250
100
75
625
250
190
—
10
0.3
—
MC14097B
ns
Second Harmonic Distortion
(RL = 10 kΩ, f = 1 kHz, Vin = 5 Vp–p)
ON Channel Bandwidth
[RL = 1 kΩ, Vin = 1/2 (VDD – VSS) p–p(sine–wave)]
20 Log10 (Vout/Vin) = – 3 dB
BW
MC14067B
MC14097B
Off Channel Feedthrough Attenuation
[RL = 1 kΩ, Vin = 1/2 (VDD–VSS) p–p(sine–wave)]
fin = 20 MHz – MC14067B
fin = 12 MHz – MC14097B
Channel Separation
[RL = 1 kΩ, Vin = 1/2 (VDD–VSS) p–p (sine–wave)]
%
MHz
(Figure 5)
10
10
15
25
—
—
—
10
– 40
—
dB
10
– 40
—
dB
10
30
—
mV
(Figure 5)
—
fin = 20 MHz
Crosstalk, Control Inputs–to–Common O/I
(R1 = 1 kΩ, RL = 10 kΩ,
Control tr = tf = 20 ns, Inhibit = VSS)
ns
ns
tPLH, tPHL
Any Pair of Address Inputs to Output
MC14067B
Unit
(Figure 6)
—
(Figure 7)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MC14067B MC14097B
4
MOTOROLA CMOS LOGIC DATA
OFF CHANNEL UNDER TEST
VDD
A
VSS
ON SWITCH
CONTROL
SECTION
OF IC
CONTROL
SECTION
OF IC
OTHER
CHANNEL(S)
LOAD
VSS
VDD
V
SOURCE
VSS
VDD
Figure 1. ∆V Across Switch
MC14067B
PIN ASSIGNMENT
Figure 2. Off Channel Leakage
MC14097B
PIN ASSIGNMENT
X
1
24
VDD
X
1
24
VDD
X7
2
23
X8
X7
2
23
Y0
X6
3
22
X9
X6
3
22
Y1
X5
4
21
X10
X5
4
21
Y2
X4
5
20
X11
X4
5
20
Y3
X3
6
19
X12
6
19
Y4
X2
7
18
X13
X2
7
18
Y5
X3
X1
8
17
X14
X1
8
17
Y
X0
9
16
X15
X0
9
16
Y6
A
10
15
INHIBIT
A
10
15
Y7
B
11
14
C
B
11
14
C
D
VSS
12
13
INHIBIT
VSS
12
13
MOTOROLA CMOS LOGIC DATA
MC14067B MC14097B
5
VC
PULSE
GENERATOR
VDD
A
B
C
D
Vout
INH
RL
VDD VSS VSS VDD
20 ns
Vin
90%
50%
tPLH
20 ns
90%
50%
10%
VC
20 ns
Vin
VX
Vin
CL = 50 pF
VDD
10%
90%
Vout
VSS
tPHL
50%
tPZH, tPZL
50%
Vout
Vout
Figure 3. Propagation Delay Test Circuit
and Waveforms Vin to Vout
tPHZ, tPLZ
50%
10%
VDD
RL
Vin = VSS
VX = VDD
RL
A
B
C
D
ON
INH
OFF
Vout
INH
Vin = VDD
VX = VSS
Figure 4. Turn–On and Delay Turn–Off
Test Circuit and Waveforms
A, B, and C inputs used to turn ON or OFF
the switch under test.
A
B
C
D
CL = 50 pF
RL
Vout
INH
20 ns
A
B
C
D
RL
CL = 50 pF
Vout
CL = 50 pF
Vin
Vin
Figure 5. Bandwidth and Off–Channel
Feedthrough Attenuation
VC
Figure 6. Channel Separation
(Adjacent Channels Used for Setup)
A
B
C
D
Vout
RL
INH
CL = 50 pF
R1
Figure 7. Crosstalk, Control to Common O/I
MC14067B MC14097B
6
MOTOROLA CMOS LOGIC DATA
VA
VB
A
B
C
D
INH
CL
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
VDD
1 kΩ
RANGE
X–Y
PLOTTER
VDD
Vout
VA
50%
VB
50%
tPHL
VSS
tPLH
50%
Vout
Figure 8. Channel Resistance (RON) Test Circuit
Figure 9. Propagation Delay, Any Pair of
Address Inputs to Output
350
300
300
250
200
150
100
25°C
– 55°C
50
0
– 10
R ON , “ON” RESISTANCE (OHMS)
TA = 125°C
– 8.0 – 6.0 – 4.0 – 2.0
0
0.2
4.0
6.0
8.0
R ON , “ON” RESISTANCE (OHMS)
350
250
200
150
25°C
– 55°C
50
– 8.0 – 6.0 – 4.0 – 2.0
0
0.2
4.0
6.0
8.0
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 10. VDD = 7.5 V, VSS = – 7.5 V
Figure 11. VDD = 5.0 V, VSS = – 5.0 V
700
350
600
300
500
400
300
TA = 125°C
200
25°C
100
0
– 10
TA = 125°C
100
0
– 10
10
RON , “ON” RESISTANCE (OHMS)
R ON , “ON” RESISTANCE (OHMS)
TYPICAL RESISTANCE CHARACTERISTICS
– 55°C
– 8.0 – 6.0 – 4.0 – 2.0
0
0.2
4.0
6.0
8.0
10
TA = 25°C
250
VDD = 2.5 V
200
150
5.0 V
100
7.5 V
50
0
– 10
– 8.0 – 6.0 – 4.0 – 2.0
0
0.2
4.0
6.0
8.0
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 12. VDD = 2.5 V, VSS = – 2.5 V
Figure 13. Comparison at 25°C, VDD = – VSS
MOTOROLA CMOS LOGIC DATA
10
10
MC14067B MC14097B
7
APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Multiplexer/Demultiplexer. The 0–to–5 volt Digital Control signal is used to
directly control a 5 Vp–p analog signal.
The digital control logic levels are determined by VDD and
VSS. The VDD voltage is the logic high voltage; the VSS voltage is logic low. For the example. VDD = + 5 V = logic high at
the control inputs; VSS = GND = 0 V = logic low.
The maximum analog signal level is determined by V DD
and VSS. The analog voltage must swing neither higher than
V DD nor lower than V SS. The example shows a 5 V p–p signal
which allows no margin at either peak. If voltage transients
above VDD and/or below VSS are anticipated on the analog
channels, external diodes (Dx) are recommended as shown
in Figure B. These diodes should be small signal types able
to absorb the maximum anticipated current surges during
clipping.
The absolute maximum potential difference between VDD
and VSS is 18.0 volts. Most parameters are specified up to
15 V which is the recommended maximum difference
between VDD and VSS.
+5 V
VDD
VSS
+ 5.0 V
5 Vp–p
ANALOG SIGNAL
SWITCH
I/O
COMMON
O/I
+5 V
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
5 Vp–p
ANALOG SIGNAL
+ 2.5 V
GND
MC14067B
MC14097B
0–TO–5 V DIGITAL
CONTROL SIGNALS
Figure A. Application Example
VDD
VDD
DX
DX
SWITCH
I/O
COMMON
O/I
DX
VSS
DX
VSS
Figure B. External Germanium or Schottky Clipping Diodes
MC14067B MC14097B
8
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 623–05
ISSUE M
24
NOTES:
1. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION (WHEN FORMED
PARALLEL).
13
B
1
12
DIM
A
B
C
D
F
G
J
K
L
M
N
A
F
SEATING
PLANE
C
L
N
D
G
INCHES
MIN
MAX
1.230
1.290
0.500
0.610
0.160
0.220
0.016
0.020
0.050
0.060
0.100 BSC
0.008
0.012
0.125
0.160
0.600 BSC
0_
15_
0.020
0.050
J
M
K
MILLIMETERS
MIN
MAX
31.24
32.77
12.70
15.49
4.06
5.59
0.41
0.51
1.27
1.52
2.54 BSC
0.20
0.30
3.18
4.06
15.24 BSC
0_
15 _
0.51
1.27
P SUFFIX
PLASTIC DIP PACKAGE
CASE 709–02
ISSUE C
24
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
13
B
1
12
A
L
C
N
K
H
F
G
D
MOTOROLA CMOS LOGIC DATA
SEATING
PLANE
M
J
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
31.37
32.13
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.03
0.20
0.38
2.92
3.43
15.24 BSC
0_
15_
0.51
1.02
INCHES
MIN
MAX
1.235
1.265
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.080
0.008
0.015
0.115
0.135
0.600 BSC
0_
15_
0.020
0.040
MC14067B MC14097B
9
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
–A–
24
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
13
–B–
12X
P
0.010 (0.25)
1
M
B
M
12
24X
D
J
0.010 (0.25)
M
T A
S
B
S
F
R
C
–T–
SEATING
PLANE
M
22X
K
G
X 45 _
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0_
8_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0_
8_
0.395
0.415
0.010
0.029
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MC14067B MC14097B
10
◊
*MC14067B/D*
MOTOROLA CMOS LOGIC
DATA
MC14067B/D