MC146818A
I
Advance
I
Information
CMOS
I
\
REAL-TIME CLOCK PLUS RAM (RTC)
The MC146818A Real-Time Clock plus RAM is a peripheral device
which includes the unique MOTEL concept for use with various
microprocessors,
microcomputers,
and larger computers. This part
combines three unique features: a complete time-of-day clock with
alarm and one hundred year calendar, a programmable periodic interrupt and square-wave generator, and 50 bytes of low-power static
RAM. The MC146818A uses high-speed CMOS technology to interface
with 1 MHz processor buses, while consuming very little power.
The Real-Time Clock plus RAM has two distinct uses. First, it is
designed as a battery powered CMOS part (in an otherwise NMOS/TTL
system) including all the common battery backed-up functions such as
RAM, time, and calendar. Secondly, the MC146818A maybe used with
a CMOS microprocessor to relieve the software of the timekeeping
,~~
workload and to extend the available RAM of an MPU such as the ., “’~:$
,!!:\’;
.\,i,.
,..
MC146805E2.
.....
,.,.>*t!F\+
{k ~\}t
● Low-Power, High-Speed CMOS
,1, $s,,..
~;, ~p
)>.
● Internal Time Base and Oscillator
‘,&~$$~.
Q.%~!*
*>sq,.,,\
,$4:*,
$+.~:;;,
. ..~.
O Counts Seconds, Minutes, and Hours of the Day
“’t:>?,.
● Counts Days of the Week, Date, Month, and Year
,$:
;<4 ,
..!.*:,:
● 3 V to 6 V Operation
~t.k,$,.,
● Time Base Input Options: 4.194304 MHz, 1.048ti
,,,,,,M,
,)$f,~~z, or 32.7W
,$\<..%.\., ...*<.*$,
kHz
,,:,,
. ..i,;t~
● Time Base Oscillator for Parallel Resonan~$$~{S]s
.~;\l..
.
● 40 to 200 pW Typical Operating Power{,~L:~#~ ‘Frequency Time Base
● 4.0 to 20 mW Typical Operating Po.~%j~*$?gh
● Binary or BCD Representation
Frequency Time Base
,~$.~,,,
~fTW~
Calendar, and Alarm
● 12- or 24-Hour Clock with ,$$,>
A~$oQ$PM
:,.,
.$k,..?.l
,{+<,
u“
CASE 623
I
in 12-Hour Mode
● Daylight
Savings Time OplWn ‘$
*;* $*,,$$
● Automatic End of Mo~:~’’~$e6gnition
● Automatic Leap Y~r ~&&~ensation
PIN ASSIGNMENT
● Microprocessor#$@t@mpatible
~‘.$$*$
● Selectable Ba$W&n’Wotorola
and Competitor Bus Timing
, -~.,y,
}$~*
● Multiplex@:~@
fbr Pin Efficiency
~’.,-,,
● lnterfq&$&%@% Software as 64 RAM Locations
Oscl
~vDD
[
23 ] SQW
● 14 B~es:$’~CIOck
,,*J
0SC2
[ 3
22 ] Ps
and Control Registers
● ~’~~~~$i’of General Purpose RAM
... ~.
@x;.$J&%ws
Bit indicates Data Integrity
?{&us Compatible Interrupt Signals (~Q)
..
● Three Interrupts are Separately Software Maskable and Testable
Time-of-Day Alarm, Once-per-Second to Once-per-Day
Periodic Rates from 30.5 ps to 500 ms
End-of-Clock Update Cycle
● Programmable
Square-Wave Output Signal
● Clock Output May Be Used as Microprocessor
At Time Base Frequency -1 or +4
● 24-Pin Dual-In-Line
● Quad Pack Also
Clock Input
Package
‘oT
2
ADO [ 4
21 JCKOUT
AD1 [ 5
20 ] CKFS
AD2 [ 6
lg ] l~Q
AD3 [ 7
18 ] RESET
AD4 [ 8
17 ] DS
AD5 c g
16 ] STBY
AD6 [ 10
15 ] Rl~
AD7 [ 11
14 ] AS
Vss [ 12
13 ]=
Available
.
hls document contains !ntormatlon on a new product. Specltlcatlons and tntormatlon here!n
are subject to change without notice
)MOTOROLAINC,,
lW
ADI-1026
FIGURE
1 –
BLOCK
DIAGRAM
—
+
Clock
output
~
CKOUT
~
CKFS
sow
~Q
RESET
Ps
User RAM
(50 Bytes)
v
,i,>,~
. ~><.,
~:*.,*.*$:, \ h .
. ..
?+
$.;).,,<,:?
,’<;}.:
-
MAXIMUM
RATINQ~~(@oJjages
R~$n&
Supply
Volta~J**
“~:?’
OSC1
Current ~rai~~r
Pin Excluding
Vmi,a%q,.vs s
Op&~~~&Temperature
‘~%$~6818A
THERMAL
Vin
Range
Unit
Value
–0.3
v
to +8.0
v
V5S– O.5 to VDD+O.5
10
TA
TL to TH
0 to 70
– 40 to 85
–55to
Tstg
This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS =(Vin
or Voutl
s VDD. Reliability of operation is enhanced if
unused inputs are tied to an appropriate logic
voltage level (e. g., either VSS or VDD).
mA
I
Range
‘<@c146818AC
Storage Temperature
Symbol
VDD
“ ‘$?
All Input V:$~&.~xcept
to VSS)
referenced
Oc
+150
Oc
CHARACTERISTICS
Symbol
Characteristic
Thermal Resistance
Plastic
Cerdlp
Ceramic
I
9JA
MOTOROLA
@
I Value
I 120I
65
50
Unit
“c/w
I
Semiconductor
Products Inc.
2
—
)C ELECTRICAL CHARACTERISTICS
(vD D = 3 Vdc, vs s = O Vdc, TA = Tl to TH unless otherwise noted)
Characteristics
I Symbol I
Min
32.768
—
32.768
Output Voltage
fosc
vOL
lLoad< lOpA
vOH
VDD– O.1
–
IDD3
–
50
IDD4
–
Output High Voltege
(l Load= – 0.25 mA, All Outputs)
vOH
2.7
Output Low Voltage
(i Load= 0.25 mA, All
VOL
Frequency of Operation
IDD – Bus Idle
CKOUT=fosc,
CL= 15 pF; SOW Disabled, STBY=O.2
fosc=32.76B kHz
IDD – Quiescent
fosc= DC; OSC1 = DC;
All Other lnpUtS=vDD–0.2
NO Clock
Input Low Voltage
Input Current
Three-State
.::.
Iin
——
— AS, DS, R/~
MOT, OSCI, CE, STBY, RESET, CKFS, PS
Leakage
IRQ, ADO-AD7
m
MOTOROkA
Semiconductor
3
I
—
I
v
v
0.5
v
I
* 10
*I
PA
* 10
WA
+10
*1
,
1
ITSL
0.3
VDD
VDD
VDD
Vss
–
1
Three-State
v
A&fi%$k
“~
{?.
50
$“’:#$, !,
,,~ i:”
:,.:
,.~~~.+
,.,...
. .:s. ‘ .. ~+
i,,..
..,t>.$.
‘:.*$
\k;~#
\
~,
. ..,.
..%
)$
i’t”
*.,+,.,/,
~-.>,,->,
t +?’+’~’’t;;k~
v
?J
<t~tl,
\k*t
,,}
$i.,,,,
-$.*;,,’:,: ~
IRQ, AD@@fl~lTsL
Input Current
0.1
——
, %&$$y’
vlH
STBY, ADO-AD7, DS, AS, R/W, CS
.,$,@,q.,
RESET, CKFS, PS, OSC1
‘$:?y$:
~ ~?:,
,,. ‘k$,’w.~’D
MOT
——
vlL ‘?$yvss
ADO-AD7, DS, AS, R/W, CS, CKFS, PS, RESET, OSCI
Vss
MOT .#vj
AS, DS, R/~F ~~:$~
–
——
—
MOT, OSCI, CE, STBY, RESET, CKFS, ,P#
‘$ ‘“
Leakage
I
kHz
.\,
OUtpUtS)
~,
Unit
I
V; CL (OSC2)= 10 pF
V;
Input High Voltage
Max
I
–
Products Inc.
AA
I
*IO
PA
I
1
BUS TIMING
VDD=5.O V
*lo%
1 TTL and
130 pF Load
Vnn=3.O V
ti;F
Load
Ident.
Number
Characteristi~
1
Cycle Time
DS/E Low or ~D/WR High
——
DS/E High or RD/WR Low
Symbol
Min
Max
Min
Max
Unit
tcvc
PWEL
5000
953
dc
ns
lm
–
—
300
–
ns
PWEH
15m
—
325
–
ns
tr, tf
—
100
—
30
ns
–
—
ns
2
Pulse Width,
3
Pulse Width,
4
Input Rise and Fall Time
8
R/~
Hold Time
tRWH
10
–
10
13
R/~
Setup Time Before DS/E
tRWS
2m
–
80
–
—
25
14
Chip Select Setup Time Before DS, ~R,
tcs
200
15
Chip Select Hold Time
tCH
10
18
Read Data Hold Time
tDHR
10
21
Write Data Hold Time
24
Muxed
Address
Valid Time to AS/ALE
25
I Muxed
Address
Hold Time
26
DelaV Time DS/E
27
Pulse Width,
28
DelaV Time,
30
31
tnu\A/
to AS/ALE
Fall
I
Rise
100
–
tASL
2~
–
tAHL—
100
tASD
m
I
10
o
I
–
50 ,~p+:;a
w
–
6~
tASED
500
*
Peripheral Output Data Delay Time from DS/ E or ~
tDDR
1300
Peripheral Data Setup Time
tDSW
tSBS
1q$.ii ~. ~’
~Q:@:J~$+’3’–
AS/ALE
AS/ALE
pwAs
High
to DS/E
Rise
S~
Setup Time before AS/ALE
33
S~
Hold Time after AS/ALE
Designations
E, ALE, ~,
* Refer to IMPORTANT
NOTICES
Rise
tSBH
Fall
and ~R
appearing
refer to signals from alternative
on page 20 of this data :~~t,
.,
H
.,......
Mp;cessor
‘~+.k
.
_
“’
~*..~y>>,
. ..s..’
“t “‘
%:.\tf.,:/?@
ax..
,.!>.
.,~.,.,.?
~...‘,’!..~,~
‘.?.?~i~,.
~,
:,
$~B~~ ~
“~$
,:,,,
*.#*..,...,:{
~s %+.<.$..
,,.
~: m
—
~~
~;~e.:
— ,,~r$
o
Im
, ‘*
– *,i$ ;~J$$95
32
NOTE:
or ~D
—
I
n:SI
ns
.—
ns
—
ns
20
240
ns
2m
–
ns
TBD
–
TBD
–
I
ns
signals.
-.
Note:
V, VLOW=O.8 V, for VDD=5.O V +IOYO for outputs only.
V for outputs onlv.
V, VLOW=O.5 V, for VDD=3.O
VHIGH=VDD–2.O
VHIGH=2.O
MOTOROLA
@
Semiconductor
4
Products Inc.
FIGURE 3 – BUS READ TIMING
COMPETITOR
MULTIPLEXED
BUS
‘LE(AddressLatch
~
(Read Output Enable)
(DS Pin)
I
IL
C= (Chip Select)
STBY
ADO-AD7
(Address/ Data Bus)
FIGURE 4 – BUS WRITE TIMINti?@PETITOR
*W
@-
ADO-AD7
VHIGH=VDD-2.O
V, VLOW=O.8
V, VLOW=O.5
V, for VDD=5.O
V, for VDD=3.O
31
Write
Valid
V A 10% for outputs
V for outputs
MOTOROLA
@
.
Address
<;
VHIGH=2.O
25
BUS
@
J
(Address/ Data Bus)
Note:
MULTIPLEXED
Data
Valld
only.
only.
‘Semiconductor
5
Products Inc.
A
TABLE 1 – SWITCHING
CHARACTERISTICS
(VSS=O
Vdc, TA= TL to TH)
-.
VDD=3.O
Description
I
I Symbol I
I Oscillator Startu~
ltRrl–
1Reset Pulse Width
I tRWL
tRLH
I +-, .,,
Reset Delay Time
D, ,1-DA,.,-. C----
!AI; A+L
Min
[
TBD
I
TBD
TDn
I
Max
Vdc
I
lTBDlms]–
—
I
I
I
–
I
I
VDD = 5.0 Vdc & 10”A
Unit
I
Min
I
Max
I
Unit
ll~lmsl
KS
ps
..-
I
51–
I
51–
C
I
I
ps
I
&s
‘i\!
I
DS
RESET
.—
ITQ
VDD
2k
(KQ OnIV)
L
MM D7000
or Equivalent
.
T
.
All Outputs Except OSC2 (See Figure 10)
m
MOTOROLA
Semiconductor
6
—
130pF
Products Inc.
.—
FIGURE 7 – POWER-UP
VDD Pin
~~
Ov
RESET Pin
CKOUT Pin
VDD Pin
Ov
PS Pin .
~
The VRT bit is set to a ,1’, by reading Register d. The VRT bit mn only be cleared by pulling the PS pin low (see REGISTER D ($OD)).
MOTOROLA
@
Semiconductor
7
Products Inc.
SIGNAL DESCRIPTIONS
ADO-AD7 – MULTIPLEXED
ADDRESSIDATA
BUS
The block diagram in Figure 1, shows the pin connection
with the major internal functions of the MC146818A RealTime Clock plus RAM. The following paragraphs describe
the function of each pin.
Multiplexed bus processors save pins by presenting the
address during the first portion of the bus cycle and using
the same pins during the second portion for data. Addressthen-data multiplexing does not slow the access time of the
MC146818A since the bus reversal from address to data is
\\;~,;.
occurring during the internal RAM access time.
.
>.t,,
.... ,..,$)
The address must be valid just prior to the fall ,@#~$~~LE
at which time the M C146818A latches the addr.e~ ??@ ADO
to AD5, Valid write data must be presente@t~~~~fi8?d stable
during the latter portion of the DS or ~~~~?~~.
In a read
cycle, the M C146818A outputs eight ~[~bf~~ta
during the
latter portion of the DS or ~ pulse~$~$~mases
driving the
bus (returns the output drivers to t~,h,$h-impedance
state)
when DS falls in the Motorola&cJ&e o~~OTEL or R~ rises in
the other case.
VDD, VSS
DC power is provided to the part on these two pins, VDD
being the more positive voltage. The minimum and maximum voltages are listed in the Electrical Characteristics
tables.
MOT–MOTEL
The MOT pin offers flexibility when choosing bus type,
When tied to VDD, Motorola timing is used. When tied to
VSS, competitor timing is used. The MOT pin must be hardwired to the VDD or VSS supply and cannot be switched
during operation of the MC146818A.
..,~t;~,
.?)?
AS – MULTIPLEX~:~@#~SS
STROBE, INPUT
+,tp:=,y,t\>
A positive goin~+ mu~~[pjexed address strobe pulse serves
to demultiplex t~~x,~~s. The falling edge of AS or ALE causes
the address+~:$~~atched within the MC146818A.
OSC1, OSC2 – TIME BASE, INPUTS
The time base for the time functions may be an external
signal or the crystal oscillator. External square waves at
4.184304 MHz, 1.M576
MHz, or 32.768 kHz may be connected to OSCI as shown in Figure 9. The internal time-base
frequency to be used is chosen in Register A.
The on-chip oscillator is designed for a parallel resonant
AT cut crystal at4.1 M04 MHz, 1.048576 MHz or32.768 kHz
frequencies. The crystal connections are shown in Figure 10
and the crystal characteristics in Figure 11.
CKOUT – CLOCK OUT, OUTPUT
The CKOUT pin is an output at the time-base freque~~
divided by 1 or 4. A major use for CKOUT is as the t~u~:t,
clock to the microprocessor; thereby saving the c,@$:&::@
second crystal. The frequency of CKOUT depends%~okt$he
..j:.+.k’~
CKFS – CLOCK OUT FREQUENCY #%&<$:
INPUT
\
DS ~ #&$A’”sTROBE
4.ly3~,,Myz
,.,..r“
M HZ
High
~$+&6
‘:\:~576
MHZ
M HZ
R/~
‘32.768 kHz
32.7&
kHz
Low
1.W576
MHz
1.W576
MHz
Low
262.144 kHz
High
32.768 kHz
Low
8.192 kHz
M070ROLA
INPUT
~S – CHIP SELECT, INPUT
The chip-select (C~) signal must be asserted (low) for a
bus cycle in which the MC146818A is to be accessed. C= is
not latched and must be stable during DS and AS (Motorola
case of MOTEL) and during ~D and ~R. Bus cycles which
take place without asserting C= cause no actions to take
place within the MC146818A. When C% is not used, it should
be grounded. (See Figure 20).
SQW – SQUARE WAVE, OUTPUT
The SQW Din can output a signal from one of the 15 taps
provided by ihe 22 internal-divid~r stages. The frequency of
the SQW may be altered by programming Register A, as
shown in Table 5. The SQW signal may be turned on and off
using the SQWE bit in Register B.
@
– READ/WRITE,
The MOTEL circuit treats the R/~ pin in one of two ways.
When a Motorola type processor is connected, R/~ is a
level which indicates whether the current cycle is a read or
write. A read cycle is indicated with a high level on R/~
while DS is high, whereas a write cycle is a Iowon R/~ during DS.
The second interpretation of R/~ is as a negative write
pulse, ~R, MEMW, and l/OW from competitor tv~e ~rocessors, The MOTEL circuit in t~s mode gives R/~’pin” the
same meaning as the write (W) pulse on many generic
RAMs.
Clock Frequency
Output Hn
(CKOUT)
4.1943W MHz
High
OR READ, INPUT
~~,DS pin has two interpretations via the MOTEL circuit,
,:&$$n@manating
from a Motorola type processor, DS is a
.,,,%~o$$lve pulse during the latter portion of the bus cycle, and
called DS (data strobe), E (enable), and 42 (42
!,,., *~~&$ariously
..-,:::.J+>,<T,
,.
*a:J clock). During read cycles, DS signifies the time that the
~\33, ‘ RTC is to drive the bidirectional bus. In write cycles, the trailing edge of DS causes the Real-Time Clock plus RAM to
latch the written data,
The second MOTEL interpretation of DS is that of ~,
MEM R, or ~
emanating from the competitor type processor. In this case, DS identifies the time period when the
real-time clock plus RAM drives the bus with read data. This
interpretation of DS is also the same as an output-enable
signal on a typical memory.
,,: .,,,
4.W:
.,
,!:!~ ‘,$$v<,,:hi:.
When the CKFS pin is tied to VD~$~$:jcai~es CKOUT to be
the same frequency as the time b~e ~~fie OSCI pin. When
CKFS is tied to Vss, CKOUJ:~~l~@~OSCl time-base frequency divided by four. T~le~~
summarizes the effect
~me Base,,~~~~=~k Frequency
(oscl~, ;$t~,;
‘+ Select Hn
Freq~ ~,,,,, ‘“
(CKFS)
BIDIRECTIONAL
Semiconductor
8
Products Inc.
—
FIGURE 9 – EXTERNAL TIME-BASE
CONNECTION
VDD
$
Optional
(VDD–1.O
4.1%304 MHz
or
1.W576 MHz
32.7:;
I
I
VI
2
Oscl
3
kHz
(Open)<—
OSC2
L
MC146818A
,..
,!~.-
OSC2
MC146818A
fow
RS (Maximum)
CO (Maximum)
MHz
1.046576 MHz
75 Q
700 n
7 pF
5 pF
32.7@ kHz
Wk
1.7 pF
cl
0.012 pF
Q
50 k
35 k
30 k
R
15-30 pF
—
15-40 pF
—
300-470 k
Rf
10 M
10 M
22 M
Cin/Cout
MOTOROLA
@
4.1-
0.~8
pF
Semiconductor
9
0.~3
pF
10-22 pF
Products Inc.
~Q–
FIGURE 12–TYPICAL
POWERUP DELAY
CIRCUIT FOR RESET
INTERRUPT REQUEST, OUTPUT
The IRQ pin is an active low output of the MC14W18A
that
may be used as an interrupt
input to a processor,
The ~Q
output remains low as long as the status bit causing the in-
When no interrupt
in the high-impedance
D2
DI
terrupt is present and the corresponding
interrupt-enable
bit
is set. To clear the 1~ pin, the processor program normally
reads Register C. The RESET pin also clears pending interrupts.
conditions
are present, the ~Q level is
state. Multiple
interrupting
devices
may thus be connected
processor.
to an ~Q
bus with
one pullup
at the
RESET – RESET, INPUT
The RESET pin does not affect the clock, calendar,
or
RAM functions.
On powerup,
the RESET pin must be held
low for the specified time, tRLH, in order to allow the power
supply
to stabilize.
Figure
12 shows
a typical
representation
of the RESET pin circuit.
When RESET is low the following
occurs:
a) Periodic Interrupt Enable (PIE) bit is cleared
to
zero,
b) Alarm
c) Alarm
Interrupt
Interrupt
Enable
Enable
(AIE)
(AIE)
bit is cleared
bit is cleared
to zero,
to zero,
d) Update ended Interrupt
Flag (UF) bit is cleared to zero,
e) Interrupt
Request status Flag (IRQF) bit is cleared to
zero,
f) Periodic
Interrupt
Flag ( PF) bit is cleared
to zero,
g) The part is not accessible.
h) Alarm Interrupt
Flag (AF) bit is cleared to zero,
i) IRQ pin is in high-impedance
state, and
j)
Square
zero,
Wave
output
Enable
(SQWE)
..
Not~~${,the
,~J,,,t dwe
~y 1~~
bit is cleared
JQ
...
BY
The STBY
pin,
MC146818A
making
when
active,
prevents
ac~s~$~
it ideal for battery back-~’~~~l~ations.
Stand-by
incorporates
operation
data strobe
(DS) goes low
recognized
as a valid signal.
The STBY signal is totally
latch is opened by the falling
a transpa~~$$~~$tch,
RTC is isolated from the MPU or M CU power by a
drop, care must be taken to meet Vin requirements.
,,f:~
‘ ~l~\
tFi’>\t:;*g*\\$
.,. ‘~’+!
,,,:*.LF,
,, .,,,.$
STBY – STAND–
.,~!,:~,,+
FIGURE 13 – TYPICAL POWERUP DELAY CIRCUIT
FOR POWER SENSE
“the
DI
D2
After
(TD
or .:>.$,:<
_j:rn@),
STBY is
J*! N
$$3,
asyR*L@6s.
Its transpare~t
e~~~.of
.@S (rising edge of RD
~.$,*,%
2’$\$-
I
VDD
or ~R) and clocked by the r$@n@~dge of AS (ALE). Therefore, for STBY to be reco$oize@t@S
and AS should occur in
pairs.
When
STBY
gop@~l,W,,before
the falling
Ps
edge of DS
(rising edge of ~R ?r ~~k$~re current cycle is completed
that edge and thq \ $h<,~ycle
will not be executsd.
~..
.!,...
at
MC146818
S*, \“~*~>
PS – POW,~”:J~~$E,
+
INPUT
Vss
The pQ,v&-s~$se
pin is used in the control
of the valid
RAM @~~~$
(VRT) bit in Register D. When the PS pin is
low ~@q,w~~T bit is cleared to zero.
W~@’Using
the VRT feature during powerup,
the PS pin
must % externally
held low for the specified tpLH time. As
power is applied, the VRT bit remains low indicating
that the
MOTOROLA
0.005 ~F
I
T
DI = M BD701 (Schottky) or Equivalent
D2 = 1N4148 or Equivalent
contents
of the RAM, time registers,
and calendar are not
guaranteed.
PS must go high after powerup
to allow the
VRT bit to be set by a read of register D,
m
2.0 k
Semiconductor
10
Products Inc.
POWER-DOWN
CONSIDERATIONS
In most systems, the MC146818A
must continue
to keep
time when system power is removed.
In such systems,
a
conversion
from system power to an alternate power supply,
Register
updates
Before
usually a battery, must be made. During the transition
from
system to battery power, the designer of a battery backed-up
RTC system must protect
data integrity,
minimize
power
tions in the selected format (binary or BCD), then indicates
the format
in the data mode (DM) bit of Register
B. All
10 time, calendar, and alarm bytes must use the same data
consumption,
and ensure hardware
reliability.
The stand-by
(STBY)
pin controls
all bus inputs (R/~,
DS, AS, ADO-AD7)
ST BY, when negated,
disallows
any
unintended
modification
also reduces
power
of the RTC data by the bus.
consumption
by reducing
transitions
seen internally.
Power consumption
may be further
resistive
and capacitive
loads
pin and the squarewave
During and after the
maximum
specification
from
(SQW) pin.
power source
must
never
of
be exceeded.
Table 3 shows
(CKOUT)
the VIN
Failure
to
Figure
14 shows
the address
The
and 1.O@fiMMz
time Qas&fl~he
data, and four control
and status bytes, All 64 bytes
directly readable and writable
by the processor program
mo,&e
the update
,,$~t~~e%~hree alarm
are
ex-
cept for the following:
1) Registers C and D are read only,
2) bit 7 of Register A is read only, and 3) the high-order
bit of
the seconds
and status
byte is read only. The contents
of four control
registers
(A, B, C, and D) are described
in
.Fi.’.’
,~..
,.,.,
REGISTERS.
~’ ~:,
.:$..,
‘%<. ‘,+
....’t)\..).$<l>\b
TIME, CALENDAR,
AND ALARM
LOCATIONS
>..!l’;:!,,t,
.,.....
these
and
RAM
alarm
decimal
locations.
bytes
The contents
may
be
either
care”
care”
state
code
tion.
of th.$,~@&~”~, calendar,
‘~
bi.~r~.,~~
binarv-coded
When
th+ l~~~~r
format
time bases and 1948 ps for the 32.768 kHz
Update Cycle section shows how to accomcycle
bytes
in the processor program.
may be used in two ways.
First,
in one or more of three alarm bytes. The “don’t
is any hexadecimal
byte from CO to FF. That is,
Similarly,
an alarm
is generated
every
minute
with
“don’t
care” codes in the hours and minutes alarm bytes.
The “don’t
care” codes in all three alarm bytes create an interrupt every second.
00
MAP
01
1
I
Seconds
Seconds
100)
Alarm
01
I
OD
Binary
or BCC
Contents
50
1
4
I
I
User
RAM
\
10
I
Register
A
I OA
63
(M) MOTOROLA
is selected
Once per second the
logic to be advanced by
—
Bvtes
10 time,
the two most-significant
bits of each byte, when set to “l”,
create a “don’t care” situation.
An alarm interrupt each hour
is created with a “don’t
care” code in the hours alarm loca-
time and calw~~~r ~tiYorlocations.
~~f~~gram
>.’*. J.
and ala~,$~p$i~rltlng
to
FIGURE 14 – ADDRESS
13
in
,%,~p~$ the Program inserts an alarm time in the appropriate
,~$~$~pbrs, minutes,
and seconds alarm locations,
the alarm in“:,$~”fbrrupt is initiated at the specified time each day if the alarm
enable bit is high. The second usage is to insert a “don’t
*J~”
(BCD).
o
bit
bit of the hoursh~&
represents PM when it is
‘J~...l,>.<.,
.:i\\y+.
:\\
.;. ..<,),
.,+*,.
calendar,
~@ ~~~rm bytes are not always
memory consists of 50 general purpose RAM bytes, 10 RAM
bytes which normally contain the time, calendar, and alarm
The processor
program
obtains
mation by reading the appropriate
may initialize
the time, calendar,
SET
one second and te<~ec~for
an alarm condition.
If any of the
10 bytes are,~&#@$?This
time, the data outputs
are undefined. The u~~a~ ~~ckout time is 248ys at the 4.19W04 MHz
MAP
map of the MC146818A,
the
and BCD form~&Q{t~e
accessible
by the proce~?i:,@;ogram.
,.::,,\., ....,
10 bytes are switched ~,~b
update
of the part.
ADDRESS
the binary
locations.
the high-order
a “l”.
The time,
meet the VIN maximum
specification
can cause a virtual
SCR to appear which may result in excessive current drain
and destruction
registers,
either binary or BCD. The SET bit may now be c~red
ing the hour
conversion,
internal
calendar,
and alarm locations.
The 24/:~9 ‘~~~,1~ Register B
establishes
whether
the hour locatio+n$f#p[&sent
l-to-12
or
O-to-23. The 24/12 bit cannot be c~;fi~&~”r%ithout
reinitializ-
by removing
out
the
to allow updates.
Once initialized
the real-time clocR’Mkes
all updates in the selected data mode. The data ~~~a,~%nnot
be changed without
reinitializing
the 10 data ,&~<~~~$t*
STBY
the number
reduced
the clock
mode,
initializing
B should be set to a “1” to prevent time/calendar
from occurring.
The program initializes the 10 loca-
Semiconductor
11
Products Inc.
TABLE 3 – TIME, CALENDAR,
AND
ALARM
DATA
MODES
.Address
Function
Location
Decimal
Example’
Range
BCD
Range
Binary Data Mode
BCD Data Mode
Bina~
Data Mode
Data Mode
21
o
Seconds
o-59
$W-S3B
$W-$59
15
1
Seconds Alarm
o-59
$00-$3B
$W-$59
15
21
2
Minutes
o-59
$W-$3B
$W-$59
3A
56
3
Minutes Alarm
o-59
$W-$3B
$m-$59
3A
56
Hours
(12 Hour Mode)
1-12
$01-$OC (AM) and
$81-$8C ( PM)
$01-$12 (AM) and
05
05
4
Hours
(24 Hour Mode)
Hours Alarm
(12 Hour Mode)
5
Hours Alarm
(24 Hour Mode)
Dav of the Week
6
7
8
9
.,~,1,,
IS,.
“.y,t,,,8t:i.,..
‘~,z
~,~m,.,
.),,.:
,,, ~
~.,..V
%$ ,?@:$,
. ..
,>.,
!’
,,,:s
~
O-23
$CO-$17
1-12
$01-$OC (AM) and
$81-$8C (PM)
O-23
$W-$17
1-7
$01-$07
1-31
1-12
$01-$1F
Month
Year
o-99
$00-$63
Sunday= 1
Date of the Month
$81-$92 (PM)
.!,.
A),,),,
l.~:~
:.*L~\,\.
t,.,
~ ,,.l.,.,$..
,1.
.,
~
*:~\
,:::’~”
,<$,+
$01-$oc
05
$W-$23
$01-$12 (AMI and
$81-$92 (PM)
,:ft<+;:t’~
05
,.\\. !:
%,...
05 ~$+j >,, “05
$~-23
,. $~?..
‘<i,)
!t. t$:i;~:;,,
$01-$07
<f@ ~\..+:t
‘
.,jh ,.*,
.,
$01-$31
$:&*$@’$’
$01-$12,<P,$ ‘t 02
$m-$~+:$~Q’ ‘
)$; ‘J* ‘*’
4F
05
15
02
79
“ Y*<
STATIC CMOS RAM
The % general purpose RAM bytes are not dedicated
within the MC140818A. They can be used by the processor
program, and are fully available during the update cycle.
When time and calendar information must use battery
back-up, very frequently there is other non-volatile data that
must be retained when main power is removed. The W u~~,,:
RAM bytes serve the need for low-power CMOS bat~y-’<~
backed storage, and extend the RAM available $&&@
M C148818AS may be included
in th~$~~~~~.
The
time/calendar
functions may be disabl~~ ~:’b~lding
the
DvO-DV2 dividers, in Register A, in th~~~es$.~hte by settin9
the SET bit in Register B or by re~ovag
the oscillator.
Holding the dividers in reset preve.~&~~&#~upts or SQW output from operating while set~&~}~&rS ET bit allows these
functions to occur. With the &~id~s clear, the available user
RAM is extended to 59+b~teS~he
high-order bit of the
seconds byte, bit 7 of @~~fS~~ A, and all bits of Registers C
and D cannot effecl~~~~ be’ used as general purpose RAM.
e. ~..h.,
t.$.:.
.!,;it,
,,, ;&:~JN~ERRUPTS
The RTC @wsJ%,@’~includes three separate fully automatic
sources of {~te~pts
to the processor. The alarm interrupt
may be@r~r%ti”med to occur at rates from once-per-second
to q~~~@aY The periodic interrupt may be selected for
rate~;<(~~” half-a-second to 30.517 ps. The update-ended interru@f may be used to indicate to the program that an update cycle is completed. Each of these independent interrupt
conditions are described in greater detail in other sections.
The processor program selects which interrupts, if any, it
wishes to receive. Three bits in Register B enable the three
interrupts.
Writing
that interrupt
a “1”
to a interrupt-enable
bit permits
to be initiated when the event occurs. A “U’ in
the interrupt-enable
bit prohibits the IRQ pin from being
asserted due to the interrupt cause.
MOTOROLA
@
If ~~’ intertupt flag is already set when the interrupt
be&%:j.enabled,
the ~
pin is immediately activated,
,,tq~u”$ the interrupt initiating the event may have occurred
.<,x,,~w{ earlier. Thus, there are cases where the program
a,f~~uld clear such earlier initiated interrupts before first
,i~y “bnabling new interrupts.
When an interrupt event occurs, a flag bit is set to a “l” in
Register C. Each of the three interrupt sources have separate
flag bits in Register C, which are set independent of the state
of the corresponding enable bits in Register B. The flag bit
may be used with or without enabling the corresponding
enable bits.
In the software scanned case, the program does not
enable the interrupt. The “interrupt”
flag bit becomes a
status bit, which the software interrogates, when it wishes.
When the software detects that the flag is set, it is an indication to software that the “interrupt’’event
occurred since the
bit was last read.
However, there is one precaution.
The flag bits in
Register C are cleared (record of the interrupt event is erased) when Register C is read. Double latching is included with
Register C so the bits which are set are stable throughout the
read cycle. All bits which are high when read by the program
are cleared, and new interrupts (on any bits) are held after
the read cycle. One, two or three flag bits may be found to
be set when Register C is used. The program should inspect
ail utilized flag bits every time Register C is read to insure that
no interrupts are lost.
The second flag bit usage method is with fully enabled interrupts. When an interrupt-flag bit is set and the corresponding interrupt-enable
bit is also set, the ~Q pin is
asserted low. ~Q is asserted as long as at least one of the
three interrupt sources has its flag and enables bits both set.
The IRQF bit in Register C is a “l” whenever the ~Q pin is
being driven low.
The processor program can determine that the RTC initiated the interrupt by reading Register C. A “l” in bit 7
Semiconductor
12
Products Inc.
...
.
operating time base, the first update cycle is one-half second
later. The divider-control
bits are also used to facilitate
testing the MC146818A.
(IRQF bit) indicates that one or more interrupts have been initiated by the part. The act of reading Register C clears all the
then-active flag bits, plus the IRQF bit. When the program
finds IRQF set, it should look at each of the individual flag
bits in the same byte which have the corresponding
interrupt-mask bits set and service each interrupt which is
set. Again, more than one interrupt-flag bit may be set.
DIVIDER
SQUARE-WAVE
STAGES
The MC146818A has 22 binary-divider stages following the
time base as shown in Figure 1. The output of the dividers is
a 1 Hz signal to the update-cycle logic. The divers are
controlled by three divider bus (DV2, DVI, and DVO) in
Register A.
DIVIDER CONTROL
The divider-control
bits have three uses, as shown in
Table 4. Three usable operating time bases may be selected
(4.184304 MHz, 1.048576 MHz, or 32.768 kHz). The divider
chain may be held at reset, which allows precision setting of
!,
TABLE
5 –
,\”.
PE~~Q&~,)~TERRUPT
$s<., l’:
,,r.\\e:
,$h,y,:~~...-
RATE AND
4.1=
,,8s3
,.,. \*...
,> ~j$
“*% 2
:
A
RS1
RSO
;
;
<..:.,
..JX:{$:,
*
.Ji+t,.,,>
.-.~,s;.:, !,.:.
,,.,.
:.’”*
‘ ..~.\\\,
WAVE
OUTPUT
Periodic
Interrupt Rate
tpl
FREQUENCY
32.768
MHz
kHz
Time
Base
Base
Periodic
outputInterrupt Rate
SQW
3;;,s
3.90625
kHz
Output
Frequency
None
None
32.768
SQW
tpl
Frequency
“‘J:{.*..,
:\:\,.
!\)>
,:ti ~‘$8, ~
SQUARE
or 1.046676
Tme
,$~$~~~jits
$~ #~iater
OUTPUT SELECTION
Fifteen of the 22 divider taps are made available to a
1-of-1 5 selector as shown in Figure 1. The first purpose of
selecting a divider tap is to generate a square-wave output
signal at the SQW pin. The RSO-RS3 bits in Register A
establish the square-wave frequency as listed in Table 5. The
SQW frequency selection shares the 1-of-15 selector,$~ith
,~)
:/,
~~.
~...
.,.......
periodic interrupts.
‘~
~,?.
,,,,,,
,:?,,,
Once the frequency is selected, the output of th:~~~~
pin
may be turned on and off under program coq:g~{,~tih the
square-wave output selection bits, or the&~,~~~outputenable bit may generate an asymmetric
m~~form at the
time of execution. The square-wave out~@~J~has a number
,../&
> “i,;...<**
of potential uses. For example, it ~~ ~+m as a frequency
standard for external use, a freqyen~$~?nthesizer,
or could
be used to generate one or m%,&~,dlo tones under Pro9ram
None
ms
256
HZ
7.8125 ms
128 HZ
8.192 kHz
122.070 ~S
8.192 kHz
4.096 kHz
244.141 flS
4.@6 kHz
2.048 kHz
W.281
PS
2.048 kHz
0
PS
976.562 US
1.024 kHz
976.562 BS
1.024 kHz
1
1
1.953125 ms
512 HZ
0
0
1
1
0
0
0
1
0
1
3.90625 ms I
256 Hz
3.90625 ms
256 HZ
7.8125 m1s I
15.625 m1s
128 HZ
7,8125 ms
128 HZ
15.625 ms
64 Hz
1
1
0
0
0
0
1
1
1
1
1
1
o
o
0
0
1
1
0
1
61.035 PS
16.384 kHz
122.070 ~S
o
1
0
0
244.141 #S
o
1
0
1
=.281
\, ,\... .....
o
1
1
..$>,..
.
0
1
1
1
1
1
L&’’”
R4
H7
512 HZ
I 1.953125 ms
I
31,25 ms
32 HZ
31.25 ms
32 HZ
0
1
62.5 ms
16 HZ
62.5 ms
16 HZ
125 ms
8 Hz
125 ms
8 HZ
1
0
250 ms
4 Hz
250 ms
4 Hz
1
1
500 ms
MOTOROLA
2 Hz
1
t
500 ms
Semiconductor
13
1
2 Hz
I
Products Inc.
complete, the output will be undefined. The update in progress (UIP) status bit is set during the interval.
PERIODIC INTERRUPT SELECTION
The periodic interrupt allows the ~
pin to be triggered
from once every 5W ms to once every 30.517 ps. The
periodic interrupt is separate from the alarm interrupt which
may be output from once per second to once per day.
Table 5 shows that the periodic interrupt rate is selected
with the same Register A bits which select the square-wave
frequency. Changing one also changes the other. But each
function may be separately enabled so that a program could
switch between the two features or use both. The SQW pin
is enabled by the SQWE bit in Register B. Similarly the
periodic interrupt is enabled by the PIE bit in Register B.
Periodic interrupt is usable by practically all real-time
systems. It can be used to scan for all forms of inputs from
contact closures to serial recieve bits or bytes. It can be used
in multiplexing
displays or with software counters to
measure inputs, create output intervals, or await the next
needed software function.
A program which randomly accesses the time and date information finds data unavailable statistically once every 4032
attempts. Three methods of accommodating nonavailability
during update are usable by the program. In discussing the
three methods, it is assumed that at random points user programs are able to call a subroutine to obtain the time o$$gay.
The first method of avoiding the update cycle, ~~,~$%e
update-ended interrupt. If enabled, an interrupt @~@kS*after
every update cycle which indicates that oveb;~w,;.&s are
available to read valid time and date inforrn~~&$’’Buring
this
time a display could be updated or the i~fqw$$bn could be
transferred to continuously availablq,t.&~~$,*Before leaving
the interrupt service routine, the ~~~~$ bit in Register C
,4
.$,.? “~,>$;:
\..
should be cleared.
The second method uses t$~wate-in-progress
bit (U IP)
in Register A to determin~;ti~~~%~update cycle is in progress
or not. The UI P bit will ,~j%,,$hce per second. Statistically,
the UIP bit will indiq$~;~~~t time and date information is
‘$+
unavailable once ~,~ery‘~~~ attempts. After the UIP bit goes
high, the updat~$’~~~,begins 244 ps later. Therefore, if a low
is read on th~~l~$it,
the user has at least 2~ ws before the
time/cale@&
d~ta will be changed. If a “l” is read in the
UIP bit, {~~@$fie/calendar data may not be valid. The user
shou~,d avb$~ interrupt service routines that would cause the
ti~)~tieded
to read valid time/calendar
data to exceed
,p%;>
UPDATE CYCLE
The MC14~18A
executes an update cycle once per
second, assuming one of the proper time bases is in place,
the DVO-DV2 divider is not clear, and the SET bit in Register
B is clear. The SET bit in the “l” state permits the program
to initialize the time and calendar bytes by stopping an existing update and preventing a new one from occurring.
The primary function of the update cycle is to increment
the seconds byte, check for overflow, increment the minutes
byte when appropriate and so forth through to the year of
<<,j~%$~#e third method uses a periodic interrupt to determine if
the century byte. The update cycle also compares each
%$s-J%update cycle is in progress. The UIP bit in Register A is set
alarm byte with the corresponding time byte and issues an
“’”$high between the setting of the PF bit in Register C (see
alarm if a match or if a “don’t care” code (1IXXXXXX) is
,..:,
‘,.
.!
Figure 15), Periodic interrupts that occur at a rate of greater
present in all three positions.
~:)::.
than tBUC+tUC allow valid time and date information to be
With a 4.19~
MHz or 1.048576 MHz time base thq$~~~+~$
read at each occurrence of the periodic interrupt. The reads
date cycle takes 248 ps while a 32.708 kHz time base~
~~~,&*&
should be completed within (Tpl + 2) + tBUC to ensure that
cycle takes 1984 ps. During the update cycle, the t~~~’~endata is not read during the update cycle.
dar, and alarm bytes are not accessible by the p~$~s~~ proTo properly setup the internal counters for daylight savings time operation, the user must set the time at least two
seconds before the rollover will occur. Likewise, the time
must be set at least two seconds before the end of the 29th
or 30th day of the month.
gram. The MCI%818A protects the progra~>~~% reading
transitional data. This protection is provid~>~~switch
ing
the time, calendar, and alarm portion,~~*~~# RAM off the
microprocessor bus during the entir~ up~ate cycle. If the
processor reads these RAM loca,@%&W~ore
the update is
(,.:,
tpl = Periodic Interrupt Time Interval (500 ms, 250 ms, 125 ms, 62,5 ms, etc. per Table 5)
tuc = Update Cycle Time (2W ps or lW ps)
tBUC = Delay Time Before Update Cycle (2M KS)
m
MOTOROLA
Semiconductor
14
Products Inc.
progress is aborted and the program may initialize the time
and calendar bytes without an update occurring in the midst
of initializing. SET is a read/write bit which is not modified
by RESET or internal functions of the MC146818A.
REGISTERS
The M C146818A has four registers which are accessible to
the processor program. The four registers arealsofullyaccessible during the update cycle.
PIE – The periodic interrupt enable (PIE) bit is a
read/write bit which allows the periodic-interrupt
flag (PF)
bit in Register C to cause the l~pin
to be driven low. A program writes a “1” to the PIE bit in order to receive periodic
interrupts at the rate specified by the RS3, RS2, RSI, and
RSO bits in Register A, A zero in PIE blocks l~Q from being
initiated by a periodic interrupt, but the periodic flag (P~) bit
is still set at the periodic rate. PIE is not modified b~,a~&$~o-
REGISTER A ($OA)
MSB
LS B
b7
b6
UIP
b5
DV2
DV1
b4
b3
DVO
RS3
b2
bl
RS2
Read/ Write
Register
bO
RS1
RSO
except UIP
UIP – The update in progress (UIP) bit is a status flag that
may be monitored by the program. When UIP is a “l”, the
update cycle is in progress or will soon begin. When UIP is a
“U’, the update cycle is not in progress and will not be for at
least 244 ps (for all time bases). This is detailed in Table 6.
The time, calendar, and alarm information in RAM is fully
available to the program when the UIP bit is zero – it is not
in transition. The UIP bit is a read-only bit, and is not affected by Reset. Writing the SET bit in Register B to a “l”
inhibits any update cycle and then clears the UIP status bit.
AIE – The alarm interrupt enable (Al E) ~T$f&j&i$&ad/write
bit which when set to a “1” permits the @~rfl~~& (AF) bit in
Register C to assert IRQ. An alarm inte~~@’\$occurs for each
second that the three time bytes e~~~~~~&i?hree alarm bytes
(including a “don’t care” alarm &od&tQ~ binary 1IXXXXX).
When the AIE bit is a “U’, the ~~~jt does not initiate an ~Q
signal. The RESET pin cle~f~~s~~% “V’. The internal functions do not affect the ,~~,t~t~
TABLE 6 – UPDATE CYCLE TIMES
Time Base
Update Cycle ~me
(Oscl)
(tuc)
Minimum Time
Before Update
UIE – The UIE (q~~~~~%%ded interrupt enable) bit is a
read/write bit which e’, ~7~s the updat%end flag (U F) bit in
Register C to a@~,,lf %
The RESET pin going low or the
—
4.lWW
MHz
Z@ ps
1
SET bit goin~~~~~c~ears the UIE bit.
—
1
1.046576 MHz
Z& fls
.4, :$, .
—
1
32.766 kHz
lw~s
SQW~;~~&&n
the square-wave enable (SQWE) bit is set
—
to a “l’’k~~ the program, a square-wave signal at the freo
4.194304 MHz
244 fis
—
qu~~y spefified in the rate selection bits (RS3 to RSO) apo
1.M576 MHz
244 ps
W$S @ the SQW pin. When the SQWE bit is set to a zero
—
244
fis
o
32.766 kHz
,,,,,~@e~QW pin is held low. The state of SQWE is cleared by
,,~,;~~~~”k ESET pin. SQWE is a read/write bit.
DV2, DVI, DVO – Three bits are used to permit the Dro*$:=:,.,:.
+:,8 DM – The data mode (DM ) bit indicates whether time
gram to select various conditions of the 22-stage divider
.1,
..,}
and calendar updates are to use binary or BCD formats. The
?’
chain. The divider selection bits identify which of the thre:~
DM bit is written by the processor program and maybe read
time-base frequencies is in use. Table 4 shows that tJ,ti’&j2,
by
the program, but is not modified by any internal functions
bases of 4.194304 MHz, 1.046576 MHz, and 32.7~ k~~)~~, ‘“
or RESET. A “l” in DM signifies binary data, while a “U’ in
be used. The divider selection bits are also used to$,~j&~,J~&
DM specifies binary-coded-decimal
(BCD) data.
divider chain. When the time/calendar is first ini~~t~~:~~the
program may start the divider at the precise,~~$~&red
in
24/12 – The 24/12 control bit establishes the format of
the RAM, When the divider reset is removed;~~~:~wt update
the hours bytes as either the 24hour mode (a “l”) or the
cycle begins one-half second later. Thes%.th~e read/write
12-hour mode (a “U’), This is a read/write bit, which is afbits are not affected by RESET.
fected on Iy by software.
..~d’”: >~UIP Bit
Cycle (tBuC)
;.i
..:.,\~,
*.,.>*,,,
~,{.,!$.~..$..
DSE – The daylight savings enable (DSE) bit is a
readlwrite
bit which allows the program to enable two
special updates (when DSE is a “1”). On the last Sunday in
April the time increments from 1:59:59 AM to 3:00:00 AM.
On the last Sunday in October when the time first reaches
1:59:59 AM it changes to 1:00:00 AM. These special updates
do not occur when the DSE bit is a ‘JO’. DSE is not changed
by any internal operations or reset.
RS3, RS2, RS1, RSO – The fo$~ ray selection bits select
one of 15 tapes on the 22-sta~.~W~~&@P,or disable the divider
output. The tap selected may ~.~hed to generate an output
square wave (SQW pin) ~i~or &periodic interrupt. The program may do one of ~~~~wing:
1) enable the interrupt
with. the PIE bit, ~~~~~le
the SQW output pin with the
SQWE bit, 3) en@’~th
at the same time at the same rate,
or 4) enable n,g~w~~~”able 5 lists the periodic interrupt rates
and the sqq~re-.g%ve frequencies that may be chosen with
the RS ~j~%h@e four bits are readlwrite bits which are not
affecte,~Q~’%ES ET.
~,.,1,
$,,,,.)e~,{.,
REGl~Ei
B ($OB)
MSB
LSB
b71b61b51b41
SET
I
b31b21bl
bO
REGISTER C ($OC)
b7/b61b51b4
IRQFIPFIAFIUFIOIO
Read/ Write
Register
@
MOTOROLA
b3
b
bl
I
bO
Read-Only
Register
jOIO
IRQF – The interrupt request flag (IRQF) is set to a “l”
when one or more of the following are true:
PF=PIE=”I”
AF=AIE=”I”
UF=UIE=”I”
i.e., IRQF= PF*PIE+ AF*AIE+UF*UIE
PIE I AIE ] UIEI SQWEI DM ] 24/12 I DSE
SET – When the SET bit is a “O’, the update cycle functions normally by advancing the counts once-per-second.
When the SET bit is written to a “1”, any update cycle in
1—
LSB
MSB
Semiconductor
15
Products Inc.
Any time the IRQF bit is a “l”,
All flag
gram
bits are cleared
or when
after
the 1~
Register
pin is driven
b6 TO bO – The remaining
bits of Register D are unused.
They cannot be written,
but are always read as “OS. ”
low.
C is read by the pro-
the RESET pin is low.
TYPICAL
PF – The periodic
interrupt
flag (PF) is a read-only
bit
which is set to a “l”
when a particular
edge is detected on
the selected tap of the divider chain. The RS3 to RSO bits
establish the periodic rate. PF is set to a “l”
independent
of
the state of the PIE bit. PF being a “l”
initiates
an ~
The
signal
–
A “l”
in the AF (alarm
interrupt
flag)
by a Register
They
REGISTER
bits of Status
Register
that
These
can
the
However,
if
address
standard
*S ~pcessors.
The inter~ign’&#’to
multiplex
the ad-
or MC6809
~~a&$r,~essor
M CWOO, MC6802,
is shown
in Figure
20.
When the MC14681~/&~,~mapped
as shown in Figures 19
and 20, the AS and D\%,~inputs should be left in a low state
D ($OD)
LSB
b6
b5
b4
b3
b2
bl
bO
Read Only
VRT
o
0
0
0
0
0
0
Register
RAM
and time
when the part iqjf~}lbeing accessed. Refer to the _
description
J@~l\~
conditions
which
must be met
STBY ca~, ~~ r,~ognized,
Figur~~:?
The valid
(VRT)
bit indicates
the
the VRT bit when the power-sense
program can set the VRT bit when
:h~u~.be
;&8f&; “t:
pin is low. The processor
the time and calendar are
be set by reading
MOTOROLA
Register
the subroutines
in a non-multiplexed
entered
with
the registers
which
system.
maybe
pin
before
used for
The subroutines
containing
the following
$Q,f$:?@~&cumulator A: The address of the RTC to be accessed.
‘~~~~> Accumulator
B: Write: The data to be written.
~~..~t
Read: The data read from the RTC.
.:!A
l,The RTC is mapped to two consecutive
memory locations
initialized
to indicate that the RAM and time are valid. The
VRT is a read only bit which is not modified
by the RES~T
bit can only
fl!~ftrates
dat~jtrans%rs
condition
of the contents
of the RAM, provided
the power
sense (PS) pin is satisfactorily
connected.
A “O” appears in
pin. The VRT
assume
quickly.
CMOS gates are used, the C—Ssetup time may be
Figure 18 illustrates
an alternative
method o?s:$hip
MCW08,
b7
–
done
dress and data bus togetherik’~:~~~
An example using eitha~t~b:~~otorola
1 are read
can not be written.
MSB
VRT
interfaces
be
MC146818A with non-multiplexed
face uses available bus control
UF is cleared
C read or a RESET.
b3 TO bO – The unused
as “O’s”.
1~.
processors.
computers
(MCU) by using eleven port lineS@~~,@Ubwn in
Figure 19. Non-multiplexed
bus micropro@~*&~an
be in.*.$ ‘ ‘ {*({F
terfaced with additional
support.
,<,,:.@$s
There
is one method
of usin~.+~~~~@ultiplexed
bus
UF – The update-ended
interrupt
flag (UF) bit is set after
each update cycle. when the UIE bit is a “l”,
the “l”
in UF
asserting
microproces-
selection which will accommodate
such slower dq~’~~&!
The MC146818A
can be interfaced
to single#[email protected]
that the current time has matched the alarm time. A “l”
in
the AF causes the ~
pin to go low, and a “l” to appear in
the IRQF bit, when the AIE bit also is a “1 .“ A RESET or a
read of Register C clears AF.
causes the IRQF bit to be a “l”,
for use with
multiplexed
bus.
to bus-compatible
metalgate
violated.
bit indicates
INTERFACING
is best suited
sors which generate an address-then-data
Figures 16 and 17 show typical interfaces
decoding
and sets the IRQF bit when PIE is also a “l”.
The PF bit is
cleared by a RESET or a software
read of Register C.
AF
MC146818A
Q:~?~,,
.,\,., ~~:;,>,,
RTC and RTC+
1 as shown
in Figure
–
20.
FIGURE ~@~~:*l&18A
INTERFACED WITH
COM,,@~~J@& MULTIPLEXED BUS MICROPROCESSORS
*
H
>
MC6801
MC146B05E2
+
w
Address
Decode*
i
CT
RESET~
I
I
I
I
L——
SiliconGate CMOS or TTL
Address Decoding
—_
—__
CKOUT
——,
———
R/~
DS AS
AD@AD7
MC146818A
VDD
●High-Speed
\
~Q
RESET
I
I
Other
Peripherals
and
Memorv
———
CKFS
STBY
SQW
+ 1
H
@
MOTOROLA
Semiconductor
Products Inc.
16
-—.
FIGURE 17 – MC148818A INTERFACED WITH
COMPETITOR COMPATIBLE MULTIPL~ED
BUS MICROPROCESSORS
I
8 Address/Data
8
/
Address Latch Enable (ALE~
8085
Read ~)
+
8M
8049
+
e
Wri?e (=)
~
Interrupt Request
Other
Periph~@ls
andw~y
4
8/4
Address
Address
Decode
‘:(,,,
I
m
l~Q
R/~
AS
DS
~m~>
FIGURE 18 – MC ~~8A
INTERFACE WITH MC148805W
CMOS MULTIPLEXED MICROP~@~,SOR
WITH SLOW ADDRESSING
DECODING
M C14@05E2
@ti’$~~?exed
Address/Data
Oscl
I
I
——
AS
RIW
IRQ ADO-AD7
RESET
MC146818A
I
VDD
I
I
MOT
CKOUT
‘1
CKFS
A
STBY
SQW
4
I
F
I
EI I
~_______-----___2l
I
v ~D
This illustrates the use of CMOS gating for address decoding.
MOTOROLA
Semiconductor
@
17
Products Inc.
4. IW304 MHz
(Typ)
FIGURE 19 – MCl~18A
INTERFACED WITH THE PORTS OF A
TYPICAL SINGLE CHIP MICROCOMPUTER
4. 193W
—
MHz (Tvp)
a
M C3870
M C6805
MC 146805
S2000
8021
t
I
I
I
——
L———
* NOTE: C= can be controlled
by a port pin (ifJav}#able).
*.
<$
AS
STBY
fl_
Power
Failure
Circuit
(See STBY
Description)
DO-D7
~ADo-AD7
—
Vss
MOTOROLA
@
Semiconductor
Products Inc.
18
.-—
FIGURE 21 – SUBROUTINE FOR READING AND WRITING
THE MCl@18A
WITH A NON-MULTIPLIED
BUS
READ
STA
LDAB
RTS
RTC
RTC+ 1
WRITE
STA
STAB
RTS
RTC
RTC+ 1
B
MOTOROLA
Semiconductor
19
Products Inc.
PACKAGE
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reserves
not assume
patent
any
rights
Affirmative
the right
liability
nor the rights
Action
m
to make
arising
changes
without
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out of the application
of others.
Motorola
notice
DIMENSIONS
to any products
or use of any product
and @are
registered
herein
or circuit
trademarks
to improve
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of Motorola,
herein;
reliability,
neither
Inc. Motorola,
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does
or design.
it convey
Motorola
any license
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its