Sony CXA1690Q Head amplifier for digital ccd camera Datasheet

CXA1690Q
Head Amplifier for Digital CCD Cameras
Description
The CXA1690Q is a bipolar IC developed as a
head amplifier for digital CCD cameras. The
CXA1690Q provides the following functions:
correlated double sampling, AGC for CCD signals,
GCA for chroma signals, GCA for line signals,
sample and hold for A/D converters, blanking, and
reference voltage output/output driver for A/D
converters.
Features
• Permits higher sensitivity with a high-gain AGC
amplifier
• Blanking function for the purpose of calibrating the
deviation in black levels of the CCD output signals
• Permits output offset adjustment
• Provides a regulator output pin for the reference
voltage for A/D converters
• Built-in GCA that amplifies video signals (chroma
and line signals) from an external source
• Built-in sample-and-hold circuits (for both camera
signals and video signals) required by external A/D
converters
Absolute Maximum Ratings
• Supply voltage
• Operating temperature
• Storage temperature
• Allowable power dissipation
VCC
Topr
Tstg
PD
Operating Conditions
Supply voltage
VCC1, 2, 3
32 pin QFP (Plastic)
Structure
Bipolar silicon monolithic IC
Applications
Digital CCD cameras
14
V
–20 to +75
°C
–65 to +150
°C
460
mW
4.5 to 5
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93X02A8X-PS
CXA1690Q
CLPDM
GND1
SHD
SHP
VCC1
CCDLEVEL
AGCCONT
AGCMAX
Block Diagram and Pin Configuration
24
23
22
21
20
19
18
17
PIN 25
DIN 26
AGCCLP
SH1 SH2
LPF CAMSH
AGC
AGCCLP
15
CLPOB
14
XRS
13
PBLK
12
OFFSET
11
VRT
10
VRB
9
VCC3
BLK
SH3
VCC2 27
16
CDSCLP1
NC 28
REF
BOTTOM
CDSCLP2
REF
TOP
LINE 29
GND2 30
LINCLP
LIN
AMP
C/V
SW
VISW
CAMCLP
DRV
VISH
LOUTCLP
RFCONT 31
RFDC
RFGCA
–2–
VSHI
CSHI
5
6
7
8
CLPDRV
4
DRVOUT
3
GND3
2
VSHP
1
PB/REC
CLPSW
CAM/VIDEO
PBRFC 32
CXA1690Q
Pin Description
1
Symbol
CAM
VIDEO
Pin voltage
PB REC
Description
Switches between CAM
mode for the camera
signal system and PB
and LIN modes for the
video signal system.
H: Vcc
L: GND
VTH =
2
Equivalent circuit
127
CAM VIDEO
High
Low
H: Vcc
L: GND
VTH =
46µA
1k
18
Vcc
50
30k
PB REC
Low High
Pin
No.
(Vcc = 4.5V)
1k
18
Vcc
50
VRT
3
VSHI
1.4V
100
2.4k
1k
127
3k
4
CSHI
1.4V
7k
50k
Video system Video system
PB mode
PB mode
Camera system Video system
CAM mode
LIN mode
This pin adjusts the
slew rate when the
video sample-and-hold
circuit (VISH) built into
the CXA1690 is
sampling. Normally
used open.
R = 1K: approx. +6dB;
R = 5K: approx. –6dB
This pin adjusts the
slew rate when the
camera sample-andhold circuit (CAMSH)
built into the CXA1690
is sampling. Normally
used open.
R = 1K: approx. +6dB;
R = 5K: approx. –6dB
100
5
VSHP
Sampling
127
Pulse input for VISH.
18
VTH =
Vcc
50
6
23
30
7
GND3
GND1
GND2
DRVOUT
Typ.
2mA
Driver GND.
Camera signal GND.
Video signal GND.
GND
Camera
system CAM
mode black
level: 1.3V
Video
system LIN
mode black
level: 1.4V
Video
system RF
mode DC
level: 2.2V
Typ.
14mA
–3–
Driver output.
Standard D range.
Camera system
signal:
870mVp-p
Video system PB RFC
signal:
500mVp-p
Video system LIN
signal:
1.4Vp-p
CXA1690Q
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
127
8
CLPDRV
Camera
system CAM
mode black
level: 2V
Video
system LIN
mode clamp
level: 2V
Video
system PB
mode DC
level: 3V
400µ
LIN mode
switch
50µ
127
78µ
157µ
CAM mode
switch
86µ
PB mode
switch
Clamps and outputs
the DRVOUT (Pin 7)
output signal.
The switch for each
mode is closed and the
clamp potentials
applied to this pin by
selecting CAMVIDEO
(Pin 1) or PBRFC (Pin
2).
1k
9
20
27
Vcc3
Vcc1
Vcc2
Driver VCC.
Camera signal VCC.
Video signal VCC.
Vcc
2V regulator output
VRB – VRT load:
160Ω or greater.
16k
10
VRB
Be sure to decouple this
pin near the IC pins to
prevent the oscillation
and external noise when
this pin is not used.
(Recommended
capacitor value: 4.7µF)
2.02V
13k
91µA
4k
6k
4V regulator output.
1k
1.9k
11
VRT
3.88V
25k
91µA
91µA
–4–
91µA
Be sure to decouple this
pin near the IC pins to
prevent the oscillation
and external noise when
this pin is not used.
(Recommended
capacitor value: 4.7µF)
CXA1690Q
Symbol
Pin voltage
Equivalent circuit
Description
54k
1k
127
12
OFFSET
20
Vcc to
Vcc
50
125k
39µA
47k
39µA
This pin offset adjusts the
CLPDRV black level when
the CXA1690 satisfies the
operating conditions for the
camera signal system
(when CAMVI is High and
PBREC is Low).
VCC: approx. 500mV
20/50 VCC: approx.
–50mV
Preset: approx. 70mV
CLPDRV
offset voltage (mV)
Pin
No.
500
70
0
–50
46µA
62k
127
13
PBLK
18
VTH =
Vcc
50
34k
14
XRS
21
SHP
VTH =
1k
22
Vcc
50
200
127
VTH =
22
24k
25
Vcc
50
200
SHD
Sampling
20
50 VCC
VCC
OFFSET voltage (V)
Pulse input for BLK
(active: Low). This pin
functions only when
CAMVI is High and
PBREC is Low, and
calibrates the black
level of the AGC
output waveform.
When the pulse is low,
the DRVOUT potential
is forced to 2V.
High-speed S/H pulse
input for CAMSH
(active: Low).
High-speed S/H pulse
input for SH1
(active: Low).
High-speed S/H pulse
input for SH2 and SH3
(active: Low).
1k
15
CLPOB
VTH =
18
Vcc
50
127
Clamp pulse input for
AGCCLP
(active: Low).
100µ
–5–
CXA1690Q
Pin
No.
Symbol
Pin voltage
Equivalent circuit
1k
16
AGCCLP
Description
2k
Capacitor connection for
AGCCLP clamping.
0.1 to 1µF
Approx. 2.8V
127
41µA
2k
2k
1k
17
AGCMAX
Vcc to
15.5k
127
20
Vcc
50
AGC amplifier MAX gain
adjustment.
15k
62µ
62µ
34.5k
300
18
AGCCONT Vcc to
20
Vcc
50
AGC amplifier gain
adjustment. MIN GAIN
20
for
VCC, MAX
50
GAIN for VCC for both
AGCMAX and
AGCCONT.
127
4k
20k
20.5µ
41µ
38.4k
20.5µ
20.5µ
41µ
20.5µ
200
19
CCD
LEVEL
DIN input
CCD signal
black level:
approx. 2.6V
CCD level detector
260µ
–6–
CXA1690Q
Pin
No.
Symbol
Pin voltage
Equivalent circuit
1k
Description
1k
63k
127
34k
86µ
24
CLPDM
VTH =
86µ
18
Vcc
50
Clamp pulse input
(active: Low).
78µ
63k
1k
34k
39µ
86µ
14k
127
36k
0.9µ
25
PIN
DIN
CCD signal input.
Black level:
approx. 2.6V
2k
2k
1k
29
LINE
Clamp
potential:
approx. 2.5V
10k
127
LIN signal input.
200µ
3µ
–7–
100µ
CXA1690Q
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
4k
1k
31
RFCONT
Vcc to
35k
127
20
Vcc
50
RFGCA gain control.
42k
50µ
52k
100µ
127
7.3k
10k
32
PBRFC
100µ
10k
approx. 2.8V
46k
18k
41k
–8–
100µ
PBRFC signal input.
CXA1690Q
Electrical Characteristics
Item
Camera
Current mode
consumpLINE mode
tion
RF mode
AGC
Symbol
(Ta = 25°C, VCC1, 2, 3 = 4.5V)
Conditions
Min.
Typ.
Max.
IDC
CAM/VIDEO = 4.5V, PB/RFC = 0V
—
49
62
IDL
CAM/VIDEO = 0V, PB/RFC = 4.5V
—
33
42
IDR
CAM/VIDEO = 4.5V, PB/RFC = 4.5V
—
33
42
AGCCONT
max.
A CONmax. AGCMAX = 4.5V, AGCCONT = 4.5V
40
43
—
AGCCONT
min.
A CONmin.
AGCMAX = 4.5V, AGCCONT = 1.8V
—
7.8
10
AGCMAX
min.
A MAXmin.
AGCMAX = 1.8V, AGCCONT = 4.5V
—
19
21
A CONmax.–A CONmin.
32
35
—
2.05
—
Dynamic
range max.
AGCMAX = 4.5V, AGCCONT = 4.5V
AGCmax. D Level at which the CLPOUT output
signal is saturated
1.9
Dynamic
range min.
AGCmin. D
AGCMAX = 4.5V, AGCCONT = 1.8V
Level at which the CLPOUT output
signal is saturated
1.9
2.05
—
Offset High
CAOF high
OFFSET = 4.5V
440
490
—
CAOF low
OFFSET = 1.8V
—
–65
–30
Offset
Preset
CAOF pre
OFFSET = 0V
13
43
73
VRT DC
level
VRTO
With 200Ω load
3.66
3.86
4.06
VRB DC
level
VRBO
With 200Ω load
1.88
2.03
2.18
VRT – VRB
∆VR
With 200Ω load
1.73
1.83
1.93
BLK
Offset
BLKOF
BLKOF (BLK = 4.5V)
– BLKOF (BLK = 0V)
–5
7
15
LINGCA
Gain
LIN G
Adjust the DC level so that LIN input
= 15kHz, 500mVp-p sine wave
LINCLP.
8.5
9.5
10.5
RF CONT
max.
RF
CONmax.
RFCONT = 4.5V, 15kHz, 80mVp-p
sine wave
14
17
—
RF CONT
min.
RF
CONmin.
RFCONT = 1.8V, 15kHz, 400mVp-p
sine wave
—
0.5
2
REF
RFGCA
mA
dB
Amount of
AGC G
variation in gain
CAMCLP Offset Low
Unit
–9–
V
mV
V
mV
dB
CXA1690Q
Electrical Characteristics Measurement Circuit
23
24
21
22
18
19
20
AGCMAX
AGCCONT
CCDLEVEL
VCC1
SHP
SHD
GND1
CLPDM
VCC
17
AGCCLP 0.1µF
25
1µF
16
PIN
1µF DIN
15
SH1 SH2
BLK
LPF CAMSH
AGC
XRS
SH3
27
VCC
CLPOB
AGCCLP
26
VCC2
14
CDSCLP1
PBLK
NC 28
REF
BOTTOM
CDSCLP2
13
REF
TOP
12
29
LINE
30
GND2
VISW
LINCLP
LIN
AMP
VRT
DRV
200
VRB
LOUTCLP
31
PBRFC
10
4.7µ
VCC3 VCC
RFDC
32
9
RFGCA
CLPSW
0.047µF
6
8
7
DRVOUT
GND3
VSHP
CSHI
PB/REC
CAM/VIDEO
5
4
3
2
VSHI
1
1µF
22
VCC
20k
VCC
10p
3V
Measurement Timing Chart
1H
Equivalent to the black
Differs for
each test
DIN
LIN
PBRFC
4.7µ
11
CAMCLP
VISH
OFFSET
CLPDRV
RFCONT
C/V
SW
Differs for
each test
2µs
VCC
CLPOB
GND
2µs
VCC
CLPDM
GND
VCC
PBLK
GND
– 10 –
PBRFC
VCC
LIN
VCC
CCD
LINE
0.047µF
PBRFC
RFCONT
50k
27
26
25
32
31
30
29
NC 28
VCC2
DIN
GND2
0.1µF
1µF
1µF
PIN
VCC
1
VCC
2
LIN
AMP
RFGCA
LINCLP
22
19
1k
10k
1k
10k
1µF
8
CLPSW
RFDC
LOUTCLP
7
VSHP
17
REF
TOP
CAMCLP
6
DRV
50k
VCC
BLK
REF
BOTTOM
CAMSH
18
5
C/V
SW
LPF
AGCCLP
20
4
VISH
AGC
21
3
VISW
CDSCLP2
CDSCLP1
SH3
SH1 SH2
23
SHP
VSHI
24
SHD
SHD
SHP
CSHI
CLPDM
VCC1
VSHP
AGCMAX
VCC
CCDLEVEL
GND3
CLPDM
CRM/
VIDEO
GND1
PB/
REC
AGCCONT
DRVOUT
– 11 –
CLPDRV
Application Circuit
VCC3
VRB
VRT
4.7µF
4.7µF
50k
PBLK
XRS
OFFSET
VCC
PBLK
XRS
CLPOB
0.1µF
AGCCLP
VCC
VRB
A/D IN
VRT
A/D
Application circuits shown are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any
infringement of third party patent and other right due to same.
9
10
11
12
13
14
15
16
50k
VCC
CXA1690Q
CXA1690Q
Description of Operation
1. Camera signal processing system
Process the video signal processing pins as follows only in camera mode.
<5> VSHP
... Connect to GND.
<29> LINE
... Connect to GND via the capacitor (approx. 0.01µF).
<31> RFCONT ... Connect to GND.
<32> PBRFC ... Connect to GND via the capacitor (approx. 0.01µF).
Operating conditions
The camera signal processing system operates when CAM/VIDEO is High, and PB/REC is Low.
Camera Signal Processing System Timing Chart
CCD output
Signal
interval
Precharge level
OPB
interval
Dummy pixel
interval
Signal
interval
Signal level
SHP
SHD
SH1 output
2.6V
[∗1]
[∗2]
SH2 output
SH3 output
2.6V
CLPDM
(Dummy bit section 2µ
for the dummy pixel interval)
AGC output
–N times ( SH3 output
– SH2 output
2µs
Black level
Basic black level
2.05V
)
[∗3]
XRS
CLPOB
(2µ for the OPB interval)
2µs
CAMSH output
2.05V
PBLK
(10µ for the dummy
pixel interval)
10µs
BLK output
CAMVISW output
DRVOUT output
[∗4]
2.05V – Vf ≈ 1.25V
CLPDM
2µs
CLPOUT output
[∗5]
Approx. 2.1V when OFFSET is 0V
20
VCC
50
Approx. 2.5V for 50 VCC
50
Approx. 2.0V for
– 12 –
CXA1690Q
CDS:
The CCD signal from the CCD image sensor enters PIN and DIN where it is correlated double sampled
(CDS: Correlated Double Sampling) by SH1, SH2 and SH3. The precharge level of the CCD output signal is
sampled-and-held and output by the SH2 output, and the signal level is sampled-and-held and output by the
SH3 output.
CDSCLP:
The CDSCLP stabilizes the DC level of the input signal, clamps (CLPDM) the input signal during the dummy
pixel interval for the purpose of eliminating the AGC input offset, and combines the DC level ([∗1], [∗2]) of
SH2 and SH3.
AGC:
The gain can be varied with the AGCMAX and AGCCONT voltage control (20/50) VCC to VCC. The maximum
gain can be varied from 19 to 43dB for AGCMAX, and from 7.9 to 43dB for AGCCONT.
LPF:
A primary low-pass filter has been installed for the purpose of eliminating unused bands and white noise and
improving S/N.
CAMSH:
The CAMSH is used for camera system signal processing. It is a sample-and-hold circuit which synchronizes
the data read-in timing for the external A/D. The slew rate of the input signal for the sample-and-hold circuit
can be controlled by adjusting the input current to the CSHI pin.
AGCCLP:
The basic black level is set ([∗3]) by clamping it with the CLPOB clock during the OPB interval of the AGC
output waveform. The capacitance for AGCCLP is connected to the AGCCLP pin.
BLK:
The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not
fall below the basic black level and replacing the DC potential. ([∗4])
The signal is blanked when PBLK is low.
C/VSW:
When the CAM/VIDEO and PB/REC pin voltages are set so that the camera signal processing system
operates, C/VSW leads the BLK output (camera signal) into the DRV. In addition, when these voltages are
set so that the video signal processing system operates, C/VSW leads the VISH output (video signal) into the
DRV.
CLPSW:
By selecting the CAM/VIDEO and PB/REC pin voltages, either [CAMCLP] is connected and lead into the
CLPDRV pin as the clamp for the output signal of the camera signal processing system, or [LOUTCLP] as
the clamp for the LIN mode output signal or [RFDC] as the DC shift for the PBREC mode output signal of the
video signal processing system.
DRV:
DRV drives the external A/D. RF mode or LIN mode signals for either the camera or video signals are input
to the DRV and output from DRVOUT by switching C/VSW.
CAMCLP:
The signal black level interval is clamped by the CLPDM clock to bring camera system signals within the
allowable input voltage range for the external A/D, and the signals are output to CLPOUT. ([∗5])
In addition, the CAMCLP contains an OFFSET control pin which adjusts the CLP potential for the purpose of
compensating the clamp level difference generated by the DRV.
REFBOTTOM, REFTOP:
REFBOTTOM and REFTOP are reference voltage source for the external A/D. They are connected to VRB
and VRT, and supply 2V and 4V to the A/D.
– 13 –
CXA1690Q
2. Video signal processing system
Operating conditions
The video signal processing system has two modes: LIN signal mode and PBREC signal mode.
The video signal processing system operates in LIN signal mode when CAM/VIDEO is Low, and PB/REC is
High.
The video signal processing system operates in PBREC signal mode when PB/REC is High.
Video Signal Processing System Timing Chart
LIN mode
LIN input
2.5V
LINGCA output
9.5dB
2.1V
VISP
DRVOUT output
(CLPDRV output)
1.4V
(2V)
LIN signal mode
LINCLP:
The video signal enters the LIN pin. LINCLP sync tip clamps the input signal to allow full input.
The input signal level and frequency are respectively 500mVp-p (typ.) and DC up to approx. 7MHz.
LINAMP:
This is a 9.5dB gain amplifier.
VISW:
VISW switches between the LIN signal and PBRFC signal for the video signal processing system.
The signals are switched according to the input conditions of the CAM/VIDEO and PB/REC pins.
VISH:
The VISH is used for video signal processing system. It is a sample-and-hold circuit which synchronizes the
data read-in timing for the external A/D. The slew rate of the input signal for the sample-and-hold circuit can
be controlled by adjusting the input current to VSHI.
LOUTCLP:
LOUTCLP is a clamp circuit which operates when the LIN signal is output by the DRV. The clamp potential is
2V.
– 14 –
CXA1690Q
PBREC signal mode
RFGCA:
This is an amplifier which controls the gain of the video chroma RF signal input to PBRFC. The RFCONT
voltage can be varied from (20/50) VCC to VCC, enabling the gain to be varied from 0.5 to 17dB.
The input signal level and frequency are respectively 200mVp-p (typ.) and DC up to approx. 1.5MHz.
RFDC:
RFDC is a DC bias circuit which operates when the PBREC signal is output by the DRV. The DC bias
potential is 3V.
PBREC mode
PBREC input
2.8V
REGCAOUT output
0.5 to 17dB
2.9V
VISH
DRVOUT output
(CLPDRV output)
2.2V
(3V)
– 15 –
CXA1690Q
Example of Representative Characteristics
AGCCONT control temperature characteristics
AGCMAX control temperature characteristics
45
45
VAGCMAX-Gain
VAGCMAX-Gain
40
40
VCC = 4.5V
VAGCCONT = 4.5V
30
Gain [dB]
30
Gain [dB]
VCC = 4.5V
VAGCCONT = 4.5V
Ta = 75°C
35°C
–20°C
20
Ta = 75°C
35°C
–20°C
20
10
10
0
0
1.5
2
3
4
1.5
4.5
2
3
4
4.5
VAGCMAX [V]
VAGCCONT [V]
AGC dynamic range temperature characteristics
RFGCA gain control temperature characteristics
20
2200
VRFCONT-Gain
Drange-T
Ta = 75°C
35°C
–20°C
10dB dynamic range VAGCMAX = 4.5V
VAGCCONT = 1.8V
Gain [dB]
D-range-AGC dynamic range [mV]
VCC = 4.500V
10
2100
40dB dynamic range
VAGCMAX = 4.5V
VAGCCONT = 4.5V
0
1.5
2
3
VRFCONT [V]
2000
–10
0
20
40
60
80
Ta – Temperature [°C]
– 16 –
4
4.5
CXA1690Q
CAMCLP offset temperature characteristics
LINGCA gain control
504.0
VLINCONT-Gain
T-Voff
VCC = 4.5V
VCC = 4.5V, Ta = 25°C
30
Fig.5
502.0
When OFFSET = 4.5V
Voff-CAMCLP offset potential [V]
Gain [dB]
20
10
0
1.6
2.0
3.0
4.0
4.5
VLINCONT [V]
500.0
–10
0
20
40
Ta – Temperature [°C]
60
75
55.0
Fig.6
54.0
53.0
–10
When OFFSET = 0V
0
20
40
60
75
Ta – Temperature [°C]
–52.0
Fig.7
–54.0
When OFFSET = 1.8V
–56.0
–10
0
20
40
Ta – Temperature [°C]
– 17 –
60
75
CXA1690Q
Package Outline
Unit: mm
32PIN QFP (PLASTIC)
9.0 ± 0.2
24
0.1
+ 0.35
1.5 – 0.15
+ 0.3
7.0 – 0.1
17
16
32
9
(8.0)
25
1
+ 0.2
0.1 – 0.1
0.8
0.24
M
+ 0.1
0.127 – 0.05
0° to 10°
PACKAGE MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
QFP-32P-L01
LEAD TREATMENT
EIAJ CODE
QFP032-P-0707
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
– 18 –
0.50
8
+ 0.15
0.3 – 0.1
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