Order this document by MC34119/D The MC34119 is a low power audio amplifier intergrated circuit intended (primarily) for telephone applications, such as in speakerphones. It provides differential speaker outputs to maximize output swing at low supply voltages (2.0 V minimum). Coupling capacitors to the speaker are not required. Open loop gain is 80 dB, and the closed loop gain is set with two external resistors. A Chip Disable pin permits powering down and/or muting the input signal. The MC34119 is available in standard 8–pin DIP, SOIC package, and TSSOP package. • Wide Operating Supply Voltage Range (2.0 V to 16 V), Allows Telephone Line Powered Applications • Low Quiescent Supply Current (2.7 mA Typ) for Battery Powered Applications • Chip Disable Input to Power Down the IC • • • • • • LOW POWER AUDIO AMPLIFIER SEMICONDUCTOR TECHNICAL DATA 8 Low Power–Down Quiescent Current (65 µA Typ) 1 Drives a Wide Range of Speaker Loads (8.0 Ω and Up) P SUFFIX PLASTIC PACKAGE CASE 626 Output Power Exceeds 250 mW with 32 Ω Speaker Low Total Harmonic Distortion (0.5% Typ) Gain Adjustable from <0 dB to >46 dB for Voice Band 8 Requires Few External Components 1 D SUFFIX PLASTIC PACKAGE CASE 751 (SO–8) MAXIMUM RATINGS Rating Value Unit –1.0 to +18 Vdc ±250 mA –1.0, VCC + 1.0 –1.0, VCC + 1.0 Vdc –55, +140 °C Supply Voltage Maximum Output Current at VO1, VO2 Maximum Voltage @ Vin, FC1, FC2, CD Applied Output Voltage to VO1, VO2 when disabled Junction Temperature NOTE: 8 1 DTB SUFFIX PLASTIC PACKAGE CASE 948J (TSSOP) ESD data available upon request. PIN CONNECTIONS Block Diagram and Simplified Application Rf 75 k 6 Audio Input Ci 0.1 C1 1.0 µF Ri 3.0 k Vin 4 FC1 3 – + VCC 5 #1 50 k 125 k 2 8 VO2 FC2 2 7 Gnd FC1 3 6 VCC Vin 4 5 VO1 VO1 Speaker 4.0 k C2* 5.0 µF CD 1 4.0 k – + (Top View) 8 #2 ORDERING INFORMATION FC2 Bias Circuit 50 k VO2 1 CD Chip Disable Device Operating Temperature Range Package MC34119 7 * = Optional Differential Gian = 2 x Rf Ri Plastic DIP MC34119P Gnd This device contains 45 active transistors. MC34119D TA = –20° to +70°C MC34119DTB Motorola, Inc. 1996 MOTOROLA ANALOG IC DEVICE DATA SO–8 TSSOP Rev 1 1 MC34119 RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Max Unit VCC VCD +2.0 0 +16 VCC Vdc Vdc Load Impedance RL 8.0 – Ω Peak Load Current IL – ±200 mA AVD 0 46 dB TA –20 +70 °C Supply Voltage Voltage @ CD (Pin 1) Differential Gain (5.0 kHz Bandwidth) Ambient Temperature ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.) Symbol Min Typ Max Unit ri – >30 – MΩ AVOL1 80 – – dB Closed Loop Gain (Amplifier #2, VCC = 6.0 V, f = 1.0 kHz, RL = 32 Ω) AV2 –0.35 0 +0.35 dB Gain Bandwidth Product GBW – 1.5 – MHz POut3 POut6 POut12 55 250 400 – – – – – – – – – 0.5 0.5 0.6 1.0 – – 50 – – – 12 52 – – – Characteristics AMPLIFIERS (AC CHARACTERISTICS) AC Input Resistance (@ VIn) Open Loop Gain (Amplifier #1, f < 100 Hz) Output Power; VCC = 3.0 V, RL = 16 Ω, THD ≤ 10% VCC = 6.0 V, RL = 32 Ω, THD ≤ 10% VCC = 12 V, RL = 100 Ω, THD ≤ 10% Total Harmonic Distortion (f = 1.0 kHz) (VCC = 6.0 V, RL = 32 Ω, Pout = 125 mW) (VCC ≥ 3.0 V, RL = 8.0 Ω, Pout = 20 mW) (VCC ≥ 12 V, RL = 32 Ω, Pout = 200 mW) mW THD % Power Supply Rejection (VCC = 6.0 V, ∆VCC = 3.0 V) (C1 = ∞, C2 = 0.01 µF) (C1 = 0.1 µF, C2 = 0, f = 1.0 kHz) (C1 = 1.0 µF, C2 = 5.0 µF, f = 1.0 kHz) PSRR Differential Muting (VCC = 6.0 V, 1.0 kHz ≤ f ≤ 20 kHz, CD = 2.0 V) GMT – >70 – dB VO(3) VO(6) VO(12) 1.0 – – 1.15 2.65 5.65 1.25 – – Vdc VOH VOL – – VCC – 1.0 0.16 – – –30 0 +30 dB AMPLIFIERS (DC CHARACTERISTICS) Output DC Level @ VO1, VO2, VCC = 3.0 V, RL = 16 (Rf = 75 k) VCC = 6.0 V VCC = 12 V Output Level High (Iout = –75 mA, 2.0 V ≤ VCC ≤ 16 V) Low (Iout = 75 mA, 2.0 V ≤ VCC ≤ 16 V) Vdc Output DC Offset Voltage (VO1–VO2) (VCC = 6.0 V, Rf = 75 kΩ, RL = 32 Ω) ∆VO Input Bias Current @ Vin (VCC = 6.0 V) IIB – –100 –200 RFC1 RFC2 100 18 150 25 220 40 Input Voltage Low High VIL VIH – 2.0 – – 0.8 – Input Resistance (VCC = VCD = 16 V) RCD 50 90 175 kΩ ICC3 ICC16 ICCD – – – 2.7 3.3 65 4.0 5.0 100 mA mA µA Equivalent Resistance @ FC1 (VCC = 6.0 V) @ FC2 (VCC = 6.0 V) mV nA kΩ CHIP DISABLE (Pin 1) Vdc POWER SUPPLY Power Supply Current (VCC = 3.0 V, RL = ∞, CD = 0.8 V) (VCC= 16 V, RL = ∞, CD = 0.8 V) (VCC = 3.0 V, RL = ∞, CD = 2.0 V) NOTE: Currents into a pin are positive, currents out of a pin are negative. 2 MOTOROLA ANALOG IC DEVICE DATA MC34119 PIN FUNCTION DESCRIPTION Symbol Pin Description CD 1 Chip Disable – Digital input. A Logic “0” (<0.8 V) sets normal operation. A logic “1” (≥2.0 V) sets the power down mode. Input impedance is nominally 90 kΩ . FC2 2 A capacitor at this pin increases power supply rejection, and affects turn–on time. This pin can be left open if the capacitor at FC1 is sufficient. FC1 3 Analog ground for the amplifiers. A 1.0 µF capacitor at this pin (with a 5.0 µF capacitor at Pin 2) provides (typically) 52 dB of power supply rejection. Turn–on time of the circuit is affected by the capacitor on this pin. This pin can be used as an alternate input. Vin 4 Amplifier input. The input capacitor and resistor set low frequency rolloff and input impedance. The feedback resistor is connected to this pin and VO1. VO1 5 Amplifier Output #1. The dc level is ≈ (VCC – 0.7 V)/2. VCC 6 DC supply voltage (+2.0 V to +16 V) is applied to this pin. GND 7 Ground pin for the entire circuit. VO2 8 Amplifier Output #2. This signal is equal in amplitude, but 180° out–of–phase with that at VO1. The dc level is ≈ (VCC – 0.7 V)/2. TYPICAL TEMPERATURE PERFORMANCE (–20° C < TA < +70°C) Function Input Bias Current (@ Vin) Total Harmonic Distortion (VCC = 6.0 V, RL = 32 Ω. Pout = 125 mW, f = 1.0 kHz) Power Supply Current (VCC = 3.0 V, RL = ∞, CD = 0 V) (VCC = 3.0 V, RL = ∞, CD = 2.0 V) MOTOROLA ANALOG IC DEVICE DATA Typical Change Units ±40 pA/°C +0.003 %/°C µA/°C –2.5 –0.03 3 MC34119 DESIGN GUIDELINES Amplifiers Referring to the block diagram, the internal configuration consists of two identical operational amplifiers. Amplifier #1 has an open loop gain of ≥80 dB (at f ≤ 100 Hz), and the closed loop gain is set by external resistor Rf and Ri. The amplifier is unity gain stable, and has a unity gain frequency of approximately 1.5 MHz. In order to adequately cover the telephone voice band (300 Hz to 3400 Hz), a maximum closed loop gain of 46 is recommended. Amplifier #2 is internally set to a gain of – 1.0 (0 dB). The outputs of both amplifiers are capable of sourcing and sinking a peak current of 200 mA. The outputs can typically swing to within ≈0.4 V above ground, and to within ≈1.3 V below VCC, at the maximum current. See Figures 18 and 19 for VOH and VOL curves. The output dc offset voltage (VO1–VO2) is primarily a function of the feedback resistor (Rf), and secondarily due to the amplifiers’ input offset voltages. The input offset voltage of the two amplifiers will generally be similar for a particular IC, and therefore nearly cancel each other at the outputs. Amplifier #1’s bias current, however, flows out of Vin (Pin 4) and through Rf, forcing VO1 to shift negative by an amount equal to [Rf × IIB]. VO2 is shifted positive an equal amount. The output offset voltage, specified in the Electrical Characteristics, is measured with the feedback resistor shown in the Typical Application Circuit, and therefore takes into account the bias current as well as internal offset voltages of the amplifiers. The bias current is constant with respect to VCC. FC1 and FC2 Power supply rejection is provided by the capacitors (C1 and C2 in the Typical Application Circuit) at FC1 and FC2. C2 is somewhat dominant at low frequencies, while C1 is dominant at high frequencies, as shown in the graphs of Figures 4 to 7. The required values of C1 and C2 depend on the conditions of each application. A line powered speakerphone, for example, will require more filtering than a circuit powered by a well regulated power supply. The amount of rejection is a function of the capacitors, and the equivalent impedance looking into FC1 and FC2 (listed in the Electrical Characteristics as RFC1 and RFC2). In addition to providing filtering, C1 and C2 also affect the turn–on time of the circuit at power–up, since the two capacitors must charge up through the internal 50 k and 125 kΩ resistors. The graph of Figure 1 indicates the turn–on time upon application of VCC of +6.0 V. The turn–on time is ≈60% longer for VCC = 3.0 V, and ≈20% less for VCC = 9.0 V. Turn–off time is <10 µs upon removal of VCC. 4 Figure 1. Turn–On Time versus C1, C2 at Power–On 360 300 t, TURN–ON TIME (ms) General The MC34119 is a low power audio amplifier capable of low voltage operation (VCC = 2.0 V minimum) such as that encountered in line–powered speakerphones. The circuit provides a differential output (VO1–VO2) to the speaker to maximize the available voltage swing at low voltages. The differential gain is set by two external resistors. Pins FC1 and FC2 allow controlling the amount of power supply and noise rejection, as well as providing alternate inputs to the amplifiers. The CD pin permits powering down the IC for muting purposes and to conserve power. C1 = 5.0 µF 240 180 120 C1 = 1.0 µF 60 VCC switching from 0 V to 6.0 V 0 0 2.0 4.0 6.0 8.0 10 C2, CAPACITANCE (µF) Chip Disable The Chip Disable (Pin 1) can be used to power down the IC to conserve power, or for muting, or both. When at a Logic “0” (0 V to 0.8 V), the MC34119 is enabled for normal operation. When Pin 1 is at a Logic “1” (2.0 V to VCC V), the IC is disabled. If Pin 1 is open, that is equivalent to a Logic “0,” although good design practice dictates that an input should never be left open. Input impedance at Pin 1 is a nominal 90 kΩ. The power supply current (when disabled) is shown in Figure 15. Muting, defined as the change in differential gain from normal operation to muted operation, is in excess of 70 dB. The turn–off time of the audio output, from the application of the CD signal, is <2.0 µs, and turn on–time is 12 ms–15 ms. Both times are independent of C1, C2, and VCC. When the MC34119 is disabled, the voltages at FC1 and FC2 do not change as they are powered from VCC. The outputs, VO1 and VO2, change to a high impedance condition, removing the signal from the speaker. If signals from other sources are to be applied to the outputs (while disabled), they must be within the range of VCC and Ground. Power Dissipation Figures 8 to 10 indicate the device dissipation (within the IC) for various combinations of VCC, RL, and load power. The maximum power which can safely be dissipated within the MC34119 is found from the following equation: PD = (140°C – TA)/θJA where TA is the ambient temperature; and θJA is the package thermal resistance (100°C/W for the standard DIP package, and 180°C/W for the surface mount package.) The power dissipated within the MC34119, in a given application, is found from the following equation: PD = (VCC x ICC) + (IRMS x VCC) – (RL x IRMS2) where ICC is obtained from Figure 15; and IRMS is the RMS current at the load; and RL is the load resistance. Figures 8 to 10, along with Figures 11 to 13 (distortion curves), and a peak working load current of ±200 mA, define the operating range for the MC34119. The operating range is further defined in terms of allowable load power in Figure 14 for loads of 8.0 Ω, 16 Ω and 32 Ω. The left (ascending) portion MOTOROLA ANALOG IC DEVICE DATA MC34119 Layout Considerations Normally a snubber is not needed at the output of the MC34119, unlike many other audio amplifiers. However, the PC board layout, stray capacitances, and the manner in which the speaker wires are configured, may dictate otherwise. Generally, the speaker wires should be twisted tightly, and not more than a few inches in length. of each of the three curves is defined by the power level at which 10% distortion occurs. The center flat portion of each curve is defined by the maximum output current capability of the MC34119. The right (descending) portion of each curve is defined by the maximum internal power dissipation of the IC at 25°C. At higher ambient temperatures, the maximum load power must be reduced according to the above equations. Operating the device beyond the current and junction temperature limits will degrade long term reliability. Figure 2. Amplifier #1 Open Loop Gain and Phase 0 72 Phase AVOL (dB) 108 144 60 180 Gain 40 20 0 100 1.0 k 10 k f, FREQUENCY (Hz) 100 k MOTOROLA ANALOG IC DEVICE DATA 1.0 M Rf = 150 k, Ri = 6.0 k DIFFERENTIAL GAIN (dB) 36 80 φ, EXCESS PHASE (DEGREES) 100 Figure 3. Differential Gain versus Frequency 36 32 24 16 Rf = 75 k, Ri = 3.0 k Rf 0.1 Input Ri 8 0 100 – #1 + VO1 VO2 VO #2 1.0 k 10 k f, FREQUENCY (Hz) 20 k 5 MC34119 Figure 4. Power Supply Rejection versus Frequency Figure 5. Power Supply Rejection versus Frequency (C2 = 10 µF) (C2 = 5.0 µF) C1 ≥ 1.0 µF PSRR, POWER SUPPLY REJECTION (dB) PSRR, POWER SUPPLY REJECTION (dB) 60 50 C1 = 0.1 µF 40 30 C1 = 0 20 10 0 200 1.0 k 10 k 20 k 60 C1 ≥ 1.0 µF 50 C1 = 0.1 µF 40 30 20 C1 = 0 10 0 200 1.0 k 20 k f, FREQUENCY (Hz) Figure 6. Power Supply Rejection versus Frequency Figure 7. Power Supply Rejection versus Frequency (C2 = 1.0 µF) (C2 = 0) PSRR, POWER SUPPLY REJECTION (dB) 60 PSRR, POWER SUPPLY REJECTION (dB) 10 k f, FREQUENCY (Hz) C1 = 5.0 µF 50 C1 = 1.0 µF 40 C1 = 0.1 µF 30 20 10 C1 = 0 0 200 1.0 k 10 k 20 k 60 50 C1 = 5.0 µF 40 30 C1 = 1.0 µF 20 C1 = 0.1 µF 10 0 200 1.0 k f, FREQUENCY (Hz) 10 k 20 k f, FREQUENCY (Hz) Figure 8. Device Dissipation, 8.0 Ω Load Figure 9. Device Dissipation, 16 Ω Load 1000 1200 800 1000 DEVICE DISSIPATION (mW) DEVICE DISSIPATION (mW) VCC = 16 V VCC = 12 V VCC = 6.0 V 600 400 VCC = 3.0 V 200 0 800 VCC = 6.0 V 600 400 VCC = 3.0 V 200 0 30 60 90 LOAD POWER (mW) 6 VCC = 12 V 120 150 0 0 100 200 300 400 LOAD POWER (mW) MOTOROLA ANALOG IC DEVICE DATA MC34119 Figure 11. Distortion versus Power Figure 10. Device Dissipation, 32 Ω Load (f = 1.0 kHz, AVD = 34 dB) VCC = 12 V VCC = 16 V 1000 THD, TOTAL HARMONIC DISTORTION (%) DEVICE DISSIPATION (mW) 1200 800 600 400 VCC = 6.0 V 200 VCC = 3.0 V 0 0 100 200 300 400 10 8.0 VCC = 3.0 V, RL = 16 Ω 6.0 4.0 VCC = 16 V, VCC = 6.0 V, RL = 32 Ω RL = 16 Ω 2.0 0 100 VCC = 3.0 V, RL = 8.0 Ω VCC = 16 V, RL = 32 Ω Limit VCC = 6.0 V, RL = 16 Ω VCC = 12 V, RL = 32 Ω 100 200 300 400 500 POut, OUTPUT POWER (mW) THD, TOTAL HARMONIC DISTORTION (%) THD, TOTAL HARMONIC DISTORTION (%) (f = 1, 3.0 kHz, AVD = 12 dB) 10 8.0 VCC = 3.0 V, RL = 16 Ω VCC = 3.0 V, RL = 8.0 Ω 6.0 2.0 0 100 I CC , POWER SUPPLY CURRENT (mA) LOAD POWER (mW) 400 RL = 16 Ω 300 RL = 8.0 Ω 100 MOTOROLA ANALOG IC DEVICE DATA 200 300 POut, OUTPUT POWER (mW) 400 500 Figure 15. Power Supply Current RL = 32 Ω VCC, SUPPLY VOLTAGE (V) VCC = 12 V, RL = 32 Ω 0 4.0 TA = 25°C–Derate at higher temperatures 0 0 2.0 4.0 6.0 8.0 10 VCC = 6.0 V, RL = 32 Ω VCC = 16 V, RL = 32 Ω Limit VCC = 6.0 V, RL = 16 Ω Limit 4.0 Figure 14. Maximum Allowable Load Power 200 500 Figure 13. Distortion versus Power 2.0 500 400 Figure 12. Distortion versus Power VCC = 6.0 V, RL = 32 Ω 0 300 POut, OUTPUT POWER (mW) 8.0 VCC = 3.0 V, RL = 16 Ω 0 200 LOAD POWER (mW) 10 4.0 VCC = 12 V, RL = 32 Ω 0 500 (f = 3.0 kHz, AVD = 34 dB) 6.0 VCC = 6.0 V, RL = 32 Ω VCC = 3.0 V, RL = 8.0 Ω RL = ∞ CD = 0 3.0 2.0 1.0 CD = VCC 0 12 14 16 0 2.0 4.0 6.0 8.0 10 12 14 16 VCC, SUPPLY VOLTAGE (V) 7 MC34119 Figure 17. Large Signal Response INPUT 1.0 mV/DIV INPUT 80 mV/DIV OUTPUT 1.0 V/DIV OUTPUT 20 mV/DIV Figure 16. Small Signal Response 20 µs/DIV 20 µs/DIV Figure 18. VCC–VOH @ VO1, VO2 versus Load Current 1.4 1.2 VOL, OUTPUT LOW LEVEL (V) 1.4 1.3 VCC –VOH (V) Figure 19. VOL @ VO1, VO2 versus Load Current 1.5 1.2 1.1 2.0 ≤ VCC ≤ 16 V 1.0 0.9 TA = 25°C 0.8 0 TA = 25°C VCC = 2.0 V 1.0 0.8 0.6 VCC = 3.0 V 0.4 VCC ≥ 6.0 V 0.2 0 40 80 120 160 200 0 40 ILOAD, LOAD CURRENT (mA) 80 Figure 20. Input Characteristics @ CD (Pin 1) 200 75 k 6 VCC 160 0.1 3.0 k ICD , (µA) 160 Figure 21. Audio Amplifier with High Input Impedance 200 4 120 – #1 + 3 0.1 80 5 4.0 k Input 5.0 µF 40 2 Valid for VCD ≤ VCC 0 120 ILOAD, LOAD CURRENT (mA) 0 4.0 8.0 12 50 k 125 k – + Speaker 4.0 k Bias Circuit 50 k MC34119 16 VCD, CHIP DISABLE VOLTAGE (V) 8 #2 7 1 Disable Gnd Differential Gain = 34 dB Frequency Response: See Figure 3 Input Impedance 125 kΩ PSRR 50 dB [ 8 [ MOTOROLA ANALOG IC DEVICE DATA MC34119 Figure 22. Audio Amplifier with Bass Suppression Figure 23. Frequency Response of Figure 22 75 k 5.1 k 5.1 k 6 4 – #1 + 3 0.1 VCC 5 4.0 k Input 5.0 µF 50 k 125 k 2 AVD, DIFFERENTIAL GAIN (dB) 0.05 0.05 – + Speaker 4.0 k 8 #2 50 k Bias Circuit MC34119 1 Disable 36 32 24 16 8.0 0 100 7 1.0 k 10 k f, FREQUENCY (Hz) Gnd Figure 24. Audio Amplifier with Bandpass 20 k Figure 25. Frequency Response of Figure 24 1000 pF AVD, DIFFERENTIAL GAIN (dB) 1000 pF 100 k 100 k 0.05 0.05 5.1 k 5.1 k 6 VCC 4 – #1 + 3 0.1 5 4.0 k Input 50 k 125 k 5.0 µF 2 – + Speaker 4.0 k 8 #2 50 k Bias Circuit MC34119 36 32 24 16 8.0 0 100 1 1.0 k 10 k f, FREQUENCY (Hz) Disable 20 k 7 Gnd Figure 26. Split Supply Operation Rf 75 k 6 VCC (+1.0 V to +8.0 V) Ci Ri 0.1 3.0 k Audio Input Vin 4 FC1 3 FC2 2 – #1 + VO1 5 Speaker 4.0 k 50 k 125 k – + 4.0 k Bias 1 Circuit 50 k MC34119 VO2 8 #2 CD 4700 20 k 7 VEE (–1.0 V to –8.0 V) NOTE: If VCC and VEE are not symmetrical about ground then FC1 must be connected through a capacitor to ground as shown on the front page. MOTOROLA ANALOG IC DEVICE DATA Chip Disable 20 k 10 k VCC VEE 9 MC34119 OUTLINE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 626–05 ISSUE K 8 5 –B– 1 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4 F –A– NOTE 2 DIM A B C D F G H J K L M N L C J –T– N SEATING PLANE D M K G H 0.13 (0.005) M T A B M MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC ––– 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC ––– 10_ 0.030 0.040 M D SUFFIX PLASTIC PACKAGE CASE 751–05 (SO–8) ISSUE P –A– M 1 4 R 4X 0.25 (0.010) –B– X 45 _ B M 5 P 8 NOTES: 1. DIMENSIONS A AND B ARE DATUMS AND T IS A DATUM SURFACE. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 3. DIMENSIONS ARE IN MILLIMETER. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 6. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. J M_ C F G –T– K SEATING PLANE 8X D 0.25 (0.010) 10 M T B S A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.18 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 MOTOROLA ANALOG IC DEVICE DATA MC34119 OUTLINE DIMENSIONS DTB SUFFIX PLASTIC PACKAGE CASE 948J–01 (TSSOP) ISSUE O 8x 0.15 (0.006) T U 0.10 (0.004) S NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4 DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5 DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7 DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. K REF M T U S V S ÇÇÇ ÉÉ ÇÇÇ ÉÉ ÇÇÇ K 2X L/2 K1 8 5 J J1 B –U– L PIN 1 IDENT. SECTION N–N 4 1 N 0.25 (0.010) 0.15 (0.006) T U S A –V– M N F DETAIL E –W– C 0.10 (0.004) –T– SEATING PLANE D G MOTOROLA ANALOG IC DEVICE DATA SEE DETAIL E H DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 2.90 3.10 4.30 4.50 ––– 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.114 0.122 0.169 0.177 ––– 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 11 MC34119 Motorola reserves the right to make changes without further notice to any products herein. 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