Order this document by MC44871/D The MC44871 is a tuning circuit for TV, VCR and Multimedia tuner applications. This device contains on one chip all the functions required for PLL control of a VCO. This integrated circuit also contains a high frequency prescaler and thus can handle frequencies up to 1.3 GHz. PLL TUNING CIRCUIT WITH HIGH SPEED I2C BUS AND 30 V TUNING SUPPLY The MC44871 has an integrated dc/dc converter to generate the 30 V supply voltage for the tuning amplifier on the chip. A tuner using the MC44871 does not require an external 30 V supply. SEMICONDUCTOR TECHNICAL DATA The MC44871 is controlled by a I2C bus, and has a chip address function. The MC44871 data format is the same as the MC44818. The MC44871 is manufactured on a single silicon chip using Motorola’s high density bipolar process, MOSAIC (Motorola Oxide Self Aligned Implanted Circuits). • • • • • • • • • 16 The Pin Called VCC2 for the MC44818 is Now Called CP (Charge Pump). This Pin is the Output of the DC/DC Converter; a 1.0 nF Capacitor Replaces the Need for an External 30 V Supply High Speed I2C Bus (up to 800 kHz) I2C Bus Read Mode for Lock Detector and AFC Level 1 DTB SUFFIX PLASTIC PACKAGE CASE 948F (TSSOP–16) HF Input is Balanced MC44871 has Three PNP High Current (30 mA) Band Buffers (B0, B1, B2) and One NPN Low Current (5.0 mA) Band Buffer (B4) VCC Internally Supplies PNP Band Buffers The Tuning Voltage is Generated Through an External Pull–Up Resistor (750 kΩ) Less Phase Comparator Output Current PIN CONNECTIONS (16 Pin TSSOP) Single 5.0 V Supply Operation MOSAIC is a trademark of Motorola, Inc. ORDERING INFORMATION Device MC44871DTB Operating Temperature Range Package TA = –20° to +85°C TSSOP–16 This document contains information on a new product. Specifications and information herein are subject to change without notice. MOTOROLA ANALOG IC DEVICE DATA VTUN 1 16 Amp In CP 2 15 Xtal HF1 3 14 SCL HF2 4 13 SDA Gnd 5 12 ADD B2 6 11 VCC B1 7 10 ADC B0 8 9 B4 (Top View) Motorola, Inc. 1998 Rev 1 1 MC44871 Figure 1. Representative Block Diagram VTUN C4 R2 R1 Bands Out C1 VCC 11 2 DC/DC Converter Fout 9 B4 Test Logic 6 7 B2 B1 8 1 16 B0 Vref Operational Amplifier Buffers DTB1 Gnd Latches T13 T14 5 DTB2 Latches Fout POR SDA SCL ADD 13 I2C Bus Receiver 14 CLO Data RL 12 DTF 4 Amp In Phase Comp T10, T11 P–On Reset C3 VTUN CP 5.0 V Fref C2 Fref 6 512/1024 Shift Register 15 Bit Ref Divider 15 Latches A 3.2 or 4.0 MHz 15 Xtal Osc ADC ADC Latches B TDI 10 Preamp HF1 3 HF2 4 ÷8 Prescaler Program Divider 15 Bit Fout Latch Control DTS This device contains 3,204 active transistors. Approximate values of the external components for generation of the tuning voltage are: C1 = 1.0 nF Charge Pump filter capacitor R1 = 750 kΩ (560 kΩ minimum) Pull–up resistor C4 = 330 pF VTUN filter capacitor C2 = 47 nF, C3 = 22 nF, R2 = 39 kΩ Loop filter These component values depend on the application. 2 MOTOROLA ANALOG IC DEVICE DATA MC44871 MAXIMUM RATINGS (Maximum ratings are those values beyond which permanent damage to the device may occur. Exposure to those limits may also affect device reliability; TA = 25°C, unless otherwise noted.) Rating Pin Value Unit Power Supply Voltage (VCC) 11 6.0 V Storage Temperature – –65 to +150 °C Operating Temperature Range – –20 to +85 °C Operational Amplifier Output Voltage 1 40 V 3, 4 1.5 Vrms NPN Band Buffer ”Off” Voltage 9 10 V NPN Band Buffer ”On” Current 9 15 mA PNP Band Buffer “Off” Voltage 6, 7, 8 6.0 V PNP Band Buffer “On” Current 6, 7, 8 50 mA PNP Band Buffer – Short Circuit Duration (Note 1) 6, 7, 8 Continuous – Band Buffer Operation at 40 mA all PNP Buffers “On” 6, 7, 8 10 s RF Input Level 80 MHz to 1.3 GHz NOTES: 1. At VCC = 5.0 V and TA = –20° to +80°C one buffer “On” only. 2. ESD data available upon request. ELECTRICAL CHARACTERISTICS (Parameter Type: A–100% Tested, B–100% Correlation Tested, C–Characterized on Samples, D–Design Parameter, VCC = 5.0 V, TA = 25°C, unless otherwise specified, 750 kΩ pull–up resistor between CP [Pin2] and VTUN [Pin 1].) Pin Min Typ Max Unit Type VCC Supply Voltage Range 11 4.5 5.0 5.5 V A VCC Supply Current (All Buffers “Off”) One Buffer “On” when Open One Buffer “On” at 40 mA 11 – – – 35 40 80 45 50 90 mA A A B B PNP Band Buffer B0, B1, B2 Leakage Current when “Off” 6, 7, 8 – 0.01 1.0 µA A PNP Band Buffer B0, B1, B2 Saturation Voltage when “On” at 30 mA 6, 7, 8 – 200 500 mV B NPN Band Buffer B4 Leakage Current when “Off” 9 – 0.01 1.0 µA A NPN Band Buffer ”Off” Voltage 9 0 – 5.5 V D NPN Band Buffer B4 Saturation Voltage when “On” at 1.0 µA 9 – 50 100 mV A NPN Band Buffer B4 Voltage when ”On” @ 5.0 mA 9 – 1.2 1.6 V A Reference Oscillator Frequency Range 15 3.15 3.2 4.05 MHz D Phase Comparator 3–State Current 16 –15 0 15 nA A Phase Comparator Output Current – High Value 16 12 20 28 µA A Phase Comparator Output Current – Low Value 16 2.0 6.0 10 µA A DC–DC Converter Output Voltage, Sourcing 50 µA 2 28 31 34.5 V A DC–DC Converter Maximum Current, Output Short Circuited 2 – 200 350 µA A DC–DC Converter setting time from VCC >4.5 V to DC–DC Converter Voltage > 28 V @ Load = 750 kΩ/1.0 nF 2 – – 25 ms C Operational Amplifier Internal Reference Voltage (Vref) – 1.3 1.9 2.5 V A Operational Amplifier Input Current 16 –15 0 15 nA A Operational Amplifier DC Open Loop Gain – 100 300 – – A Operational Amplifier Gain Bandwidth Product (CL = 1.0 nF) – 0.3 – – MHz D Operational Amplifier Low Output Voltage, Sinking 50 µA 16 – 0.2 0.4 V D Oscillator – Negative Resistance 15 1.0 – – kΩ D Characteristic MOTOROLA ANALOG IC DEVICE DATA 3 MC44871 PIN FUNCTION DESCRIPTION (see Figure 1) Pin Symbol Description 1 VTUN 2 CP 3, 4 HF1, HF2 5 Gnd 6, 7, 8 B2, B1, B0 PNP Band Buffer outputs NPN Band Buffer output Operational amplifier output which provides the tuning voltage DC–DC Converter output (Charge Pump) Symmetrical HF inputs Ground 9 B4 10 ADC Three bit ADC for Automatic Frequency Tuning, readable through the bus 11 VCC Positive supply of the circuit (5.0 V) 12 ADD Chip address function 13 SDA I2C bus Data Input/Output 14 SCL I2C bus Clock 15 Xtal Crystal Oscillator (3.2 MHz or 4.0 MHz) 16 Amp In Operational amplifier input HF INPUT SENSITIVITY AND OVERLOAD CHARACTERISTICS (VCC = 5.0 V, TA = 25°C.) (See Figure 2.) Characteristics Pin Min Typ Max Unit Type DC Bias (Internal) 3, 4 – 1.6 – V A 80–150 MHz 3, 4 10 – 315 mVrms C 150–600 MHz 3, 4 5.0 – 315 mVrms C 600–950 MHz 3, 4 10 – 315 mVrms C 950–1300 MHz 3, 4 50 – 315 mVrms C Figure 2. HF Sensitivity Test Circuit Figure 3. Typical HF Sensitivity Performance (VCC = 5.0 V, Temperature = 25°C) ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ 10 Bus VCC = 5.0 V 1.0 nF 13 11 4 0 Guaranteed Sensitivity Performance RF LEVEL (dBm) Bus Controller 14 MC44871 HF1 3 Gnd 5 B0 8 B1 7 B2 6 B4 9 HF Generator 1.0 kΩ 1.0 kΩ 1.0 kΩ –30 –50 50 Ω Cable 50 Ω –20 –40 1.0 nF HF Out Gnd –10 Counter In –60 0 200 400 600 800 1000 1200 1400 FREQUENCY (MHz) NOTE: 4 1. Device is in test mode. B1, B2 are “On” and B0, B4 are “Off”. Sensitivity is level of HF generator on 50 Ω load. MOTOROLA ANALOG IC DEVICE DATA MC44871 Figure 4. Pin Circuit Schematic 10 k 50 VTUN 1 Operational amplifier output which provides the tuning voltage 2.0 k 20 V 20 V 20 V 100 32 V 6.0 kΩ CP 2 Converter output (Charge Pump) 16 Amp In Negative input of operational amplifier and phase detector charge pump output 1.5 k 20 V 1 5.0 V 20 V 2 5.0 V 6 5.0 V VCC 96 k 5.0 V 15 Xtal Crystal oscillator (3.2 MHz or 4.0 MHz) 132 k 500 1/2 VCC 2.0 k HF1 3 14 SCL Clock input (I2C bus) 20 V 96 k 1.2 … 1.8 V 2.0 k VCC Inputs to presealer 96 k 132 k 500 1/2 VCC HF2 4 20 V 13 SDA Data input/output (I2C bus) 96 k ACK VCC Gnd 5 Circuit ground 150 k 10 k 50 k 20 V VCC 5.0 V B2 6 20 V “On”/“Off” 5.0 V 12 ADD Chip Address 11 VCC Positive supply of the circuit (5.0 V) 10 k PNP Band Buffers 20 V B1 7 “On”/“Off” 20 V 200 VCC B0 8 10 ADC Three bit control for AFC 20 V 9 B4 NPN Buffer “On”/“Off” 20 V MOTOROLA ANALOG IC DEVICE DATA “On”/“Off” 5 MC44871 HIGH SPEED I2C BUS (The circuit is controlled by a I2C bus with a Serial Data [SDA], Serial Clock [SCL], Chip Address Control [ADD] inputs. The device I2C bus has a read mode [odd addresses] and a write mode [even addresses]. ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25°C, unless otherwise specified.) Characteristic Pin Symbol Min Typ Max Unit Type SDA/SCL Output Current at 0 V 13, 14 – – 10 µA A SDA/SCL Low Input Level 13, 14 VIL – – 1.5 V B SDA/SCL High Input Level 13, 14 VIH 3.0 – – V B SDA/SCL Input Current for Input Level from 0.4 V to 0.3 VCC 13, 14 –5.0 0 5.0 µA C SDA/SCL Input Level 13, 14 0 – VCC + 0.3 V D 12 –0.01 VCC – 1.1 VCC – – 10 pF C ADD Input Level SDA/SCL Capacitance 13, 14 Ci D SDA Low Output Level (sinking 3.0 mA) 13 – 0.3 1.0 V A SDA Low Output Level (sinking 15 mA) 13 – – 1.5 V C Min Typ Max Unit Type 0 – 800 kHz C Tbuf 200 – – ns C TIMING CHARACTERISTICS Characteristic Pin Symbol Bus Clock Frequency 14 Bus Free Time Between Stop and Start – Setup Time for Start Conditions – Tsu;sta 500 – – ns C Hold Time for Start Condition – Thd;sta 500 – – ns C Data Setup Time – Tsu;dat 0 – – ns C Data Hold Time – Thd;dat 0 – – ns C Setup Time for Stop Condition – Tsu;sto 500 – – ns C Hold time for Stop Condition – Thd;sto 500 – – ns C Tack;low – – 300 ns C Acknowledge Propagation Delay SDA Fall Time at 3.0 mA sink I and 130 pF Load 13 – – 50 ns C SDA Fall Time at 3.0 mA sink I and 400 pF Load 13 – – 80 ns C SDA/SCL Rise Time 13, 14 – – 300 ns C SCL Fall Time 13, 14 – – 300 ns C Pulse Width of Spikes Suppressed by the Input Filter 13,14 – – 50 ns C Tsp Timings Definition Tbuf Stop Start Stop SDA SDA SDA SCL SCL SCL Tsu;sta Thd;sto Start Chip address Tsu;dat Thd;dat Tsu;sto Thd;sta ACK Tack:low Levels Definition VCC VIH Not Defined VIL 0V 6 MOTOROLA ANALOG IC DEVICE DATA MC44871 Figure 5. High Speed I2C Compatible Bus Data Format 1 2 3 4 5 6 7 8 9 10 18 19 SCL SDA STA Chip Address ($C2) First Byte ACK Stop ACK ACK 2 or 4 Data Bytes I2C Write Mode Format and Bus Receiver The incoming information, consisting of a chip address byte followed by two or four data bytes, is treated in the I2C bus receiver. The definition of the permissible bus protocol is shown below: 1_STA 2_STA 3_STA 4_STA CA CA CA CA CO FM CO FM BA FL BA FL FM FL CO BA STO STO STO STO STA = Start Condition CA = Chip Address Byte CO = Control Information BA = Band Information FM = Frequency Information with MSB FL = Frequency Information with LSB STO = Stop Condition Figure 5 shows the five bytes of information that are needed for circuit operation: the chip address, two bytes of control and information, and two bytes of frequency information. After the chip address, two or four data bytes may be received: if three data bytes are received, the third one is MOTOROLA ANALOG IC DEVICE DATA ignored. If five or more data bytes are received, the fifth and following ones are ignored, and the last acknowledge pulse is sent at the end of the fourth data byte. The first and the third data bytes contain a function bit which allows the IC to distinguish between frequency information and control plus band information. If the function bit is logic “1”, the two following bytes contain control and band information. The first data byte, after the chip address, may be byte CO or byte FM. The two bytes of frequency information are preceeded by a logic “0”. Chip Address Even addresses are for write mode, and odd addresses are for read mode. Chip address is programmable by Pin 12 (ADD). ADD Pin 12 Address (HEX.) –0.01 VCC to 0.1 VCC C0/C1 0.2 VCC to 0.3 VCC (or Open) C2/C3 0.4 VCC to 0.7 VCC C4/C5 0.8 VCC to 1.1 VCC C6/C7 7 MC44871 The Two Permissible Protocols with Five Bytes CA_Chip Address CO_Control Information BA_Band Information FM_Frequency Information FL_Frequency Information CA_Chip Address FM_Frequency Information FL_Frequency Information CO_Control Information BA_Band Information ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 1 1 0 0 0 0/1 CA_Chip Address ADC_LO 0 ACK 1 T14 T13 T12 T11 T10 T9 T8 ACK X X X B4 X B2 B1 B0 ACK 0 N14 N13 N12 N11 N10 N9 N8 ACK N7 N6 N5 N4 N3 N2 N1 N0 ACK ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 1 1 0 0 0 0/1 0/1 0 ACK 0 N14 N13 N12 N11 N10 N9 N8 ACK N7 N6 N5 N4 N3 N2 N1 N0 ACK 1 T14 T13 T12 T11 T10 T9 T8 ACK X X X B4 X B2 B1 B0 ACK I2C Read Mode Format The incoming information consists of the chip address byte in read mode (odd address). The device then answers with an acknowledge followed by a byte containing lock and ADC information. There is no ACK pulse sent after this byte. I2C Read Format 0/1 1_STA CA ADC_LO ADC_LO = ADC and Lock information ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 1 1 0 0 0 0/1 0/1 1 ACK 1 LO X X X AD2 AD1 AD0 (no ACK) Definition of the Bits for Test and Features Bits B0, B1, B2: Control the PNP Band Buffers Bit T10, T11: Control the Reference Divider B0, B1, B2 = 0 Buffer is “Off”, Output Low T10 T11 =1 Buffer is “On”, Output High 0 0 512 0 1 1024 1 0 1024 1 1 512 Bit B4: Controls the NPN Band Buffer B4 = 0 Buffer is “Off”, Output High =1 Buffer is “On”, Output Low Divider Ratio Bit T9, T12: Control the Phase Comparator Bit T8: Controls the Operational Amplifier Output T8 T8 = 0 =1 8 Operation Operational Amplifier Normal Operation Output State of Operational Amplifier Switched Off Output Pulls High through External Resistor T9 T12 Function 0 0 Upper Source Only 0 1 Lower Source Only 1 0 Normal Operation 1 1 High Impedance MOTOROLA ANALOG IC DEVICE DATA MC44871 Bit T13: Switches the Band Buffer Output to Test Mode T13 = 0 Normal Operation =1 Test Mode: Fref Out at B2 Fby2 Out at B1 In the test mode, B2 and B1 have to be ON (B2=B1=1). Fref is the reference frequency. Fby2 is the output frequency of the programmable divider divided–by–2. Bit T14: Controls the Charge Pump Current T14 = 0 Pump Current 5.0 µA =1 Pump Current 20 µA Bit AD2, AD1, AD0: Indicate the ADC Pin Analog Level ADC Input Voltage AD2 AD1 AD0 0 to 0.18 VCC 0 0 0 0.18 to 0.34 VCC 0 0 1 0.34 to 0.5 VCC 0 1 0 0.5 to 0.66 VCC 0 1 1 0.66 to 0.82 VCC 1 0 0 0.82 to 1.0 VCC 1 0 1 Bit LO: Indicates the Status of Lock Detetector LO = 0 PLL Status Not Locked LO = 1 PLL Status Locked Figure 6. Equivalent Circuit of the Integrated PNP Band Buffers VCC Saturation Voltage 0.2 V Typical 0.5 V Max IB ISUB “On”/“Off” Out B0…B2 IB + ISUB = 5.5 mA Typical IB = Base Current ISUB = Substrate Current of PNP 30 mA (40 mA at 0 to 80°C) Figure 7. Equivalent Circuit of the Integrated NPN Band Buffer VCC = 5.0 V IB1 Out B4 OPERATING DESCRIPTION Introduction A representative block diagram and typical system application are shown in Figures 1 and 8. A discussion of the features and function of each of the internal blocks is given. The Programmable Divider The programmable divider is a presettable down counter. When it has counted to zero it takes its required division ratio out of the latches B. Latches B are loaded from latches A by means of signal TDI which is synchronous to the programmable divider output signal. Since latches A receive the data asynchronously with the programmable divider; this double latch scheme is needed to assure correct data transfer to the counter. The division ratio definition is given by: N = 16384 x N14 + 8192 x N13 + … + 4 x N2 + 2 x N1 + N0 Maximum Ratio 32767 Minimum Ratio 256 N0 … N14 are the different bits for frequency information. At power–on the whole bus receiver is reset and the programmable divider is set to a counting ratio of N = 256 or higher. The Prescaler The divide–by–8 prescaler has a preamplifier which guarantees high input sensitivity. The Phase Comparator The phase comparator is both phase and frequency sensitive and has very low output leakage current in the high impedance state. The Operational Amplifier The operational amplifier is designed for very low noise, low input bias current and high power supply rejection. The positive input is biased internally. The operational amplifier output (Pin 1) needs an external 750 kΩ pull–up resistor (560 kΩ minimum). This minimum value is defined by the charge pump output current capability. The Oscillator The oscillator uses a 3.2 or a 4.0 MHz crystal tied to ground in series with a capacitor. The crystal operates in the series resonance mode. The voltage at Pin 15 has low amplitude and low harmonic distortion. Power Dissipation The typical power dissipation of the circuit is about 200 mW (VTUN = 15 V with external pull–up of 560 kΩ, one buffer “On” at 30 mA). It is calculated with the following formula: 200 PD IB2 Protection 20...25 V IB3 1.2 V typ @ 5.0 mA + ǒ V CC ) ǒ x I CC Ǔ) V sat x I IB1 + IB2 + IB3 = 0.5 mA Typ IB = Base Current MOTOROLA ANALOG IC DEVICE DATA * V Pin2 TUN x V TUN 560 kW Ǔ Out buffer ) 5.632 x– 10155 ) (0.20 x 30) + 197 mW Example: (5 x 38) ”On”/”Off” V x 15 9 MC44871 Figure 8. Typical Tuner Application IF External Switching UHF VHF B III 8 B0 Mixer Antenna Filter B. P. Filter 1.0 nF HF1 3 Fosc Oscillator B1 6 9 B2 MC44871 ÷8 1.0 nF HF2 4 VCC 11 5.0 V 5 2 C1 VTUN 10 ADC Bus Rec 14 13 12 SCL SDA ADD Program Divider Osc & 15 Xtal Ref Div B4 CXtal 3.2/4.0 MHz Phase Comp Vref CP Gnd AGC 7 16 1 R1 R2 C4 (Note 1) C2 C3 NOTES: 1. 330 pF minimum is required for stability. 2. Approximate values of the external components for generation of the tuning voltage are: C1 = 1.0 nF Charge Pump filter capacitor R1 = 750 kΩ (560 kΩ minimum) Pull–up resistor C4 = 330 pF VTUN filter capacitor C2 = 47 nF Loop Filter C3 = 22 nF Loop Filter Loop Filter R2 = 39 kΩ These component values depend on the application. Figure 9. Typical Charge Pump Output Current 34 32 30 VOLTAGE (V) DC–DC Converter Characteristics The dc–to–dc converter block generates the 30 V supply voltage on the chip from VCC. Pin 2 only needs an external capacitor (1.0 nF) instead of an external 30 V supply. The charge pump switching frequency is taken from the oscillator. Typical charge pump output current capability at 25°C is shown in Figure 9. VCC = 5.5 V 28 26 VCC = 5.0 V 24 VCC = 4.5 V 22 20 0 20 40 60 80 100 120 CURRENT (µA) 10 MOTOROLA ANALOG IC DEVICE DATA MC44871 OUTLINE DIMENSIONS DTB SUFFIX PLASTIC PACKAGE CASE 948F–01 (TSSOP–16) ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B –U– L SECTION N–N J PIN 1 IDENT. 8 1 N 0.25 (0.010) 0.15 (0.006) T U S A –V– M N NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4 DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5 DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7 DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. F DETAIL E –W– C 0.10 (0.004) –T– SEATING PLANE H D MOTOROLA ANALOG IC DEVICE DATA G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 ––– 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 ––– 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 11 MC44871 Motorola reserves the right to make changes without further notice to any products herein. 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