MOTOROLA MC68BOOS

MCWOO
I
i
I
8-BIT MICROPROCESSING
UNIT (MPU)
The MC6800 is a monolithic 8-bit microprocessor forming the central
control function for Motorola’s M68~ family. Compatible with TTL, the
MC6B~, as with all M6800 system parts, requires only one + 5.O-volt
power supply, and no external TTL devices for bus interface.
The MC6800 is capable of addressing 64K bytes of memory with its
16-bit address lines. The 8-bit data bus is bidirectional as well as threestate, making direct memory addressing and multiprocessing applications realizable.
● 8-Bit Parallel Processing
● Bidirectional
.
Data Bus
16-Bit Address Bus – WK Bytes of Addressing
● 72 Instructions
.
– Variable Length
Seven Addressing Modes – Direct, Relative, Immediate,
Extended, Implied and Accumulator
Indexed,
,>:
,,*!.
“)!.IC,[
. Vectored Restart
.}. ‘.*$
,,2:+.(
~
‘~”‘%1
*F.
. Maskable Interrupt Vector
~..!’.
. Separate Non-Maskable Interrupt – Internal Registers Saved i#’’::$$
, +,
~,
,)i~.,,,!,.
. ,{).
.Y,:>,
-,,,.
Stack
.......
*: ,.. ‘is
. Six Internal Registers – Two Accumulators, Index Regist~#?Y’:Y’
Program Counter, Stack Pointer and Condition Code [email protected]~
● Direct Memory Addressing (D MA) and Multiple [email protected]$esso’r
.:;.!,.,,
.+
Capability
,“,., .,>.s,-.
,1’.‘ -->,,:,+
~..,
*V\>>>.,
**.
● Simplified Clocking Characteristics
‘~:?iii
*
...*”,+<
,,:+,..,
‘.~;:),t.{t,.
. Clock Rates as High as 2.0 MHz
,~>
*:;.>
● Simple Bus Interface Without TTL
,$~~~~i$~’
● Variable Length Stack
● Halt and Single Instruction
Executlo*k$~~$bility
,.*. .\
~~$$~‘;:$*Y*:,F
. .., .it~
,.,.$,.>.
‘i,\,.*>
& ‘~~$
,{, ..,.
,:&f*,>~<~’
,>$ $$:$
.~~
... ~:
~+~,
\*:,.:
,*..
.+~’‘
\,\<\!
;..
., \.J.*
.+,t~
..
,,,~~&[email protected]’DERING
w<, .-1. $,)
Package Type ‘$:,~~equency (MHz)
ceramic+,,:,~f~ “
1.0
L s~~i~ ~ “
1.0
@y*+(k:::
Ti. ... ,
~rdio
.—
! –!–
s suffix
Plastic
P Suffix
2.0
1.0
1.0
1.5
1.5
2.0
1.0
1.0
1.5
1.5
2.0
to
70°c
PIN ASSIGNMENT
Vss[
10
HALT[
2
KQ [ 4
VMA [ 5
m[
6
BA [ 7
Temperature
Ooc to 70°c
–40°C
to 85°C
O“c to 70°c
–40°C to 85°C
O“c to 70°c
–40°C to 85°C
O“c to 70°c
O“c to 70°c
–40°C
to 85°C
O“c to 70°c
– 40°C to 85°C
Ooc to 70°c
CERAMIC PACKAGE
CASE 715
@l [ 3
INFORMATION
Ooc
SUFFIX
uu. -
Order Number
MC6800L
MC~~CL
I
MC68BOOL
MC68WS
[email protected]
Mc68Ams
Mc68Amcs
MC68BOOS
MC6800P
MC6800C P
MC68AOOP
MC68AOOCP
MC68BOOP
Vccc
8
AC [ 9
38 ]N. C.
37
342
36 ]DBE
35 ]N, C.
34 ]Rl~
33 ] DO
32 ]Dl
Al [ 10
31 ] D2
30 ] D3
A3[
12
29 ] D4
A4[
13
28 ] D5
A5 [ 14
27 ] D6
A6 [ 15
26 ] D7
A7 [ 16
25 ]A15
A8 [ 17
24 ]A14
A9 [ 16
23 JA13
A1O c
19
MOTOROLA INC., lW
——
JRESET
39 ]TSC
A2 [ 11
Al 1q 20
-——— -—
~
22 ]A12
21 Jvss
DS9471-F
MAXIMUM
M C6~C
RATINGS
THERMAL
I
M C68A~C
Storage Temperature
Range
I
I
Tsta
-40to
l-55to
+85
I
+150
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electrical fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum-rated
voltages
to this highimpedance circuit. Reliability of operation is
I
I “C I
RESISTANCE
Rating
Plastic Package
Cerdip Package
Ceramic Packaqe
Symbol
Value
Unit
eJ A
Im
60
m
“Clw
POWER
The average
chip-junction
TJ=TA+(PDo
temperature,
CONSIDERATIONS
TJ, in ‘C can be obtained
from:
OJA)
(1)
Where:
TA = Ambient
Temperature,
‘C
,.,\\wy\~.::$,i~
;F’s~;
.,$ ‘f:?ki,,
, ,,$3
~..,..,.
.
PD=PINT+PpORT
::i~.’.
~i.:.,.
.<,,..,,
PINT= ICC x Vcc, Watts – Chip Internal Power
1*+:
,..,
.,+*
PpORT = Port Power Dissipation, Watts – User [email protected]:$,,,
. ,.,. ..,.
OJA=
Package
Thermal
Resistance,
Junction-to-Ambient,
“C/W
For most applications PPORT< PINT and can be neglected. P$o~~
may become significant if the device is configured to
%i*\:,+,:,
,,**F
drive Darlington bases or sink LED loads.
..,,,.,,\+,*
An approximate relationship between PD and TJ (if PpO~~$YWbglected)
is:
,.>,,,.
PD= K- (TJ+2730C)
(2)
.,J:> ~,:*
,J,t::i,}
Solving equations 1 and 2 for K gives:
.,(*;{:\
K= PD. (TA+2730C)+0JA*
PD2
.. ‘}~. $
(3)
,’,:::
/:’\,.*:..*>.\\
Where K is a constant pertaining to the parti~$~$~~~it. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K the va~~~~:Qft,@Dand TJ can be obtained
.,,
\\*‘:*,.
value of TA,
,>f:?>,{,,,>i,
,t
.~\ ~“,’.,,\<..
‘~$,\
.,!.{w
‘-.<~:,.
~~y
>
V’i, .\\
by solving equations(1)
.-
and (2) iteratively for any
,::,2.CF i?~jt:,?.
.
.},.
DC ELECTRICAL
CHARACTERl~%~C~(Vcc=
,..:$:,?,$
,,,..,,.,
>
5,0 Vdc, +5%,
Vss = O, TA= TL to TH unless otherwise noted)
Svmkl
“ .&i,t.
~~
@aracteriatic
\t$.<,%,\.
“i’;,,L,, ‘$,
,;>? “a?+$,}.,,’~
~.,t...t,
Input Low Voltage ~w”$&~$,$#
.,. , ‘<$
.,~’tat;.{,,,
\ .:,,
*,,.;’.
Input [email protected]:$~&f$n~
(Vin =Ot&@&~~, Vcc= Max)
V, Vcc=o V to 5.25 V)
(Vin ~&!0,[email protected]
Input High Voltage
Logic
41,42
–
–
—
Logic
@l, #2
D&D7
AO-A15, Rlw
[email protected]@akage
Current
f~#’@&.4 to 2.4 V, Vcc = Max)
~w~?
VSS–0,3
VSS–0,3
Logic
~1 ,42
VSS+O.8
VSS+O.4
2.5
1,0
,
v
PA
[
1
I
High Voltage
‘$$lLoad= - 205tiA, Vcc= MinJ
“(lLoad= – 1454A, VCC= Min)
(lLoad= – 100KA, VCC= Min)
A&A15,
R/~,
DO-D7
VMA
BA
VSS+2.4
VSS+2.4
VSS+2.41
VOH
Output Low Voltage (lLoad = 1.6 mA, VCC = Min)
VOL
—
Internal Power Dissipation
PINT
—
Capacitance
(Vin=O, TA=250C,
(Measured at TA = TL)
–
–
–
! —
I
0.5
I
f=l.O
MHz)
~1
42
DGD7
Logic Inputs
AO-A15, Rl~,
VMA
—
Cin
—
—
Cout
—
—
Semjconducfor
2
Ivss+o
]
1,0
I
25
45
10
6.5
—
—
(M) MOTOROLA
I
–
–
–
Products Inc.
v
I
w
,4
w
I
35
70
12.5
10
12
I
v
pF
pF
I
CLOCK TIMING (Vcc= 5,0 V, *5%, VSS=O,
TA=TL
to TH unless otherwise
noted)
Characteristic
Frequency of Operation
Cycle Time (Figure 1)
Clock Pulse Width
(Measured at VCC– 0.6 V)
Symbol
Min
Typ
Max
Unit
MC~
MC68AO0
MCWBW
f
0.1
0.1
0.1
–
–
–
1.0
1.5
2.0
MHz
M Cm
M [email protected]
MC~BW
tcyc
1.000
O.m
O.m
–
—
ps
–
10
10
10
w
Za
180
–
–
–
90
600
w
—
–
–
–
—
@l, @2 – MCmN
@l, @2 – MC6BAO0
@l, @2 – MC68BO0
Total 01 and 42 Up Time
pW~H
MCH
M C~A~
MC6BBW
t“t
tr, tf ~
Rise and Fall Time (Measured between VSS +0.4 and VCC– O.6)
Delay Time or Clock Separation (Figure 1)
(Measured at VOV=VSS+O.6
[email protected]=tf=l~
ns)
(Measured at VOV= VSS + 1.0 [email protected]=tf S35 ns}
td+
+
td
‘d+
,,
. ..>.,,,.
.~t~ 4:.
*T,
,+1
- . $~~+’<.
~a..~+,k~
[email protected]&$iF, ~~’
~\+,\ -i
*,. .....:
,~.;.,+
-.~:$,
’-- ‘:.$
Address DelaV
..,,.
~,t~,,,:y
,
C=90pF
,,,,
**3::,:>
C=30 pF
,,..,
..
>
Peripheral Read Access ~fi&~f:
tacc = tut – (tAD +~~~$~.
Data Setup Tim$,:( ~~~?:
Input Data [email protected]
Addressf&,&,Jime
[email protected]
Data ~lav
(Address, R/~,
VMA)
for DBE Input
Time (Write)
Processor Controls
Processor Control Setup Time
Processor Control Rise and Fall Time
8US Available DelaV
Hi-Z Enable
Hi-Z DelaV
Data Bus Enable Down Time During @l Up Time
Data Bus Enable Rise and Fall Times
—
m
M070ROLA
<
MC6BBO0
MC8BAO0
Unit
Typ
Max
Min
Typ
Max
Min
Typ
Max
tA D
–
—
–
—
270
2W
–
–
–
–
1BO
165
–
–
–
–
150
135
ns
tacc
605
–
—
m
–
—
2W
–
—
ns
tH
Output [email protected] ‘~l,#Time
ns
Min
tDSR
‘
,*!.
‘*{,1,
.!>.,:..,.,.:
~:~,
Y “~:..
d *“:*’:*L
‘$$:fi+s:~
1,
,,,,
,,fj:$’,i~ ,’;?
,..~’
%$*t&
,>+1,:
,,
–$; y< “$,~
—.$:~,
?\:i..
$\*.’,
o
o
MC~
Symbol
–
–
ns
b,’’”
. ,,
,,,.
vl~c*
9m
9m
9W
—
lm
–
–
60
–
–
40
–
–
ns
10
–
–
10
–
–
10
–
–
ns
tH
10
25
–
10
25
–
10
25
–
ns
tA H
30
50
–
30
a
–
m
50
–
ns
tEH
450
–
–
280
–
–
220
–
–
ns
tDDW
–
–
225
–
–
2W
–
–
160
ns
tpcs
tpcr, tpcf
tBA
tTSE
tTSD
tDBE
2m
–
–
o
–
Iw
–
–
–
–
–
–
–
–
–
Im
29
40
270
–
25
140
–
–
0
–
120
–
–
–
–
–
–
–
–
–
100
165
40
270
–
25
110
–
–
0
–
75
–
–
–
–
–
–
–
–
–
100
135
m
220
–
25
tDBEr, tDBEf
Semiconductor
3
Products Inc.
ns
1
FIGURE 2 – READ DATA FROM MEMORY OR PERIPHERALS
Start
of
/
Cycle
+
‘VIHC
@l
~
Data
Not
7
0.4 v
0.4 v
Valid
~
Start of Cvcle
‘):.,
2.4
[
V
Data
From
MPU
0.4 v
I
k\\\\\\Y
Data
Not
ktDDw+
Valid
NOTES:
1. Voltage levels shown are VLSO.4,
2. Measurement
—
VH> 2.4 V, unless otherwise
points shown are 0.8 V and 2.0 V, unless otherwise
MOTOROLA
@
specified
noted
Semiconductor
4
Produck
Inc.
FIGURE 4 – TYPICAL DATA BUS OUTPUT DELAY
versus CAPACITIVE LOADING (TDDw)
600
I OH
‘lo
=-205A
FIGURE 5 – TYPICAL READ/WRITE, VMA, AND ADDRESS
OUTPUT DELAY versus CAPACITIVE LOADING (TAD)
600
max @ 2.4 V
[email protected]
500 - Vcc = 5.0v
1A= 25°C
~
=
u
z
F
>
~
400
:
200
300
/
/
/
100
/
~
‘
[email protected]
-VCC=5.OV
TA = 25°C
500
-
lo H=-145*[email protected]
‘lo
z
u
z
400
~
~
u
0
300
-$,:,
200
~
/
100
CL includes stray capacitance
0’
0
100
200
CL, LOAO
300
400
CAPACITANCE
(pF)
500
MOTOROLA
@
CL includes stray capacitance
o
600
0
100
Semiconductor
5
2og~+~~ ,i$oo
Products Inc.
400
500
600
I
FIGURE
A15
A14
A13
7 –
A12
All
=PANDED
A1O
BLOCK
A9
DIAGRAM
A7
A8
A6
A5
A4
A3
A2
Al
AO
Clock, @l
Clock, @2
37
RESET
40
Interrupt
6
HALT
2
Instruction
Interrupt
Request
4
Decode
Three-State
Control
39
Non-Maskable
a
Data Bus Enable
3
and
Control
36+
Bus Available
Valid Memory
Read/Wtite,
Address
Rl~
34+
1
Instruction
Register
‘*”
..l.t\,,
.—
!*
.—
MOTOROLA
@
Semiconductor
Products Inc.
6
.—
MPU SIGNAL DESCRIPTION
Proper
operation
of the MPU requires
that certain
and timing signals be provided to accomplish
tions and that other signal lines be monitored
the state
control
Read (high)
specific functo determine
of the processor.
Clocks Phase One and Phase Two
are used for a two-phase
(o1, 42)
non-overlapping
the VCC voltage level.
Figure 1 shows the microprocessor
–
Two
clock that
clocks.
output
90 pF.
pins
of clock
Address
at the system
Bus (AOA15)
dress bus. The outputs
frequency
– Sixteen
are specified
MPU
capable
Data Bus (DO-D7)
It is bidirectional,
bus to go into the three-state
–
of
mode.
Eight pins are used for the data bus.
transferring
data to and from
the memory
and peripheral devices. It also has three-state
output buffer$
capable of driving one standard TTL load and 130 pF. D,a~$,
Bus is placed
in the three-state
which
when
with
three-state
control
signal for the M PU data ~$~l:~yd
will
enable the bus drivers when in the high st~:&[email protected] Input is
TTL compatible;
however
in normal op~,atib~~$twould
be
that another
device
contr$PtR~&ata
write, the DB E down ,~,~~ @n be decreased, as shown in
Figure 3 (DBE#@2\R:~~e~inimum
down time for DBE is
Bus Ay~i$~l~.(bA)
–
The
Bus Available
nor-
the peripherals
and memory
devices
wether
output
the MPU
MOTOROLA
@
Ioa&?iqnd
.:}
reset
seqe~$~.
During
the
reset
se-
accept
a false write
during
this
time
(such
as
RAM) must be disabled until VMA is forced
cycles. RESET can go high asynchronously
clock
any time after
is shown
in Figure
the eighth
cycle.
8. The maximum
rise and
time tpcs
is met.
Request
(~Q)
–
This
level sensitive
input
re-
dition Code Register is not set, the machine will begin an interrupt sequence. The Index Register, Program Counter, Accumulators,
and Condition
Code Register are stored away on
the stack. Next, the MPU will respond to the interrupt
request by setting the interrupt
mask bit high so that no further
interrupts
may occur. At the end of the cycle, a 16-bit ad-
of a maskable (mask bit I = O) or nonmaskable
interrupt,
This
output
is capable
of driving
one standard
TTL load and
30 pF. If TSC is in the high state, Bus Available will be low,
– This TTL compatible
TTL
quests that an interrupt
sequence
be generated
within the
machine.
The processor will wait until it completes
the current instruction
that is being executed
before it recognizes
the request. At that time, if the interrupt
mask bit in the Con-
state as a result of the execution
of a WAIT instruction.
At
such time, all three-state
output
drivers will go to their off
state and other outputs to their normally inactive level. The
processor is removed from the WAIT state by the occurrence
(R/~)
the
the system
Interrupt
will
mally ~%~ ~}$’low
state; when activated,
it will go to the
..,*.’:* Y
high.?ata~:+indicating
that the microprocessor
has stopped
* “’“’*’l+
and @,@tfhe address bus is available.
This will occur if the
HALT~ne
is in the low state or the processor is in the WAIT
Read/Write
could
if setup
to E, data
signal
standard
begin on the next cycle as shown. The RESET control line
may also be used to reinitialize the MPU system at any time
during its operation.
This is accomplished
by pulsing RESET
low for the duration
of a minimum
of three complete
42
cycles. The RESET pulse can be completely
asynchronous
with the MPU system clock and will be recognized during 42
bus, such as in
respect
one
beginning
of..,$~b.:wet
routine.
During
the reset
~.\J
~t.~,,~y..
the interrupt
~s~
bit is set and must be cleared
RESET timing
Direct Memory Access (DMA)[email protected]~ions,
DBE should be
.>.:,:,.,,
, ~t~
,x.
held low.
If additional
data setup+p[+ho~d~?me is required on an MPU
tDB E as shown, ~~~.s}~ting
D B E with
setup or hold t~,[email protected]#
be increased.
\\\$.
;>L:.,.?J
~,
drivina
fall transition
times are specified by tpcr and tpcf.
If RESET
is high at tpcs
(processor control setup time), as shown in
Figure 8, in any given cycle then the restart sequence will
driven by the phase two clock. Durin&@n~~,K~
read cycle,
the data bus drivers will be disabled,’~~t~nal
ly. When it is
desired
begin
battery-backed
low after eight
DBE is Io#t\,t w~$.
,{’.y...:>.:>
,,:!:.?..
.+,.‘+:+”
‘ ‘$,. ?
– This level sensitive i~[~t~$sthe
Data Bus Enable (DBE)
mode
of
under program c~~ol,
before the M PU can be interrupted
by
(assuming
a minimum of8 clock
IRQ. While ‘K%Jk’’low
cycles have ~Jcc~$r8d) the MPU output signals will be in the
followinqj$&MVMA=
low, BA= low, Data Bus= high impeda~~e,>~~~=
high (read state), and the Address Bus will
con$&8 the ‘reset address FFFE. Figure 8 illustrates a power
?}4
&“[email protected]~nce
using the RESET control line. After the power
~i. ~,[email protected]
reaches 4.75 V, a minimum of eight clock cycles are
?$:jlj$~qtiired for the processor to stabilize in preparation
for
‘~trestarting.
During these eight cycles, VMA will be in an in.lp~
determinate
state so any devices that are enabled by VMA
driving one standard TTL load and 90 pF. When the output is
turned off, it is essentially
an open circuit. This permits the
MPU to be used in DMA applications.
Putting TSC in its high
state forces the Address
is capable
to
to the
routine,
rate.
bus drivers
state of
quence, the contents of th,~?%f$wb
locations
(FFFE, FFFF)
in memory will be [email protected]{~~&,Jtie Program Counter to point
pins are used for the ad-
are three-state
standby
~+,r+i~
width high time). To guarantee the required
the peripherals,
the clock up time, tut, is
separation,
td, is measured at a maximum
(overlap voltage), This allows for a multitude
variations
The normal
RESET – The RESET input is used to rese~&}N~&~rt
the
M PU from a power down condition
resulti~~,jf~%
a power
failure or initial start-up of the processor,+:[email protected]%~i&el sensitive
at any time
input can also be used to reinitialize t,$~~~~~ne
.)’ k%}?*
after start-up.
:t:;l,\ \
If a high level is detected
in th~ Inpw; this will signal the
The high level
@l and @2 high level pulse widths
by PW~H (pulse
access time for
specified.
Clock
voltage of VOV
(low) state,
runs at
is specified
at VIHC and the low level is specified
at VILC.
The allowable
clock frequency
is specified by f (frequency).
The minimum
or Wrile
this signal is Read (high). Three-State
Control going high will
turn Read/Write
to the off (high impedance)
state. Also,
when the processor is halted, it will be in the off state. This
dress will be loaded that points
is located in memory locations
to a vectoring
address which
FFF8 and FFF9. An address
loaded at these locations causes the MPU to branch to an interrupt
routine
in memory.
Interrupt
timing
is shown
in
Figure 9.
signals
is in a
Semiconductor
7
Products Inc.
time [email protected] without destroying data within the M PU. TSC
then can be used in a short Direct Memory Access (DMA)
application.
Figure 12 shows the effect of TSC on the MPU. TSC must
have its transitions at tTSE (three-state enable) while holding
+1 high and +2 low as shown, The Address Bus and Rl~
line will reach the high-impedance state at tTSD (three-state
Non-Maskable Interrupt (NMI) and Wait for Interrupt
delay), with VMA being forced low. In this exampl$~%the
Data Bus is also in the high-impedance state while,,~;[email protected]&(WAI) – The MCWCO is capable of handling two types of interrupts: maskable (~)
as described earlier, and noning held low since DBE= 42. At this point in [email protected]~,$,’)~MA
maskable (~)
which is an edge sensitive input. IRQ is
transfer could occur on cycles #3 and #4. -+$~SC
is
maskable by the interrupt mask in the condition code register
returned low, the MPU Address and R/~lfl&/&Mrn
to the
while ~
is not maskable. The handling of these interrupts
bus. Because it is too late in cycle #5 to,,~cp~,~emory,
this
cycle is dead and used for synchroni$~~w.i$~rogram
execuby the M PU is the same except that each has its own vector
.*’ .!~:l..>;.
tion resumes in cycle #6.
address. The behavior of the MPU when interrupted is
.’~\k:\,
.:~:.3,
~.:~’
shown in Figure 9 which details the MPU response to an in‘1~$
~
Valid Memory Address (VM&,~~$ This output indicates to
terruDt while the MPU is executina the control ~roaram. The
peripheral devices that [email protected]&[email protected]~a~?daddress on the address
interrupt shown could be either ~Q or ~
and ca~ be asynbus. In normal operation~<gti~, signal should be utilized for
chronous with respect to +2. The interrupt is shown going
enabling peripheral i~tf~f~w’
low at time tpcs in cycle #1 which precedes the first cycle of
.y;.%,,a:.~+~b
~ such as the PIA and ACiA.
This signal is not [email protected]~te.
One standard TTL load and
an instruction (OP code fetch). This instruction is not ex90 pF may be d~&ly dfiven by this active high signal.
ecuted but instead the Program Counter (PC), Index
~,.,,+$s:
.:>
Register (IX), Accumulators
(ACCX), and the Condition
..?XL?*
>’.~~’.
Code Register (CCR) are pushed onto the stack,
HALT - ~h”~$’~%is level sensitive input is in the low state,
The Interrupt Mask bit is set to prevent further interrupts.
all activik~~o?~~e machine will be halted. This input is level
-.:<.
~.~~
The address of the interrupt service routine is then fetched
sensitj,ve. +i.,,
fram FFFC. FFFD for an NMI interruDt and from FFF8, FFF9
l.ti~~
line provides an input to the MPU to allow confor an ~’interrupt.
Upon complet~on of the interrupt ser{W,gf”Program execution by an outside source. If HALT is
vice routine, the execution of RTI will pull the PC, IX, ACCX,
[email protected] the MPU will execute the instructions; if it is low, the
and CCR off the stack; the Interrupt Mask bit is restored to
“*~PU will go to a halted or idle mode. A response signal, Bus
‘~+,’tv:a,::
its condition prior to Interrupts (see Figure 10).
“’t~, Available (BA) provides an indication of the current MPU
Figure 11 is a similar interrupt sequence, except in this
status. When BA is low, the MPU is in the process of ex$’+
case, a WAIT instruction has been executed in prepara$$~
ecuting the control program; if BA is high, the MPU has
for the interrupt. This technique speeds up the M&U’”~
halted and all internal activity has stopped,
response to the interrupt because the stacking of tbe~~~$.W,
When BA is high, the Address Bus, Data Bus, and Rl~
ACCX, and the CCR is already done. While [email protected]
iS
line will be in a high-impedance state, effectively removing
waiting for the interrupt, Bus Available wilP&@+{Q?~h inthe MPU from the system bus. VMA is forced low so that the
dicating the following states of the control lj~~Y~MA is low,
floating system bus will not activate any device on the bus
and the Address Bus, R/~and
Data B~~ ~~, ~{ in the high
that is enabled by VMA.
impedance state. After the interrupt w-$*
IS serviced as
While the MPU is halted, all program activity is stopped,
,.\, .<
previously described.
and if either an ~
or IRQ interrupt occurs, it will be latched
},it?~
,,,::
A 3-10 kQ external resistor to V&*’&~&tild be used for wireinto the MPU and acted on as soon as the MPU is taken out
OR and optimum control of igi~r~w~t~.
of the halted mode. If a RESET command occurs while the
,*+
$
..,,.
MPU is halted, the following states occur: VMA= low,
.. “$,’
MEMORY [email protected] IMRRUPT VECTORS
BA= low, Data Bus= high impedance, Rl~= high (read
state),
and the Address Bus will contain address FFFE as
~:.$ ‘*, ,,$’
Vetior
,.., ;. ‘~’
long
as
RESET is low, As soon as the RESET line goes high,
Description
,,f*y
MS
the MPU will go to locations FFFE and FFFF for the address
of the reset routine.
Reset
FFFE :,* E=3
Figure 13 shows the timing relationships involved when
Non-Maskable Interrupt
FFFQ”J” %FFD
halting the MPU. The instruction illustrated is a one byte, 2
Software Interrupt
E&.~\x}i,,$ FFFB
cycle instruction such as CLRA. When HALT goes low, the
Interrupt Request
—
‘$,~aip” ~
MPU will halt after completing execution of the current instruction. The transition of HALT must occur tpcs before
the trailing edge of @l of the last cycle of an instruction
Three-State Control (TSC) – When the level sensitive
(point A of Figure 13). HALT must not go low any time later
Three-State Control (TSC) line is a logic “l”, the Address
than the minmum tpcs specified.
Bus and the Rim line are placed in a high-impedance state.
The fetch of the OP code by the M PU is the first cycle of
VMA and BA are forced low when TSC= “1” to prevent
the
instruction. If HALT had not been low at Point A but
false reads or writes on any device enabled by VMA. It is
went low during 42 of that cycle, the MPU would have
necessary to delay program execution while TSC is held
halted after completion of the following instruction. BA will
high. This is done by insuring that no transitions of 41 (or 42)
go high by time tBA (bus available delay time) after the last
occur during this period. (Logic levels of the clacks are irreleinstruction cycle. At this point in time, VMA is low and R/~,
vant so long as they do not change). Since the MPU is a
Address Bus, and the Data Bus are in the high-impedance
dynamic device, the 01 clock can be stopped for a maximum
state.
The HALT line must be in the high state for interrupts to
be serviced. Interrupts will be latched internally while HALT
is low.
The ~
has a high-impedance puilup device internal to
the chip; however, a 3 kQ external resistor to VCC should be
used for wire-OR and optimum control of interrupts.
MOTOROLA
@
Semiconductor
9
Products Inc.
1
To debug programs it is advantageous
to step through
programs instruction byinstruction .To do this, HALT must
be brought high for one MPU cycle and then returned low as
Iinesare back on the bus. Asingle byte, 2 cycle instruction
such as LSRisused
forth isexample also. During the first cycle, the instruction Y is fetched from address M+l.
BA
shown at point B of Figure 13. Again, the transitions of
HALT must occur tpcs before the trailing edge of $1. BA
returns high
dicating the
three cycles,
increased by
will go low at tBA after the leading edge of the next @l, indicating
that the Address
Bus, Data
Bus, VMA
and Rl~
FIGURE
f
10 –
MPU
at tBA on the last cycle of the instruction inMPU is off the bus. If instruction Y had been
the width of the BA low time would have been
one cycle.
FLOWCHART
Y
1 +BA
3
Y
●
I
1
0
A
1. Reset is recognized at any
2
3
m
MOTOROLA
position in the flowchart.
Instructions which affect the l-Bit act upon a on~bh buffer register,
“lTMP.” This has the effect of delaying any CLEARING of the l-Bit one
clock time. Setting the l-Bit, however, is not delayed.
See Tables 6-11 for details of Instruction
Semiconductor
10
Execution.
Products Inc.
FIGURE 11 – WAIT INSTRUCTION
I
Address
Bus
Cycle
#1
I
*
*
I
#4
I
*
x
x
x
Instruction
&
x
x
#7
I
x
I
#8
I
*
TIMING
I
#1 o
I
n
n+l
I
n+2
New PC
Address
x
R/R
VMA
1[
\
Interrupt
First
Inst
of Interrupt
IRQ
or
Routine
m
Data
x
Bus
x
x
Wait
Pc
0-7
x
PC 8-15
x
I 0-7
x
I B-15
x
x
ACCA
ACCB
New
[[
I nst
BA
A
Note:
Midrange
high
waveform
iMDedanCe
indicates
-TBA
state.
FIGURE 12..+$tikE-STATE
CONTROL TIMING
x
x
x
PC 8-15
Address
New
PC O-7
Address
x
1
FIGURE13 – HALT AND SINGLE INSTRUCTION =ECUTION FOR SYSTEM DEBUG
Instruction
m
Instruction
Instruction
Fetch
Execute
@l
@z
m
BA
x
VMA
XY
x
R/%
Addr
Bus
/
{1
))
XY
Exwute
Fetch
Address
\
M
x
Data
Bus
-.
.,
, :.~~>),
The M PU has three 16-bit registers and thra-$,8~*@
registers available for use by the programmer (FJ$’@[email protected]
*.Y -I:,.,~~>
,$
FIGURE14 – PROGRAMMING MODEL OF
THE MICROPROCESSINGUNIT
Program Counter – The program count~$&~?:’&t&o byte
(16 bits) register that points to the curre~~,”w~$m
address.
,+$,‘~,i
Stack Pointer – The stack pon~*i~%,;&o
byte register
that contains the address of the ne&,,a$ilable location in an
external push-down/pop-up
st$~~$~fs stack is normally a
random access Read/Write,,,%b*~.#’’that
may have any location (address) that is [email protected]~t. In those applications that
require storage of [email protected]~atidB’ In the stack when power is
lost, the stack muskl~~~~volatile.
,.,,,
$:.,,,
~?,
{.. .. .
Pc
B
Register
Program
15
Counter
7
Pointer
w
INZVC
II -
code register indicates the results of an Arithmetic Logic Unit operation:
Negative (N), Zero (Z), Overflow (V), Carry from bit 7 (C),
and half carry from bit 3 (H). These bits of the Condition
Code Register are used as testable conditions for the conditional branch instructions. Bit 4 is the interrupt mask bit (l).
The unused bits of the Condition Code Register (b6 and b7)
are ones.
r
Semiconductor
(From
Bit 7)
Overflow
zero
;:::t
Half
12
Code
Registar
Carrv
– The condition
MOTOROLA
Stack
o
Condition
llt
m
The MPU contains two 8-bit accwuktprs
that are used to hold operands and results from
a~~{~~metic logic unit (ALU).
...
Code Register
0
SP
–
@
Accumulator
..
....\..:+L.\:!!i,
Condition
A
Index
Index RWis~~~~~$%e index register is a two byte register
that is used x~i$~$?data or a sixteen bit memory address for
the lnde&& &&e of memory addressing.
;8
,*.:,.
:$.,,,
Aq~$#~ators
Accumulator
Products Inc.
Carrv
(From
Bit 3)
—.
MPU INSTRUCTION
The MC~
instructions are described in detail in the
MWW Programming Manual. This Section will provide a
brief introduction
and discuss their use in developing
MC~
control programs. The MC66W has a set of 72 different executable source instructions. Included are binary
and decimal arithmetic, logical, shift, rotate, load, store,
conditional or unconditional
branch, interrupt and stack
manipulation instructions.
Each of the 72 executable instructions of the source
language assembles into 1 to 3 bytes of machine code. The
number of bytes depends on the particular instruction and
on the addressing mode. (The addressing modes which are
available for use with the various executive instructions are
discussed later, )
The coding of the first (or only) byte corresponding to an
executable instruction is sufficient to identify the instruction
and the addressing mode. The hexadecimal equivalents of
the binary codes, which result from the translation of the 72
instructions in all valid modes of addressing, are shown in
Table 1. There are 197 valid machine codes, 59 of the 256
possible codes being unassigned.
30
31
12
3A
3B
3C
?D
3E
3F
10
11
12
13
14
15
16
17
18
19
1A
IB
Ic
ID
IE
IF
20
21
22
23
24
25
2a
27
2a
29
NOP
TAP
TPA
INX
DEX
CLV
SEV
CLC
SEC
CLI
SEI
SBA
CBA
TAB
TBA
DAA
ABA
BRA
REL
BHI
REL
REL
REk
40
41
42
43
44
45
4a
47
48
49
4A
40
4C
4D
4E
4F
50
51
52
53
54
55
5a
57
5a
59
5A
5B
5C
5D
5E
5F
ao
A
COM
LSR
A
A
ROR
ASR
ASL
ROL
DEC
A
A
A
A
A
INC
TST
A
A
CLR
NEG
A
B
COM
LSR
B
B
ROR
ASR
ASL
ROL
DEC
B
B
B.
80
81
82
83
84
85
88
87
8a
a9
8A
aB
ac
8D
8E
8F
90
91
92
93
QA
INC
TST
IND
IND
INO
IND
IND
(ND
PUL
PUL
DES
TXS
PSH
PSH
.
RTS
“
RTI
“
.
WAI
Swl
A
B
A
B
aE
6F
70
71
72
73
74
75
7a
77
78
79
7A
7B
7C
7D
7E
7F
INC
TST
JMP
CLR
N EG
.
.
COM
LSR
.
ROR
ASR
ASL
ROL
DEC
.
INC
TST
JMP
CLR
m
SUB
CMP
SBC
A
A
A
IMM
IMM
IMM
AND
BIT
LDA
A
A
A
IMM
IMM
IMM
EOR
A
IMM
INO
IND
IND
IND
EXT
EXT
EX1
EXT
EX1
EX1
EX1
EX1
EX1
EX1
EX1
EX1
9D
9E
9F
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
Ba
B7
Ba
B9
BA
BB
BC
BD
BE
BF
When an instruction translates into two or three bytes of
code, the second byte, or the second and third bytes contain(s) an operand, an address, or information from which an
address is obtained during execution.
Microprocessor instructions are often divided into three
general classifications:
(1) memory reference, so called
because they operate on specific memory locations; (2)
operating instructions
that function without
needing a
memory reference; (3) 1/0 instructions for transferring data
between the microprocessor and peripheral devices. $+cl+
In many instances, the M Cm
performs the sarn”$*ation on both its internal accumulators and ~#[email protected]
memory locations.
In addition,
the MC%:,[email protected]
adapters (PIA and ACIA) allow the MPU t~$~~~k~peripheral
devices exactly like other memory [email protected][email protected]#nce, no 1/0
instructions as such are required. Beca&[email protected]
features,
‘$,?~
other classifications are more [email protected]~&~~b~
introducing the
MC66WS instruction set: (1) ,$cc’%hlator
and memory
operations; (2) Program cont~~t~perations;
(3) Condition
~ i~~~
Code Register operations, ,,,~~~~, %
~~-~
,,, ,.,,\.,
, ,\<!\{
.i$’‘~,,
~:li
‘*+\.,
~~i,
.t;~..
co
cl
C2
C3
C4
C5
ca
C7
C8
Notes:
B
A
A
A
A
A
IND
INO
ac
ao
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
NEG
SET
LDS
STS
sua
CMP
SBC
A
A
A
AND
BIT
LDA
STA
EOR
ADC
ORA
ADD
CPX
JSR
LDS
STS
SUB
CMP
SBC
A
A
A
A
A
A
A
A
AND
BIT
LDA
STA
EOR
ADC
ORA
ADD
CPX
JSR
LOS
STS
A
A
A
A
A
A
A
A
MOTOROLA
A
A
A
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
IND
[ND
IND
IND
IND
IND
IND
IND
lND
IND
IND
IND
IND
IND
IND
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
CE
CF
DO
01
D2
D3
D4
D5
D6
D7
Da
D9
DA
DB
DC
DD
DE
DF
EO
El
E2
E3
E4
E5
Ea
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
LDX
.
SUB
CMP
SBC
“
AND
BIT
LDA
STA
EOR
ADC
ORA
ADD
‘
.
LDX
STX
SUB
CMP
SBC
.
AND
BIT
LDA
STA
EOR
ADC
ORA
ADD
.
.
LDX
STX
SUB
CMP
SBC
.
AND
BIT
LDA
STA
EOR
ADC
ORA
ADD
“
.
LDX
STX
IMM
IMM
IMM
IMM
A=
B
REL
INO
Accumulator A
= Accumulator B
= Relative
= Indexed
IMM
DIR
= Immetiate
= Direc?
IMM
B
B
B
OIR
DIR
DIR
B
B
B
B
B
B
B
B
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
B
B
B
DIR
DIR
IND
IND
IND
B
B
B
B
B
B
B
B
IND
IND
IND
IND
IND
IND
IND
IND
B
B
B
IND
IND
EXT
EXT
EXT
B
a
B
B
B
B
B
a
2. Unassign4
code indicated by J # * )‘.
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
Semiconductor
13
1 Addressing Modes:
Products Inc.
1
-----
lABLt
-
Z —
. . . . . .. .. ----
. . .. . .. . . . . .. ----
ALUUMULAIUR
AOORESSING
AND
IUN>
BOOLEAN/ARITHMETIC
EXTNO
1P-=
MNEMONIC
OPERATIONS
.-,-. ,-
UrErnAt
MOOES
INOEX
Add
MtMUMY
IMPLIEO
OPERATf
ON
(All register labels
refer to contents)
1P-=
ADDA
.-
ADOB
Add Acmltrs
B21
ABA
Add wlfh Carry
AOCA
AOCB
And
ANDA
ANOB
Blt Tesl
BITA
BITE
Clear
CLR
CLRA
F21
CLRB
F21
Compare
CMPA
CMPB
Compare Acmltrs
CBA
Complement,
COM
Complement,
1’s
COMA
1321
COMB
i321
NEG
2’s
(Negate)
Dec!mal Adi.st,
121
A
Decrement
NEGA
lo2f
NEGB
io21
OAA
1921
OEC
ExcI”si”e OR
oECA
IA21
OECB
,A21
EORA
EORB
Increment
INC
Load Acmltr
INCA
1C21
INCB
iC21
LOAA
LDAB
Or, Inclusive
A+ M-A
B+M+B
Push Oata
O RAA
ORAB
PSHA
1
A+ MSp, SP-f-SP
B-, Msp, SP–l+SP
Pull Oata
?SHB
PU LA
1
SP+I-SP,
MSP-A
PU LB
I
SP+I+SP,
M
MSP-B
A
Rotate Left
1
ROL
ROLA
!9
2
ROLB
j9
2
1
1
RORA
!6
2
1
A
RORB
j6
2
1
B lk-’’’’”[dc
ASLA
$8
2
1
ASLB
58
2
1
ASR
ASRA
a7
2
1
ASRB
57
2
1
LSRA
44
2
1
A
LSRB
54
2
1
Store Acmltr.
B}
A’-M
Subtract
A–
M-A
B–
M-B
Rotate R,ght
ROR
b7
B }L-’’’’””Jc
M
b7
-
.—
bO
—
bO
ASL
Shift Left, Ar!thmet!c
Sh[ft Right, Arfthmet!c
M
LSR
Sh!f! Right, Logic
o-~
-
0
C
bO
b7
B-M
Subtracf Acmltrs.
10
2
1
16
17
2
2
I
1
A-B
$0
2
1
50
2
1
—
A–00
B–DO
A– B-A
A–M–
C-A
B-
CON OtTION
CODE SYMBOL5
M–
C-B
B-A
M–00
CON OITION
COOE REGISTER
(Bit Set if testis
Arithmetic
Minus;
Boolean ANO:
MSP
contents Of memow
location pointed to be Stack Pointer:
Boolean Inclusive OR;
Boolean Exclusive OR;
&
M
+
Complement of M;
Transfer Into;
o
Bit = Zero;
00
Byte = Zero;
H
Hal f.carrv from bit 3;
I
Interrupt mask
N
Negative (tign bit)
z
v
Zero (byte)
c
R
otherwise]
1
V)
(Bit
Test: Result = 1000OOOO7
2
(Bit C)
Test: Result = 000000007
3
(Bit
Test:
C)
Oecimal
Character
Ovetilow, 2’s complement
Carv from bit 7
value of most significant
BCO
greater than nine?
( Not cleared
if previously
set.]
Rewt Always
4
(Bit V)
Test: Operand=
10000000 prior to execution?
01111111
s
Set Alwav$
5
(Bit V)
Test: Operand=
t
Test and set if true, cleared otherwise
6
(Bit V)
Test: Set equal to result of [email protected] after shift has occurred
●
Not Affected
Note – Accumulator addresbng mode instructions are included in tho column for IMPLIEO
MOTOROLA
@
NOTES:
true and cleared
prior to execution?
-.
addressing
Semiconductor
14
Products Inc.
PROGRAM CONTROL OPERATIONS
Program Control operation can be subdivided into two
categories: (1) Index Register/ Stack Pointer instructions; (2)
Jump and Branch operations.
Stack Pointer is automatically incremented by one just prior
to the data transfer so that it will point to the last byte stacked rather than the next empty location. Note that the PULL
instruction does not “remove” the data from memory; in the
example, 1A is still in location (m+ 1) following execution of
PULA. A subsequent PUSH instruction would overw~jt~~at
‘..$.,,,.$,.
*,.,,.:
location with the new “pushed” data.
i:~).:~~.f.,k\,
Execution of the Branch to Subroutine (B SR)a$d. #~rrfp to
Subroutine (JSR) instructions cause a returD%~*~
to be
saved on the stack as shown in Figures [email protected] 20. The
stack is decremented after each byte of,.#[email protected]?n
address is
pushed onto the stack. For both of$&[email protected],
the
return address is the memory locatid~ f~jo’wing the bytes of
code that correspond to the B,S$.:an’~:$&SRinstruction. The
code required for BSR or J g~g”~<y be either two or three
bytes, depending on whet~r,%~.J S R is in the indexed (two
bytes)
or
the [email protected] bytes) addressing mode.
Before it is stacked, [email protected]<&~$Yam Counter is automatically incremented the correct Rgmber of times to be pointing at the
location of the ~$~~~$truction. The Return from Subroutine
lnstruction,,,@K$~~puses the return address to be retrieved
and [email protected] I$to t~e Program Counter as shown in Figure 21.
There $r~s~$eral operations that cause the status of the
M PU.,$0b$wved on the stack. The Software Interrupt (SWI)
and$%ait for Interrupt (WAI) instructions as well as the
~?~,ah~e (~Q) and non-maskable (N MI) hardware inter-$ ‘[email protected]&all cause the M PU’S internal registers (except for the
,.,,,:f?
*,..~,@tack Pointer itself) to be stacked as shown in Figure 23.
“$k MPU status is restored by the Return from Interrupt, RTI, as
,,\.
shown in Figure 22.
Index Register/ Stack Pointer Operations
The instructions for direct operation on the MPU’S Index
Register and Stack Pointer are summarized in Table 3.
Decrement (DEX, DES), increment (INX, INS), load (LDX,
LDS), and store (STX, STS) instructions are provided for
both. The Compare instruction, CPX, can be used to compare the Index Register to a 16-bit value and update the Condition Code Register accordingly.
The TSX instruction causes the Index Register to be loaded with the address of the last data byte put onto the
“stack. ” The TXS instruction loads the Stack Pointer with a
value equal to one less than the current contents of the Index
Register. This causes the next byte to be pulled from the
“stack” to come from the location indicated by the index
Register. The utility of these two instructions can be clarified
by describing the “stack” concept relative to the [email protected]
system.
The “stack” can be thought of as a sequential list of data
stored in the MPU’S read/write memory. The Stack Pointer
contains a 16-bit memory address that is used to access the
list from one end on a last-in-first-out (LIFO) basis in contrast
to the random access mode used by the MPU’S other addressing modes.
The MC~
instruction set and interrupt structure allow
extensive use of the stack concept for efficient handling of
data movement, subroutines and interrupts. The instructi~.os
can be used to establish one or more “stacks” anywhg~~~<
read/write memory. Stack length is limited only <,q~$~~e
.,is,~ ,.,
amount of memory that is made available.
Operation of the Stack Pointer with the [email protected],@i~~,Rtillinstructions is illustrated in Figures 15 and 1~~..%~.$ush instruction (PS HA) causes the contents of kd$~~icated
accumulator (A in this example) to be stor~+in;wemory
at the
location indicated by the Stack [email protected] ~Q&Stack Pointer is
automatically decremented by ~~~~$~t~wing the storage
operation and is “pointing” to th~~:~e{$empty stack location.
The Pull instruction (PULA [email protected]~:~%’B) causes the last byte
stacked to be loaded intothe:w’ropriate
accumulator. The
Jump and Branch Operation
The Jump and Branch instructions are summarized in
Table 4. These instructions are used to control the transferor
operation from one point to another in the control program.
The No Operation instruction, NOP, while included here,
is a jump operation in a very limited sense. Its only effect is to
increment the Program Counter by one. It is useful during
program development as a “stand-in”
for some other instruction that is to be determined during debug. It is also used for equalizing the execution time through alternate paths
in a control program.
I
.s. .
, ‘:.
!*,.
CO ND.
?::r~
~~,,,t>~i
*,
?..*
.t ‘*:Z
PO 1NT$&Q$~&&?10
Co mp%~$~:her
iMMED
!$s.
MNEMONIC
NS
CPX
Reg
f
DIRECT
OP
-
=
OP
-
~
OP
—
8C
3
3
9C
4
2
AC
(TNO
OP
—IMPLIEO
—
OP
—
—
BOOLEAN/ARITHMETIC
1
X–l+x
Oe~.~efit
Stack
Pntr
O ES
34
4
1
SP–1-SP
lnc;&ment
Index
Reg
INX
08
4
1
X+l+x
Increment
Stack
Pntr
INS
31
4
1
SP+l+SP
o~eq~,:~$ndex
Reg
OEX
09
4
Load Index
Reg
LOX
CE
3
3
OE
4
2
EE
Load Stack
Pntr
LOS
8E
3
3
9E
4
2
AE
Index
Reg
STX
DF
5
2
EF
Store Stack
Pntr
STS
9F
5
2
AF
Store
Indx
Reg +Stack
Stack
Pntr *
Indx
Pntr
TXS
Reg
TSX
@
(Bit
N)
Test:
Sign
@
(Bit
V)
Test:
2s
bit
@
(Bit
N)
Test:
Result
of
most
complement
Iesstha”
significant
o“erfiow
zero?
(MS)
from
(Bit
15=
byte
subtraction
1
62
FE
5
62
BE
5
72
FF
6
72
BF
6
result=
of
I
35
4
30
—
4
—
L
1
1
MA
XH,
M+
SPH,
XH+M,
(M+l)
-XL
(M+1)4SPL
XL+(M+l)
SPH+M,
SPL~(M+l)
X-1-SP
SP+l+X
1?
m.
byte.?
1)
MOTOROLA
@
of
OPERATION
~
Bc
62
I
Semiconductor
15
Products Inc. —
COOEREG
I
FIGURE 15 – STACK OPERATION,
PUSH INSTRUCTION
MPU
m
SP~m
Previously
Stacked
Data
.{EI
m+l
7F
m+2
63
m+3
FD
‘c-(a) Before
~’q..i,
%
PSHA
(b)
Aftar
PSHA
—
MPU
I
I
I
I
m I
ACCA
m—2
m—1
m
SP+m+l
Previously
Stacked
Data
1A
mt2
3C
m+3
D5
\
{
Pc
~
PULA
Next
—
In$tr.
P
(a) Before
m
PULA
MOTOROLA
(b)
Semiconductor
16
After
PULA
Products Inc.
TABLE 4 – JUMP AND BRANCH INSTRUCTIONS
—
RE
G
MNEMONIC
OPERATIONS
Branch Always
BRA
Branch If Carry Clear
BCC
Branch If Carry Set
B CS
Branch If = Zero
BEO
Branch If > Zero
BGE
Branch If >Zero
BGT
Branch If Higher
BHI
Branch If < Zero
BLE
Branch If Lower Or Same
B LS
Branch If < Zero
B LT
Branch If Minus
BMI
Branch If Not Equal Zero
BNE
Branch If Overflow
Clear
BVC
Branch If Ovefilow
Set
BVS
Branch If Plus
BPL
Branch To Subroutine
BSR
hl
—
G
24
25
27
2C
2E
22
2F
23
20
2B
26
28
29
2A
80
Y
T
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8
CONO. COOE REG.
—
i— —
#
— —
T
—
# G
—
L
6E
AO
3
9
JMP
JSR
No Operation
NOP
I
Return From Interrupt
RTI
I
Return From Subroutine
RTS
I
Softwre
Swl
@
—
~
(All)
I
WAI
IAI puts Address Bus, RN,
Load
(Bit 1) Set
Condition
when
Code
interrupt
is required
to
— ~
‘n
~
ita Businthet
and
Register
occurs.
exit
the
if
wait
—
m
from
next instruction
Always
struction
Stack.
previously
(See
set,
a
state.
..?
Special
‘+~’$..used as the end of a subroutine
~y:
(BRA) instruction is similar to the J~~?~#~&nded)
inexcept that the relative addre&Sin&. fiode applies
and the branch is limited to the rang~Wtkm$125 or + 127
bytes of the branch instruction ~4,i.
i~$~}%%.~~e
opcode for the
.‘..,
,..\.?,,$<
‘
BRA instruction requires one les$by~ than J M P (extended)
to Subroutine
(BSR) is shown in Figures
18 through 20. Note t~%:[email protected] Counter is properly incremented to be$:~~~:n~
at the correct return address
before it is stac~&i,;~~#~ration of the Branch to Subroutine
and Jump to a~w~’tine
(extended) instruction is similar except for [email protected]~~n~&>The BS R instruction requires less opcode
than J $$&R{%Q~#es
versus 3 bytes) and also executes one cy (JSR)
[email protected]
Non-MaSk,:~e’’%?errUPt
.* ~+. ‘~
to be executed is fetched from ,$~$~*~~cafollowing the JM P instructl~~~}K~WBranch
but takes one more cycle to @?
The effect on program fl~~ f$r the Jump
I
—
low
Execution of the Jump Instruction,
JMP, and Branch
Always, BRA, affects program flow as shown in Figure 17.
When the MPU encounters the Jump (Indexed) instruction,
it adds the offset to the value in the Index Register and %,
the result as the address of the next instruction to~b~;~x~$
ecuted. In the extended addressing mode, the add[e~~~?he
tions immediately
10
Vc
3
3
Jump
Wait for Interrupt%
T
TEST
2
2
2
2
2
2
2
2
2
2
2
z
2
2
2
Jump To Subroutine
Interrupt
BRANCH
and Branch to Sw#rQu{*$
to return to the main program as indicated in Figure 21,
The effect of executing the Software Interrupt, SWI, and
the Wait for Interrupt, WAI, and their relationship to the
hardware interrupts is shown in Figure 22. SW! causes the
M PU contents to be stacked and then fetches the starting
address of the interrupt routine from the memory locations
that respond to the addresses FFFA and FFFB. Note that as
in the case of the subroutine instructions, the Program
Counter is incremented to point at the correct return address
before being stacked. The Return from Interrupt instruction,
RTI, (Figure 22) is used at the end of an interrupt routine to
restore control to the main program. The SWI instruction is
useful for inserting break points in the control program, that
is, it can be used to stop operation and put the MPU
registers in memory where they can be examined. The WAI
instruction is used to decrease the time required to service a
hardware interrupt; it stacks the MPU contents and then
waits for the interrupt to occur, effectively removing the
stacking time from a hardware interrupt sequence,
FIGURE 17 – PROGRAM FLOW FOR JUMP AND BRANCH INSTRUCTIONS
[X+K
~
[ ,,-,
(n+2)*Klxl
●K = Signed 7-bit value
(b) Branch
(a) Jump
m
MOTOROLA
Semiconductor
17
Products Inc.
I
FIGURE 18 – PROGRAM FLOW FOR BSR
a
SP~m–2
m—1
(n +2)H
m
m+l
n
“ + 1
]
tK
n+ 2 I
Next
= Offset*
Main
* K = Signed
(a) Before
l“str.
7-Bit
I
n+l
I
n+2
value
Execution
-.
,~i)::~’
FIGURE 19 – PROGRAM FLOW FOR JSR (~TENDEm,\
\ ,\~.,,
‘%,
FIGURE 20 – PROGRAM FLOW FOR JSR (lNDWED)
r
m—l
m—1
(n+2)H
m
(n+2)L
sP—m
7E
m+l
m+l
7E
7A
7A
—
B
PC_n
JSR=AD
n+l
“1
JS R
I
“
“+1
K = Of fset”
Next
“+2
Main
JSR
K = Offset
“+2
l“str.
= AD
Next
Main
l“str.
a
g
n+
2
I
SL=Sub,.
Addr,
I
●K = 8-Bit
U“sig”ed
Value
PC+
X.+K
1st S.br,
Instr.
1
r
(a) Before
1
“Contents
Ex%utton
““s=
(a) Before
(S formed
from
SH and SL)
Execution
1
(b) After
MOTOROLA
Execution
Semiconductor
18
Products Inc.
(b)
of Index
Afrer
Register
Execuxion
FIGURE 21 – PROGRAM FLOW FOR RTS
H
SP-m–2
m—2
(n+3)H
m—1
m—1
m
m+l
n
n+l
SH
= Subr.
Addr.
n+l
nt2
SL
= Subr.
Addr.
n+2
nt3
I
B
Last Subr.
Instr.
R TS
FLOW FOR RTI
m—7
m—6
CCR
m—5
ACCB
m—4
ACCA
m—3
x~
m—2
XL
PCH
m—1
4
sp~
PCL
m
7E
Pc—
s“
Pc —
a
Last Inter.
“+1 I
I
I nstr.
I“str.
I
Last S“br.
Instr.
I
s“
(b)
Execution
MOTOROLA
@
Main
J
RTI
(a) Before
Next
Semiconductor
19
After
Execution
Products Inc.
I
FIGURE ~
– PROGRAM
FLOW FOR INTERRUPTS
.Wait For
Interrupt
Main Program
Software lnterruDt
Main Program’
n:=.
:1=
Hardware Interrupt or
NonMaskable Interrupt (NMI)
Main Program
n-
Sp
+
7“
Stack MPU
Register Contents
m—7
m—6
m—5
m—4
m—3
m—2
m—1
m
WI
FFFC
FFFD
FFF8
FFF9
d
Interrupt Memorv Assignment
FFF8
I
IRQ
I
FFF9
IRQ
LS
FFFA
Swl
MS
FFFB
Swl
#
Set Interrupt
Mask (CCR 4)
Ms
First Instr.
Addr. Formed
LS
e
Load Interrupt
Vector Into
Program Counter
BvFetching
2. Eytes From
Per, Mere,
Assign.
Q
f
NOTE: MS= Most Significant Address Bvte;
LS = Least S~nificant Address Byte;
MOTOROLA
@
>
1 lstlnterruutlnstr.
1
I
1
Semiconductor
20
A
I nterruot
,. Proaram
Products Inc.
FFFE
FFFF
FIGURE 24 – CONDITIONAL
BRANCH INSTRUCTIONS
:
N=l
;
BEQ
:
Z=l
;
BPL
:
[email protected]
;
BNE
:
Z=4
;
BVC
:
V=$
;
BCC
:
C=$
;
BVS
:
V=l
;
BCS
:
C=l
;
BHI
:
c+
;
BLT
:
[email protected]=l
;
BLS
:
C+z=l
;
BGE
:
[email protected] [email protected]
;
BLE
:
Z+([email protected])=l
BGT
:
Z+([email protected])[email protected]
The conditional
[email protected]
branch
for testing
magnitude
as unsigned
when
binary
the values
numbers,
being
tested
that is, the values
are in the range 00 (lowest) to FF (highest).
BCC following
a
comparison
(CMP) will cause a branch if the (unsigned)
value in the accumulator
is higher than or the same as the
value of the operand.
Conversely,
BCS will cause a branch if
the accumulator
value is lower than the operand.
The fifth complementary
pair, Branch On Higher (Qi&~~~,nd
Branch
On Lower or Same (BLS) are, in a se~~~/[email protected]~plements to BCC and BCS. BHI tests for both C [email protected]~~O;
if
used following
a CMP, it will cause a branc~,?k~~pWalue
in
;
instructions,
relative
are regarded
BMI
the accumulator
is higher than the oper&~~%50nversely,
BLS will cause a branch if the unsignq~’~~a~’”value
in the
Figure 24, consists
accumulator
is lower than or the saW:~$J&b
operand.
The remaining
two pairs are u~~l
~ ‘testing results
of
of
seven pairs of complementary
instructions.
They are used to
test the results of the preceding
operation
and either continue with the next instruction
in sequence
(test fails) or
cause a branch to another
point in the program
(test suc-
operations
in which the values at% re&~Yded as signed two’s
complement
numbers. This $%&&}{rom
the unsigned binary
case in the following
sen:~+~~.{~nsigned,
the orientation
is
higher or lower;
in si~w’~,wo’s
complement,
the com-
ceeds).
Four of the pairs are used for simple
parison
is between
@$~~g~&~ smaller
values is between
– 1~,.,and + 127.
Z, V, and C:
1. Branch on Minus
tests of status
(B MI) and Branch
bits N,
(BNE) are used to test the zero status
whether or not the result of the previous
to zero. These two instructions
pare (CMP) instruction
to test
bit, Z, to determine
operation was equal
are useful following
a Comfor equality
between
an ac-
cumulator
and the operand. They are also used following
the
Bit Test (BIT) to determine whether or not the same bit pos~~
>.t;.’:
,Y).
....,.,,
~
tions are set in an accumulator
and the operand.
3. Branch
On
Overflow
Clear
(BVC)
and
,+::>
[email protected]$~ns
The
Condition
~
~~~~Register
(CCR)
is a 6-bit
the MPU~~~kl$*useful
in controlling
system d;%tlon.
The bits are defined
and Branch On Greater Than Zero (BGT) test the status bits
for [email protected] (N+V) = 1 and [email protected] (N +V) =0, respectively.
The action of BLE is identical to that for BLT except that a branch
will also occur if the result of the previous result was zero,
Conversely,
BGT is similar to BGE except that no branch will
occur following
a zero result.
instruction
earl~:~~$~~
processors,
was $~d (Least Significant
sequence
operated
to the user
properly,
with
only if the preceding
instruction
Bit= 1), Similarly it was advisable
MOTOROLA
@
to precede any SEI instruction
with
as NOP. These precautions
are not
processors
indicating
manufacture
later.
Systems which require an interrupt
under program control should use a
rather than CLI-SEI.
register
program
flow
in Figure 25.
The instr~~lia~% shown in Table 5 are available
for dire~#[email protected]@@ulation
of the CCR.
A C~,$A/
‘*N cause. a branch following
operations
in which two positive
values were added or in which the result was zero.
The last pair, Branch On Less Than Or Equal Zero (BLE)
CONDITION CODE REGISTER
OPERATIONS
‘ i$,:,i
;;*
. .
. .?“s$.~$$:’
,,
l~~k,J.F
‘$?.,,
within
during
of
adde,~. in’~dition,
it will cause a branch following
a CMP in
wh#~$Jhe
value in the accumulator
was negative and the
,@$&~~n’&was positive.
B LT will never cause a branch follow.,:[email protected],$#CMP
in which the accumulator
value was positive and
{f$:,,.j
,,+,...::}
we operand
negative.
BGE, the complement
to BLT, will
( BCS) tests the state of the C bit to determ~~$$~~~previous
operation
caused a carry to occur. BCC ~~,~~~b
are useful
.,*.J?,’ -~>,‘:?
,,,1.,.
range
and N e V{~$<,,r~pectively.
B LT will always cause a branch
followin$~~s
8~~ration
in which two negative numbers were
Overflow
Set ( BVS) tests the state of the V bit to ~&~*e
if the previous operation
caused an arithmetic
[email protected],@~
Set
4. Branch On Carry Clear (BCC) and Branch @~b$rY
.,.y
the
Branch On [email protected]$~$anZero
(BLT) and Branch On Greater
Than Or Eq~#k.~~~’~~G
E) test the status bits for N @V= 1
On Plus (BPL) tests
the sign bit, N, to determine
if the previous
result was
negative or positive,
respectively.
2. Branch
On Equal (BEQ) and Branch
On Not Equal
where
Semiconductor
21
an odd opcode
necessary for
in November
– such
MC~
1977 or
window
to be opened
CLI-NOP-SEI
sequence
Products Inc.
L
CO ND.
COOE
—.
REG.
m
E
=
The M P&%~&$ates on 8-bit binary numbers
via the..~t~~~?{~us.
A given number
(byte)
HI
NZVC
●
00m*
1
0+1
●
R****
1
O+v
●
.mm
1
l+C
●
Ore**
1
1+1
●
1
l-v
●
S.
**O
1
A+CCR
1
CCR+A
R
R.
s
*Q.
s.
w
●
●
● \*
●
●
appropriate
opcode then depends on the method
used. If
manual translation
is used, the addressing
mode is inherent
in the opcode. For example, the immediate,
Direct, Indexed,
and Extended modes may all be used with the ADD instruction. The proper
mode is determined
by selecting
(hexadecimal notation)
8B, 9B, AB, or BB, respectively.
The source statement
format includes adequate
informa-
presented to it
may rePresent
actloh on 197 of the 256 possibilities that can occur using an
8-bit word length. This larger number of instructions
results
from the fact that many of the executive
instructions
have
tion for the selection
if an assembler
program
is used to
generate the opcode.
For instance,
the Immediate
mode is
selected by the Assembler
whenever
it encounters
the “#”
symbol in the operand field. Similarly, an “X” in the operand
field causes the Indexed
mode to be selected.
Only the
Relative mode applies to the branch instructions, therefore,
more than one addressing
mode.
These addressing
modes refer to the manner in which the
program causes the MPU to obtain its instructions
and data.
The programmer
must have a method
for addressing
the
MPU’S internal registers and all of the external memory loca-
the mnemonic instruction itself is enough
to determine addressing mode.
tions.
Selection
of the desired addressing
mode is made by the
user as the source statements
are written.
Translation
into
MOTOROLA
OPERATION
O+c
eithe&~{[email protected]:or an instruction
to be executed,
depending
on
[email protected]@/~,~s encountered
in the control program.
The Mm
ha$~~tinique
instructions,
however, it recognizes and takes
@
BOOLEAN
1
Semiconductor
22
for the Assembler
Products Inc. ~
“operands”
but the space between
may be omitted. This is commonly
For the instructions that use both Direct and Extended
modes, the Assembler selects the Direct mode if the operand
vaiue is in the range O-255 and Extended otherwise. There
are a number of instructions for which the Extended mode is
valid but the Direct is not. For these instructions,
the
Assembler automatically
selects the Extended mode even if
the operand
summarized
is in the O-255 range. The addressing
in Figure 26.
parent four character mnemonics for those instructions.
The addition instruction,
ADD, provides an example
dual addressing
(Includes
“Accumulator
Addressing”
ADDB
Mode)
The successive
fields in a statement
are normally
separated by one or more spaces. An exception to this rule
the two accumulators.
Direct:
n
Example:
SUBB
Z
Addr.
Rane
= O–255
A
DO
n+l
ADD CONTENTS OF MEM12 %Q #&C~
i.;~:,
,,,~ ,;i,\.JtJ$+t’$
used earlier for the test instru~&~~?ST,
Next
n+2
Instr.
OR
(K
= Two-Bvte
Inst.
Next
OR
z&
Oprnd)
ad-
Address
●
(K = One-Bvte
also
Instruction
Z = Oprnd
n+2
MEM12
The example
In these cases, A and B are
of
field:
applies to the accumulators and uses th,$~~~~ohulator
dressing mode” to designate which o$,,x’v-accumulators
\,*\ ~$.;:
is being tested:
.~#<:,\,
~:;
.jt
.\~;,
.
.
occurs for instructions
that use dual addressing
in the
operand field and for instructions that must distinguish retween
in the operand
Comment
Operand
MEM12 ADD CONTENTS OF MEM12 TO j&~$:k
. t;..,
~~,~~1~$~
,,?~
..:$
Operator
ADDA
modes are
or
Inherent
them and the operator
done, resulting in ap-
I
n+2
.:,,.
*“r,
n+3
KL
= Operand
I
Next
Instr.
I
Instruction
I
I
Oprnd)
n
Relative:
Example:
BNE
(K = Signed
7-Bit
I
K
Value)
●
Addr.
Range:
–125t0
+129
Relative
to n.
●
(“+2)’K-
J
ntl
ZH
= Oprnd
Addr-s
~
n+2
ZL
n+3
= Oprnd
Next
If Br”ch
Tst
False,
~
if Brnch
Tst True.
Address
Instr.
.
n
Indexad:
●
Example:
ADDA
Instruction
I
Z, X
‘+1-
Addr.
O–255
Index
(K = One-Bvte
Range:
Relative
Register,
Next
n+2
o
Oprnd)
z&
●
OR
(K = Two-Bvte
OPrnd)
z
[
KH
= Operand
I
(Z = a-Bit
Value)
MOTOROLA
@
Unsignad
Semiconductor
Q9
x+z&
Products Inc.
Instr.
1
I
to
X
1
* :’@ o
Operator
TSTB
Comment
TEST CONTENTS OF ACCB
mode,
the “address”
of the operand
is effectively
the
memory location immediately
following
the instruction
itself.
Table 7 shows the cycle-by-cycle
operation
for the im-
TSTA
TEST CONTENTS OF ACCA
mediate
or
A number
of the instructions
either
alone or together
Direct
with
ing, enabling
require only one byte of opcode.
Cycle-by-cycle
of the inherent
mode is shown in Table 6.
In the
Direct
the MPU to reach theik~~~J&”hg
memory
loca-
to the value [email protected] t~~{~100
in the example) and fetches the
operand,
in t~~~$$e
a value to be loaded into accumulator
A, from th,~+~p~$$n.
For instructions
requiring a two-byte
Immediate Addressing Mode – In the Immediate addressing mode, the operand is the value that is to be operated on.
For instance, the instruction
operande$~hk~
LDX (Load the index Register), the operand
bytes $+~4&Be retrieved from locations 100 and 101. Table 8
sh%~ws t~~ cycle-by-cyc4e
operation
for the direct mode of
a*~ssi
ng,
,~~’+i$xt~nded
addressing,
Figure 31, is similar except that a
Comment
LOAD 25 INTO ACCA
load accumulator
–
tion
LDAA
(Direct)
at,~~ary
location
5004 (Program
Counter=
5004), look~~~~$~:~next
location,
5005, for the address of the operan~$~~~{~~
sets the program counter equal
on the left and a specific example is shown on the right.
Numerical
examples are in decimal notation.
Instructions
of
the M PU to “immediately
Modes
tions, 256 through
65535. An ex~&pl$ O* Direct addressing
and its effect on program flo,~~~ ~&lrated
in Figure 30.
The M PU, after encoun\[email protected]<~e
opcode for the instruc-
Program flow for instructions
of this type is illustrated
in
Figures 27 and 28. In these figures, the general case is shown
causes
Addressing
M PU. Direct addressing
generates
a sin~l~.~~%~ operand
and, hence, can address only memory [email protected]~&&~’& O through
255; a two byte operand is generated~{&~QEx&&~ded address-
of accumulator
B to be increased by one. Similarly,
INX, increment the Index Register, causes the contents of the Index
Register to be increased by one.
Operand
#25
and Extended
operated on. The Direct and Extended modes d~ff~$:fi$y
in
the range of memory locations to which they ~$~~trect
the
add the contents of accumulators A and B together and place
the result in accumulator
A. The instruction
INCB, another
example of “accumulator
addressing,”
causes the contents
Oper*or
LDAA
mode.
and Extended modes of addressing,
the operand field of the
source statement
is the address of the value tha$+i$j~o be
an accumulator
operand contain all of the address informain the instruction
tion that is required,
that is, “inherent”
itself. For instance, the instruction
ABA causes the MPU to
this type
operation
addressing
:t:~:[email protected]
A with
address
is obtained
from
locations
5007 and 5008
~~,,.$$tafter
the LDAB (Extended)
opcode shows up in location
“e$s 5006. Extended addressing
can be thought
of as the “standard” addressing
mode, that is, it is a method of reaching
m,~de ~y>t,$
y..\
.*.,.J.$,i~>>,
any place in memory.
Direct addressing,
since only one ad-
the value 25’; no further address reference is required. The
Immediate
mode is selected by preceding
the operand value
with
the “#”
symbol.
Program
is illustrated
in Figure 29.
The operand format allows
flow for this addressing
either
properly
to 255.
—
dress byte is required,
provides a faster method of processing data and generates fewer bytes of control code. In most
applications,
the direct addressing
range, memory locations
O-255, are reserved for RAM. They are used for data buffering and temporary
storage of system variables,
the area in
define$:$ym
bols or numerical
values. Except for the instru~ti~~’WX,
LDX, and LDS, the operand may be any valu~,i~:~e,;~nge
—
O
Since
Compare
Index Register (C&,~Q$.~~&’d Index
Register (LDX), and Load Stack Pointer (~$~;.$e~uire
16-bit
values, the immediate
mode for these~%re~+ ~tistructions
require
two-byte
operands.
In th~:T~,Yate
addressing
which
faster
operation
addressing
is shown
FIGURE Z
MPu
is of
most
value.
in Table 9 for Extended
– ACCUMULATOR
Cycle-by-cycle
Addressing.
ADDRESSING
m
MPU
M Pu
INDEX
ACCB
a
z
@
PROGRAM
MEMORY
Pc
4
RAM
PC = 5000
pROGRAM
MEMORY
INSTR
Pc
I
PC = 5001
w
GENERAL
FLOW
a
PROGRAM
MEMORY
B
INX
t
RAM
RAM
F
PROG RAM
MEMORY
INSTR
GENERAL
m
EXAMPLE
FLOW
MOrOROLA
@
Semiconductor
24
Producfs Inc.
INC B
EXAMPLE
-.
Relative Address Mode – In both the Direct and Extended
nodes, the address obtained by the MPU is an absolute
~umerical address. The Relative addressing mode, im)Iemented for the MPU’S branch instructions, specifies a
nemory location relative to the Program Counter’s current
Dcation. Branch instructions generate two bytes of machine
:ode, one for the instruction opcode and one for the
‘relative” address (see Figure 32). Since it is desirable to be
ible to branch in either direction, the 8-bit address byte is inerpreted as a signed 7-bit value; the 8th bit of the operand is
rested as a sign bit, “O”= plus and “1”= minus. The renaining seven bits represent the numerical value. This
esults in a relative addressing range of * 127 with respect to
he location of the branch instruction itself, However, the
)ranch range is computed with respect to the next instrucion that would be executed if the branch conditions are not
iatisfied. Since two bytes are generated, the next instruction
s located at PC + 2. If D is defined as the address of the
)ranch destination, the range is then:
the unconditional jump (JMP), jump to subroutine (JSR),
and return from subroutine (RTS) are used.
In Figure 32, when the MPU encounters the opcode for
BEQ (Branch if result of last instruction was zero), it tests the
Zero bit in the Condition Code Register. If that bit is “O,” indicating a non-zero result, the MPU continues execution
with the next instruction (in location WIO in Figure 32). If the
previous result was zero, the branch condition is satisfied
and the MPU adds the offset, 15 in this case, to PC+ 2 and
branches to location W25 for the next instruction.
The branch instructions allow the programmer to efficientIy direct the MPU to one point or another in the contro$.:~rogram depending on the outcome of test results. ~W~%e
control program is normally in read-only memory #[email protected]
be changed, the relative address used in [email protected][email protected]&ranch
instructions is a constant numerical valuq~’[email protected]
operation is shown in Table 10 for relatig& [email protected]
.}:\A,#‘
~,\ .!-,
s. ,,,,i,
-!l!,.,
Indexed Addressing Mode – ~~~~d~xed
addressing,
the numerical address is variable qnd d~ends on the current
(PC+2)– 127SD S(PC+2)+127
contents of the Index [email protected]~~$ource statement such as
)r
.+:Y>
,.‘.~’\\..!
.-,~.‘‘\,.
~,*.\:)fJ~
PC–125<D~PC+129
Operan~*~~~ ~
Operator
Comment
hat is, the destination of the branch instruction must be
X Ut;;:[email protected]&T A IN INDEXED LOCATION
STAA
vithin – 125 to + 1.29 memory locations of the branch in*\+~*%\.g;~
:
truction itself. For transferring control beyond this range,
causes the M PU,:~q
stalk
the
contents of accumulator A in
.,)
.tJ;.,
.,~<{y..,\\
., $:.?;,\
TABLE 6 – INHERENT MODE CYCLE-BY-CYCLE~~~~*lON
Addre*
Mode
and I nmructions
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA
Cycles
SEC
SE I
SEV
TAB
TAP
TBA
TPA
TST
2
DES
DEX
INS
INX
4
Cycle
#
1
1
2
1
,,+?
,:~, ,@ ~~’lw
~t.:.:~’ Lina
.r]i,
,%
.,,
.<,;
,,,
..- ,
,,.t,,,,., .l’:.+
.c:.~
~*,:r,
1
Op Code Address
~.i: .$.
1
OP Code Addrass + 1 ~*.st,&$f~
‘!><::+:$<>
~,.;*:~\,
.,?>~:k(.’
.fi
~~~
~,
,~~ ~i~
.,
:$.>, ,\,,,.\
,
..*Y-. “’?.
1
0 p$**j$dHress
Address Bus
1
1
2
1
3
0 *$~~$~~us
Register Contents
~..~<f;~~~~w Register Contents
4
PSH
VMA
Lina
~~.~~$$e
Address+
I
4
PUL
.,
,{,:
.-~
\\,
.+
.:! [email protected]*” ~}
‘\~\ \\t\*.’
.3..,,, ,.
~:’,$.,j$:t
$“
,... “’i:.*
.
Y ~~.$,,
TSX
‘-?
;*-{.,-$:.
J.~.~.ikb
,.*T. “‘,?.. ‘
“J~
$~” ...
4
:.$
.. . . ‘k~:+.},t~$
*$,f..‘:%”
\**,,
,.~.’~kq~,,.’
*Y.,
..,,
TX$~~~W ““
y;.
4
RTS
5
~,q ~p.~ #
>,.
.,.
?4>,,
~j$ ,
., .
2
3
o
,
‘
0
Instruction
Op Code
1
Op Code of Next Instruction
1
Irrelevant
Data (Note
1
Irrelevant
Data (Note 1 )
1
Op Code
1
Op Code of Next
Stack Pointer
o
Accumulator
Data
Data
1
Accumulator
Op Code Address
1
Op Code
Op Code Address + 1
1
Op Code of Next
Stack Pointer
1
Irrelevant
1
Operand
Stack Pointer
– 1
4
1
Stack Pointer
1
1
Op Code Address
1
Op Code Address+
+ 1
1)
Instruction
instruction
Data (Note
1)
Data from Stack
1
Op Code
1
Op Code of Next
Q
Stack Pointer
1
Irrelevant
Data (Note
1)
0
New Index Register
1
Irrelevant
Data (Note
1)
1
1
Op Code Address
1
Op Code
2
1
OP Code Address+
1
Op Code of Next
Index Register
1
Irrelevant
Data
Data
2
3
4
1
1
Instruction
Instruction
3
0
4
0
New Stack Pointer
1
Irrelevant
1
1
OP Code Address
1
Op Code
1
Irrelevant
Data (Note 2)
1
Irrelevant
Data (Note
2
1
OP Code Address+
3
0
Stack Pointer
4
1
Stack Pointer
+ 1
1
Address of Next
Order Byte)
Instruction
(High
5
1
Stack Pointer
+ 2
1
Address of Next
Order Byte)
Instruction
(Low
M070ROLA
@
Op Code
Op Code of Next
Op Code Addrass + 1
1 ,/ S* ‘$~~~?.$OP Code Address
.,t~,.:! ,),,,$
g 3 ‘$$,“’” ,
Data Bus
1
Semiconductor
25
Products Inc.
1)
TABLE
I
Address Mode
and Instructions
Cycles
6 –
CVcle
#
VMA
Line
R lx
Line
Address Bus
1
Op Code
Op Code Address + 1
1
Op Code of Next
3
1
Stack Pointer
Return
4
1
Stack Pointer
– 1
5
1
Stack Pointer
– 2
o
0
0
6
1
Stack Pointer
– 3
7
1
Stack Pointer
– 4
8
1
Stack Pointer
– 5
0
0
0
9
1
Stack Pointer
– 6 (Note 3)
1
1
1
Op Code Address
2
1
Op Code Address+
3
0
Stack Pointer
1
1
1
1
Instruction
Address (Low Order Byte)
Return
Address (High Order Byte) ‘Q,,x,
t:f,s:.,.;:~;$$
*
Index Register (Low Order By&G].;;.;” ~
“..*.,> !~{$
Index Register (High Ord:[O &#}$
Contents
of Accumula~~.
~~p~ “p
.’.,,,.\{..>
~,*r<,+
Contents of Accurn,~taYM $:
\%*~,
\.
Contents of [email protected]~,Segister
..*,
i.,.:.$.,)yp
,t,\,+
Op Code
.a>~+m.,
Irrelevant ~ata [email protected] 2)
lrreleva$$k~~a
(Note 1 )
...*;,*,\,
,~<
~.+,>+
‘..,.>
CoRW~&~ti Cond. Code Register from
S*[email protected]” ,,s.
4
1
Stack Pointer + 1
1
5
1
Stack Pointer + 2
1,4 :#&q$ %ts
6
1
Stack Pointer + 3
7
1
Stack Pointer + 4
‘f$ac ~y~e~ Register from Stack (High Order
8
1
Stack Pointer + 5
Index Register from Stack ( Low Order
Byte)
9
1
Next Instruction Address from Stack
(High Order Byte)
10
1
,>;:
,,,,.?,:*.
‘\.*: ,
,,,.y;,:,~, ,,.
Stack Pointer + 7
~;? ~...k.
,$ ~!’>i, ,;i)
.+\ \ ..,,.....
Op Code Addresq&+,t~S
,,
Op Code Address ~{~
.\i?.....3:,~*.,
1
1
2
1
3
1
1
.3**:
Stack Pointer + 6
Stack Poi$ter
,><~.
Stack ,~in~~
Sta*~hter
{!,<, - ...
1 :@~ok%~inter
6
~ ‘..S,:...,NTY’
.*
1 >j$
‘:;t*,#
Pointer
J
,.::,,
/.. ,:~<
, .,:>,
,,{’!~$$ ;$tack Pointer
8
,:,,i:\$\
i?,
%~i> $1 ‘ Stack Pointer
5
1
$:TO ;6:r$o
Stack Pointer
1
1
[email protected]?~$~,~PU is waiting for the interrupt, Bus Available
[email protected]~ess
BUS, RM, and Data Bus are all in the high
,,:‘w:.”‘~.,~jl,
~.~> ,:
‘%ntents
Irrelevant
Return
Index
– 5
o
0
0
0
– 6
0
– 7
1
– 1
– 2
– 3
– 4
will go high indicating
B from Stack
of Accumulator
A from Stack
.Op Code
o
0
~;
of Accumulator
Next Instruction Address from Stack
(Low Order Byte)
1
Vector Address FFFA (Hex)
1
.>’+):$W,$
1
,~
$.}
:;,*
:,
,$,
. .J$,*
“’”
“?.,..>
‘;’ 12
1
Vector Address FFFB (Hex)
1
....% :.$
,
:.+;l+
,.:y
?
t$.~
~’ .QA:.$~
If device wh.?~~ls,@dressed
during this cycle uses VMA, then the Data Bus will go to the
Dependi,n,~ 4Q b~ capacitance, data from the previous cycle may be retained on the Data
Data is,@[email protected] bv the MPU,
,,<.J*:\\>
Data Bus
Op Code Address
4
Note 3.
(CONTINUED)
1
SwI
Note 2.
OPERATION
1
10
Note 1.
CYCLE-BY-CYCLE
1
RTI
12
MOOE
2
WA I
9
INHERENT
Data (Note
1)
Address (Low Order BVte)
Return
Address (High Order Byte)
Register
(Low Order Byte)
Index Register
(High Order Byte)
Contents
of Accumulator
A
Contents
of Accumulator
B
Contents
of Cond. Code Register
Irrelevant
Data (Note
1)
Address of Subroutine
Byte)
(High Order
Address of Subroutine
Byte)
(Low Order
high impedance
Bus.
the following
three-state
states of the control
condition.
lines: VMA
is
impedanca State.
‘,$.
,.,.!;.,...:,+ ....,y. .:’>”
~’~i>,,
,; ]*;i~.?J>
.l,*!<.
-
location 5006, it looks in the next memory location for the
value to be added to X (5 in the example) and calculates the
required address by adding 5 to the present Index Register
value of 4~.
In the operand
format,
the offset
may be
represented
by a label or a numerical value in the range O-255
th$w.~ory
location specified
by the contents
of the Index
[email protected] (recall that the label “X” is reserved to designate the
Index Register). Since there are instructions
for manipulating
X during program execution
(LDX, INX, DEC, etc.), the indexed addressing
mode provides a dynamic “on the fly” way
to modify program activity.
The operand field can also contain a numetical
value that
will
to X during
execution.
mat is illustrated
in Figure 33.
When the MPU encounters
the LDAB
be automatically
added
(Indexed)
This foropcode
MOTOROLA
@
as in the
example.
In the
earlier
example,
STAA
X, the
operand is equivalent
to O, X, that is, the O may be omitted
when the desired address is equal to X. Table 11 shows the
cycle-by-cycle
operation
for the Indexed Mode of Addressing,
in
Semiconductor
26
Products Inc.
FIGURE =
–
IMMEDIATE
ADDRESSING
FIGURE 30 –
MODE
MPU
MPU
DIRECT ADDRESSING
MPU
ACCA
ACCA
m
%
RAM
MODE
MPU
m
RAM
m
RAM
m
RAM
G
DATA
ADOR
*
PROGRAM
MEMORY
I
DATA
GENERAL
1
PROGRAM
MEMORY
‘C=’oo’w
‘C’*
INSTR
Pc
II
PROGRAM
MEMORY
EXAMPLE
FLOW
Address Mode
and 1nstructions
Cycle
#
Cycles
EXAMPLE
VMA
Line
Addrass Bus
,1?,’
?!i<,,l>;
.\.!),,
Data Bus
.f’’’*,..,
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
2
CPX
LDS
LDX
1
Op Code Address
1
Op Code Address+
3
Address Mode
and Instructions
[
1
2
~\
.es”’$% ‘“
1 ‘~+?<q,~’~
“‘~!-’::...
,,.!’$.,,..
, .,,,,,
‘~
~..,?t.,,
.Q,.
1
Op Code
1
Operand
Data
1
1
Op Code
1
Op Code [email protected] *’”
,,,:,
..:..i.~,
OP CodaL$dd~ss
+ 1
1
2
1
Operand
Data (High Order Byte)
3
1
OD C&&hress
1
Oparand
Data (Low Order Byte)
+ 2
Addres
Cycles
R/~
Line
Bus
Data Bus
!.~:
~~
,
t:~
>.,....., ..~~
,a.\’.
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
\,.
‘*.,
,.
Op Code Address
1
Op Code
Op Code Address+
1
Address of Operand
Address of Operand
1
Operand
Op Code Address
1
Op Code
Op Code Address + 1
1
Address of Operand
Address of Operand
1
Operand
Data (High Order Byte)
1
Operand
Data (Low Order Byte)
1
Data
,,
CPX
LDS
LDX
STS
STX
5
4
1
Operand
1
1
Op Code Address
1
Op Code
Op Code Address + 1
1
Destination
3
0
Destination
Address
1
irrelevant
4
1
Destination
Address
o
Data from Accumulator
1
Op Code
1
Address of Operand
Address + 1
1
1
Op Code Address
1
OP Code Address+
3
0
Address of Operand
1
Irrelevant
4
1
Address of Operand
o
Register Oata (High Order Byte)
5
1
Address of Operand
0
Register Data (Low Ordar BVte)
on bus capacitance,
B
1}
2
Note 1. If device which is address during this cvcle uses VMA,
Depending
Address
Data (Note
1
+ 1
then the
Data BUS WIII go to ?ne nigh
data from the previous cycle may be retained
MOTOROLA
,.,
impeaance
tnree-s~aIe
on the Data Bus.
Semiconductor
27
Data (Note
Products Inc.
1)
,.. .
conolrlon.
I
FIGURE 31 – EXTENDED ADDRESSING
MPU
MODE
MPu
R
RAM
RAM
ADOR
DATA
ADDR
= 300
PROGRAM
w
M
I
PROGRAM
MEMORY
%MEMORY
PC = 5006
INSTR
Pc
I
LDA
B
ADDR
ADDR
AODR
300
“
5009
@
> 256
GENERAL
EXAMPLE
FLOW
TABLE 9 – EXTENDED MODE CYCLE-BY-CYCLE
Address Mode
and Instructions
Cycles
Cycle
=
VMA
Line
1
STS
STX
6
OP Code
2
Address
of Operand
(High
Order
Byte)
3
Address
of Operand
(Low
Order
Byte)
4
Irrelevant
5
Operand
Data
(High
Order
Byte)
6
Operand
Data
(Low
Order
Byte)
JSR
Op Code
Address
of Subroutine
(High
Order
Byte)
3
Address
of Subroutine
( LOW Order
BVte)
8
9
3
Op Code
Address
+ 1
OP Code
Address
+ 2
OP Code
6
Address
Address
of Operand
Address
of Operand
Address
0
Return
Address
1
1
1
1
Irrelevant
of Next
Irrelevant
Address
Instruction
(Low
(High
---
Order
Bvte)
Order
BVte)
Oata
(Note
1)
Data
(Note
1)
of Subroutine
(Low
Order
Bvte)
Op Code
Jump
Address
(High
Order
Bvte)
1
Jump
Address
( LOW Order
Bvte)
1
Op Code
Address
of Operand
(High
Order
BVte)
Address
of Operand
(Low
Order
Bvte)
Operand
Data
Op Code
1
+ 2
Address
3P Code
Return
II
w
OP Code
1
0
L
5
7
LSR
NEG
ROL
ROR
TST
1)
1
6
ASL
ASR
CLR
COM
DEC
INC
(Note
2
4
9
Data
I
+ 1
Address
of Operand
(High
Order
BVte)
Address
of Operand
(LOW
Order
BVte)
1
Operand
Data
(High
Order
BVte)
1
Operand
Data
(LOW
Order
Bvte)
OP Code
Address
1
Op Code
Op Code
Address
+ 1
1
Destination
Address
(High
Order
Bvte)
Op Code
Address
+ 2
1
Destination
Address
( Low
Order
Bvte)
Operand
Destination
Address
1
Irrelevant
Operand
Destination
Address
o
Data
1
OP Code
1
Address
of Operand
(High
Order
Bvte)
Address
of Operand
(Low
Order
Bvte)
Operand
Op
Code
Address
Op
Code
Address
+ 1
Op Code
Address
+ 2
II
I
Oata
from
Address
of Operand
1
Current
Address
of Operand
1
Irrelevant
Address
of Operand
o
New
(Note
1)
Accumulator
Data
Operand
Data
(Note
Data
1)
(Note
2)
..
~te 1.
It device
Depending
Note
2.
For
TST,
which
IS addressed
during
on bus capacitance,
VMA
= O and
Operand
this
data
data
cvcle
from
does
uses VMA,
the
not
previous
the
mav
Data
Bus will
ba retatned
go to the
on the
Data
high
impedance
three-state
condition,
Bus.
change,
MOTOROLA
@
then
cycle
Semiconductor
28
Products Inc.
a
s
FIGURE 32 – RELATIVE ADDRESSING
~AM
RAM
1
PrOaram
MeGory
Program
Memorv
i
Instr.
Pc
Offset
(PC + 2)
Next
MODE
MPU
MPU
5008
Instr.
BEQ
15
Pc
5010
Pc
Next Instr.
t
MPu
ADDR
= INOX
+ OFFSET
.
..3
1,’
,,.
.,.y#
...
?k,\*a\.
-~
...
..,.
OFFSET<
255
..
TABLE 10 – RELATIVE MODE CYCLE-BY-CYCLE
.
..,$~~
,>?
.+..
Address [email protected],.,.j:, ‘
and I nstruc,$~~ “r’’’*’f Cycles
‘:.>,.$’{,,
{t,. i.>~:+,,
cycle
+
VMA
Line
OPERATION
Address Bus
RIG
Line
Data Bus
1
\*>: .+
BCC
BH#~’B~b’
BCS ,@&[email protected]>>@~L
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4
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8
1
1
OP Code Address
1
Op Code
2
1
Op Code Address + 1
1
Branch Offset
3
Op Code Address t 2
1
Irrelevant
Data (Note
1)
4
0
0
Branch Address
1
Irrelevant
Data (Note
1)
1
1
OP Code Address
1
Op Code
2
1
Op Code Address+
1
Branch Offset
3
0
Return
4
1
Stack Pointer
1
Irrelevant
Return
Address (Low Order Byte)
Data (Note
1)
Return
Address (High Order Byte)
5
1
Stack Pointer
– 1
o
0
6
0
0
0
Stack Pointer
– 2
1
Irrelevant
Data (Note
1)
1
Irrelevant
Data (Note
1)
7
Return
Address of Main Program
Irrelevant Data (Note 1 )
1
Subroutine Address
. . ..-.
. . . . -.,
.
. . ,,
.,.
,.,
. . . . . . .- —J.. ,-—
If device which is addressed during this cycle uses VMA,
tnen tne UaTa Bus WIII go TO tne nlgn !mpeaance ~nree-staTe conut~!un.
Depending on bus capacitance, data from the previous cycle may be retained on the Oata Bus.
8
Note 1.
1
Address of Main Program
MOTOROLA
@
Semiconductor
29
Products Inc.
—
I
TABLE
Address Mode
and Instructions
Cycles
Cycle
#
11 –
INDEXEO
VMA
Line
MOOE
CYCLE-BY-CYCLE
R 1~
Line
Address Bus
Deta Bus
I
INDEXED
JMP
4
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
T
1
Op Code Address
2
1
OP Code Address + 1
3
0
Index Register
4
0
Index
T
5
6
STA
6
1
Op Code Address + 1
3
0
Index Register
4
0
1
Index Register Plus Offset
Index Register PI us Offset
1
Op Code Address
2
Op Code Address+
3
Index Register
Index Register Plus Offset
~~y
6
Index Register Plus Offset + 1
~~~$rand Data (Low Order Byte)
,’
Op Code
(w/o Carry)
1
Op Code Address
2
Op Code Address + 1
3
Index Register
4
Index Register Plus Offset
5
Index Register Plus Offset ,,:~j,
‘k
$.\\$&h
Index Register Plus [email protected]?:~
kTi\$ $:~t
Op Code Address
‘i:%,>.
:..,>{:
\“,~b-
3
Index ReQ&er Pyus Offset
,...,,,,,
Index ~{gf$~~{ Plus Offset
5
6
7
T
2
lg{&,~[email protected]#Data (Note
,,,,
.7>.,,
,,+y:>,
B:#
,$<i?!
’.”.,,
(w/o *~/Y)
3$$
‘q;
1)
Oata (Note
1)
Irrelevant
Data
Op Code
Irrelevant
Data (Note
1)
Irrelevant
Data (Note
1)
Operand
(w/o Carry)
Index Resister Plus Offset + 1
1)
(Note 2)
Offset
Irrelevant
Data (Note
1
Irrelevant
Data (Note
1)
1
0
0
1
1
Irrelevant
Data (Note
1)
Op Code
1)
Operand
Data ( High Order Byte)
Operand
Data ( Low Order Byte)
T
Op Code Address
2
Op Code Address+
3
Index Register
1
Irrelevant
4
Stack Pointer
Return
Address ( Low Order Byte)
5
Stack Pointer
Return
Address (High Order Byte)
6
Stack Pointer – 2
7
Index Register
0
0
1
1
1
8
—
1
– 1
Index Register Plus Offset
(w/o Carry)
Op Code
Offset
Data (Note 1 )
Irrelevant
Data (Note
1)
Irrelevant
Data (Note
1)
Irrelevant
Oata (Note
1)
If device which is addressed during this cycle uses VMA, then the Data Bus will go to the high impedance
Oepending on bus capacitance, data from the previous cycle may be retained on the Oata Bus.
Note 2.
For TST, VMA
= O and Operand
three-state
data does not change.
MOTOROLA
@
Data
1
1
1
Note 1.
—
Data
Data (Note
New Operand
Index Register Plus Offset
7
1)
Data (Note
Irrelevant
Index Register Plus Offset
6
Data (Note
Current
Index Register
;@p
Irrelevant
Irrelevant
Operand
(w/o Carry)
1
Index Register Plus Offset
Data (High Order Byte)
Offset
I nde~l.%~,~ter
PI us Offset
.- ‘.~$+t
t#d,* R*gister Plus Offset
.;$:,>~:.,!
?n. S,pt:+f
“
yt{\,
?
‘&p Code Address
Op Code Address+
1)
Offset
Op Code Address’~~%?.?#~
~~.,
~;,\
Index Register
,
‘.:
4
;TS
3TX
1
Index Register Plus Offset
2
?
(w/o Carry)
5
1
LSR
NEG
ROL
ROR
TST
(w/o Carry)
4
6
ASL
ASR
CLR
COM
DEC
INC
Register Plus Offset
Op Code Address
2
5
CPX
LDS
LDX
T
Semiconductor
30
Products
Inc.
condition.
PACKAGE
DIMENSIONS
CASE 711-W
(PLASTIC)
Motorola reserves the right to make changes to any products herein to improve reliability, function or design. Motorola does not assume any Iiabilityarising
out of the application or usa of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
MOTOROLA
@
Semiconductor
31
Products Inc.
I
—
M070ROLA
Semiconductor
@
3501 ED BLUESTEIN BLVD
*,1,,,-,
PR,m,,
,.
“,.
—-.
,-84
1.,,,,0
LI,,m
—
.20206
Products Inc.
AUSTIN, TEXAS 78721
●
A SUBSIDIARY OF MOTOROLA lNC
—
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1s,000
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