Micrel MIC58P42 8-bit serial-input protected latched driver Datasheet

MIC58P42
Micrel
MIC58P42
8-Bit Serial-Input Protected Latched Driver
General Description
Features
The MIC58P42 serial-input latched driver is a high-voltage
(80V), high-current (500mA) integrated circuit comprised of
eight CMOS data latches, a bipolar Darlington transistor
driver for each latch, and CMOS control circuitry for the
common STROBE, CLOCK, SERIAL DATA INPUT, and
OUTPUT ENABLE functions. Similar to the MIC5842, additional protection circuitry supplied on this device includes
thermal shutdown, under voltage lockout (UVLO), and overcurrent shutdown.
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The bipolar/CMOS combination provides an extremely lowpower latch with maximum interface flexibility. The MIC58P42
has open-collector outputs capable of sinking 500 mA and
integral diodes for inductive load transient suppression with
a minimum output breakdown voltage rating of 80V (50V
sustaining). The drivers can be operated with a split supply,
where the negative supply is down to –20V and may be
paralleled for higher load current capability.
3.3 MHz Minimum Data-Input Rate
CMOS, PMOS, NMOS, and TTL Compatible
Internal Pull-Up/Pull-Down Resistors
Low Power CMOS Logic and Latches
High Voltage (80V) Current-Sink Outputs
Output Transient-Protection Diodes
Single or Split Supply Operation
Thermal Shutdown
Under-Voltage Lockout
Per-Output Over-Current Shutdown (500mA typical)
Ordering Information
With a 5V logic supply, the MIC58P42 will typically operate at
better than 5MHz. With a 12V logic supply, significantly
higher speeds are obtained. The CMOS inputs are compatible with standard CMOS, PMOS, and NMOS circuits. TTL
circuits may require pull-up resistors. By using the serial data
output, drivers may be cascaded for interface applications
requiring additional drive lines.
Part Number
Temperature Range
Package
MIC58P42BN
–40°C to +85°C
18-Pin Plastic DIP
MIC58P42BV
–40°C to +85°C
20-Pin PLCC
MIC58P42BWM
–40°C to +85°C
18-Pin Wide SOIC
Each of these eight outputs has an independent over current
shutdown of 500 mA. Upon over-current detection, the
affected channel will turn OFF until VDD is cycled or the
ENABLE/RESET pin is pulsed high. Current pulses less than
2µs will not activate current shutdown. Temperatures above
165°C will shut down the device. The UVLO circuit prevents
operation at low V ; hysteresis of 0.5V is provided. See the
DD
MIC59P60 for a similar device that additionally provides an
error flag output.
Functional Diagram
7
Pin Configuration
(DIP and SOIC)
VEE
18 OUT 1
1
SUB
3
VSS
4
6
SERIAL DATA OUT
5
VDD
7
STROBE
8
OUTPUT
ENABLE/RESET
8-BIT SERIAL–PARALLEL SHIFT REGISTER
LATCHES
UVLO
MOS
BIPOLAR
THERMAL
SHUTDOWN
ILIMIT
10
18
K
OUT 1
17
16
OUT 2 OUT 3
15
14
13
12
11
OUT 4
OUT 5
OUT 6
OUT 7
OUT 8
SUB
1
9
VEE
CLOCK
2
17 OUT 2
SERIAL DATA IN
3
16 OUT 3
VSS
4
VDD
5
SERIAL DATA OUT
6
STROBE
7
12 OUT 7
OUTPUT
ENABLE/RESET
8
11 OUT 8
VEE
9
7-49
14 OUT 5
13 OUT 6
10 K
SUB
I LIMIT
UVLO
October 1998
15 OUT 4
LATCHES
2
SHIFT REGISTER
CLOCK
SERIAL
DATA IN
THERMAL
SHUTDOWN
MIC58P42
Micrel
Absolute Maximum Ratings (Note 1, 2)
PLCC Pin Configuration
SERIAL DATA IN
CLOCK
VEE
OUT 1
OUT 2
at 25°C Free-Air Temperature and VSS = 0V
3
2
1
20
19
NC
4
18
OUT 3
VSS
5
17
OUT 4
VDD
6
16
OUT 5
SERIAL DATA OUT
7
15
OUT 6
NC
8
14
OUT 7
9
10
11
12
13
STROBE
OE/RESET
VEE
K
OUT 8
MIC58P42BV
Output Voltage
Output Voltage, VCE(SUS) (Note 1)
Logic Supply Voltage Range, VDD
VDD with Reference to VEE
Emitter Supply Voltage (Substrate), VEE
Input Voltage Range, VIN
Package Power Dissipation, PD
MIC58P42BN
Derate above TA = +25°C
MIC58P42BV
Derate above TA = +25°C
MIC58P42BWM
Derate above TA = +25°C
Operating Temperature Range, TA
Storage Temperature Range, TS
1.82W
18mW/°C
1.4W
14mW/°C
1.2W
12mW/°C
–55°C to +125°C
–65°C to +150°C
Note 1: For Inductive load applications.
Note 2: CMOS devices have input-static protection but are susceptible to
damage when exposed to extremely high static electrical
charges.
Typical Input Circuits
Typical Output Driver
K
V DD
V DD
80V
50V
4.5V to 15V
25V
–20V
–0.3V to VDD + 0.3V
OUT N
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT
ENABLE
3K
V SS
V EE
V SS
SUB
Pin Description
Pin
Name
Description
1,9
V
Substrate. Most Negative voltage in the system connects here.
2
CLOCK
Serial Data Clock. A CLEAR input must also be clocked into the latches.
3
SERIAL DATA IN
Serial Data Input pin.
4
V
Logic reference (Ground) pin.
5
V
6
SERIAL DATA OUT
Serial Data Output pin. (Flow–through).
7
STROBE
Output Strobe pin. Loads output latches when high. Strobe is needed to clear latch.
8
OUTPUT
ENABLE/RESET
When Low, Outputs are active. When High, device is reset from a fault condition.
10
K
Transient suppression diode's cathode common pin.
11—18
OUTPUT N
Open Collector outputs 8 through 1.
(DIP & S.O.)
EE
SS
DD
Logic Positive Supply voltage.
7-50
October 1998
MIC58P42
Micrel
Electrical Characteristics at TA = +25°C, VDD = 5V, VSS = VEE = 0V (unless otherwise noted)
Limits
Characteristic
Symbol
Test Conditions
Output Leakage Current
ICEX
Max.
Unit
VOUT = 80V
50
µA
VOUT = 80V, TA = +70°C
100
Collector-Emitter
Saturation Voltage
VCE(SAT)
IOUT = 100mA
IOUT = 200mA
IOUT = 350mA
Collector-Emitter
Sustaining Voltage
VCE(SUS)
IOUT = 350mA, L = 2mH
Input Voltage
VIN(0)
Min.
Typ.
0.9
1.1
1.3
1.1
1.3
1.6
50
V
1.0
VIN(1)
VDD = 12V
VDD = 10V
VDD = 5.0V, Note 1
Input Resistance
RIN
VDD = 12V
VDD = 10V
VDD = 5.0V
Supply Current
IDD(ON)
All Drivers ON, VDD = 12V
All Drivers ON, VDD = 10V
All Drivers ON, VDD = 5.0V
6.4
6.0
4.6
10.0
9.0
7.5
IDD (1 ON)
One Driver ON, All others OFF, VDD = 12V
One Driver ON, All others OFF, VDD = 10V
One Driver ON, All others OFF, VDD = 5V
3.1
2.9
2.3
4.5
4.5
3.6
IDD(OFF)
All Drivers OFF, VDD = 12V
All Drivers OFF, VDD = 10V
All Drivers OFF, VDD = 5.0V
2.6
2.4
1.9
4.2
3.6
3.0
Clamp Diode
Leakage Current
IR
VR = 80V
Clamp Diode
Forward Voltage
VF
IF = 350mA
Output Current
Shutdown Threshold
ILIM
Start Up Voltage
VSU
Minimum Supply (VDD)
VDD MIN
V
10.5
8.5
3.5
50
50
50
200
300
600
1.7
kΩ
mA
50
µA
2.0
V
500
Note 2
V
mA
3.5
4.0
4.5
V
3.0
3.5
4.0
V
Thermal Shutdown
165
°C
Thermal Shutdown Hysteresis
10
°C
Note 1: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to insure a minimum logic "1".
Note 2: Undervoltage Lockout is guaranteed to release device at no more than 4.5V, and disable the device at no less than 3.0V.
October 1998
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7
MIC58P42
Micrel
CLOCK
A
D
B
DATA IN
E
F
C
STROBE
OUTPUT
ENABLE
G
OUT N
Timing Conditions
(TA = +25°C, Logic Levels are VDD and VSS), VDD = 5V
A.
B.
C.
D.
E.
F.
G.
Typical Data Active Time Before Clock Pulse (Data Set-Up Time) ........................................................................... 75 ns
Minimum Data Active Time After Clock Pulse (Data Hold Time) .............................................................................. 75 ns
Minimum Data Pulse Width ..................................................................................................................................... 150 ns
Minimum Clock Pulse Width .................................................................................................................................... 150 ns
Minimum Time Between Clock Activation and Strobe ............................................................................................. 300 ns
Minimum Strobe Pulse Width ................................................................................................................................... 100 ns
Typical Time Between Strobe Activation and Output Transition ............................................................................. 500 ns
SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL
DATA must appear at the input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion).
The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed
(STROBE tied high) will require that the ENABLE input be high to prevent invalid output states.
When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the latches
or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches. A positive OUTPUT ENABLE/
RESET pulse resets the output after a current shutdown fault. Thermal limit faults are not latched and require no reset pulse.
MIC58P42 Truth Table
Shift Register Contents
Serial Data
Input
Clock
Input
I1
I2
I3 ……
I8
Serial
Data
Output
Latch Contents
Strobe
Input
I1
I2
I3
……
Output Contents
Output
I8 Enable I1 I2
I3 …… I8
H
H
R1
R2 ……
R7
R7
L
L
R1
R2 ……
R7
R7
X
R1
R2
R3 ……
R8
R8
O
O
O ……
O
L
X
X
X ……
X
X
L
R1 R2
R3
……
R8
P1
P2
P3 ……
P8
P8
H
P1 P2
P3
……
P8
L
P1
P2
P3 ……P8
X
X
……
X
H
H
H
H …… H
X
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
O = Output OFF
7-52
October 1998
MIC58P42
Micrel
0
50
100
TEMPERATURE (°C)
Output Delay
vs. Supply Voltage
RL = 50Ω
250
200
150
TD OFF
100
TD ON
50
5
7
9
11
13
15
SUPPLY VOLTAGE (VDD)
ALL OUTPUTS ON
4
VDD = 5V
3
2
ALL OUTPUTS OFF
1
0
–50
150
SHUTDOWN THRESHOLD (A)
0.6
0.5
–50
IL = 100mA
0.60
0
50
100
TEMPERATURE (°C)
150
0.55
VDD = 5V
0.50
0.40
0.35
–50
Supply Current
vs. Temperature
7
6
ALL OUTPUTS ON
5
VDD = 12V
4
3
ALL OUTPUTS OFF
2
1
0
–50
0
50
100
TEMPERATURE (°C)
150
VDD = 12V
0.45
CURRENT LIMIT DELAY (µs)
VDD = 5V to 12V
0.9
0.8
0.7
300
OUTPUT DELAY (ns)
IL = 350mA
1.2
1.1
1
Current Shutdown
Threshold vs. Temperature
Supply Current
vs. Temperature
5
SUPPLY CURRENT (mA)
1.5
1.4
1.3
Output Saturation
Voltage vs. Temperature
SUPPLY CURRENT (mA)
SATURATION VOLTAGE (V)
Typical Characteristic Curves
20
18
16
0
50
100
TEMPERATURE (°C)
150
Current Shutdown
Delay vs. Output Current
14
12
10
8
6
VDD = 12V
4
VDD = 5V
2
0
0.3 0.4 0.5 0.6 0.7 0.8 0.9
OUTPUT CURRENT (A)
Maximum Allowable Duty Cycle, Plastic DIP
VDD = 5.0V
VDD = 12V
October 1998
Number of Outputs ON
(IOUT = 200mA
Max. Allowable Duty Cycle at Ambient Temperature of:
VDD = 5.0V)
25°C
40°C
50°C
60°C
70°C
8
85%
72%
64%
55%
46%
7
97%
82%
73%
63%
53%
6
100%
96%
85%
73%
62%
5
100%
100%
100%
88%
75%
4
100%
100%
100%
100%
93%
3
100%
100%
100%
100%
100%
2
100%
100%
100%
100%
100%
1
100%
100%
100%
100%
100%
Number of Outputs ON
(IOUT = 200mA
Max. Allowable Duty Cycle at Ambient Temperature of:
VDD = 12V)
25°C
40°C
50°C
60°C
70°C
8
80%
68%
60%
52%
44%
7
91%
77%
68%
59%
50%
6
100%
90%
79%
69%
58%
5
100%
100%
95%
82%
69%
4
100%
100%
100%
100%
86%
3
100%
100%
100%
100%
100%
2
100%
100%
100%
100%
100%
1
100%
100%
100%
100%
100%
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