LINER LTC3405A-1.375 1.375v, 1.5mhz, 300ma synchronous step-down regulators in thinsot Datasheet

LTC3405A-1.375
1.375V, 1.5MHz, 300mA
Synchronous Step-Down
Regulators in ThinSOT
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FEATURES
DESCRIPTIO
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The LTC ®3405A-1.375 is a high efficiency monolithic
synchronous buck regulator using a constant frequency,
current mode architecture. Supply current during operation is only 20µA and drops to <1µA in shutdown. The 2.5V
to 5.5V input voltage range makes the LTC3405A-1.375
ideally suited for single Li-Ion battery-powered applications. 100% duty cycle provides low dropout operation,
extending battery life in portable systems.
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High Efficiency: Up to 90%
Very Low Quiescent Current: Only 20µA
During Operation
300mA Output Current at VIN = 3V
2.5V to 5.5V Input Voltage Range
1.5MHz Constant Frequency Operation
No Schottky Diode Required
Low Dropout Operation: 100% Duty Cycle
Stable with Ceramic Capacitors
Shutdown Mode Draws < 1µA Supply Current
±3% Output Voltage Accuracy
Current Mode Operation for Excellent Line and
Load Transient Response
Overtemperature Protected
Low Profile (1mm) ThinSOTTM Package
Switching frequency is internally set at 1.5MHz, allowing
the use of small surface mount inductors and capacitors.
The LTC3405A-1.375 is specifically designed to work well
with ceramic output capacitors, achieving very low output
voltage ripple and a small PCB footprint.
The internal synchronous switch increases efficiency and
eliminates the need for an external Schottky diode. The
LTC3405A-1.375 is available in a low profile (1mm)
ThinSOT package.
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APPLICATIO S
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Cellular Telephones
Personal Information Appliances
Wireless and DSL Modems
Digital Still Cameras
MP3 Players
Portable Instruments
For other output voltages, refer to the LTC3405A and
LTC3405A-1.5/LTC3405A-1.8 data sheets.
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode
is a registered trademark of Linear Technology Corporation. ThinSOT is a trademark of
Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815,
6498466, 6611131.
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TYPICAL APPLICATIO
100
90
CIN
4.7µF
CER
VIN
VOUT
1.375V
300mA
SW
LTC3405A-1.375
COUT
4.7µF
CER
RUN
MODE
GND
VOUT
3405A1375 F01
80
EFFICIENCY (%)
VIN
2.7V
TO 5.5V
4.7µH
70
60
50
VIN = 2.7V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
40
30
0.1
10
100
1
OUTPUT CURRENT (mA)
1000
3405A1375 F01b
Figure 1a. High Efficiency Step-Down Converter
Figure 1b. Efficiency vs Load Current
3405a1375f
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LTC3405A-1.375
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
Input Supply Voltage .................................. – 0.3V to 6V
MODE, RUN, VOUT Voltages....................... – 0.3V to VIN
SW Voltage .................................. – 0.3V to (VIN + 0.3V)
P-Channel Switch Source Current (DC) ............. 400mA
N-Channel Switch Sink Current (DC) ................. 400mA
Peak SW Sink and Source Current .................... 630mA
Operating Temperature Range (Note 2) .. – 40°C to 85°C
Junction Temperature (Note 3) ............................ 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
TOP VIEW
RUN 1
6 MODE
GND 2
5 VOUT
SW 3
4 VIN
LTC3405AES6-1.375
S6 PART MARKING
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
LTBRP
TJMAX = 125°C, θJA = 250°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 3.6V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IPK
Peak Inductor Current
VIN = 3V, VOUT = 1.238V, Duty Cycle < 35%
375
500
625
mA
VOUT
Regulated Output Voltage
MODE = 3.6V
1.334
1.375
1.416
V
∆VOVL
∆Output Overvoltage Lockout
∆VOVL = VOVL – VOUT
2
5.6
9.3
%
∆VOUT
Output Voltage Line Regulation
VIN = 2.5V to 5.5V
0.04
0.4
%/V
VLOADREG
Output Voltage Load Regulation
VIN
Input Voltage Range
IS
Input DC Bias Current
Pulse Skipping Mode
Burst Mode® Operation
Shutdown
(Note 4)
VOUT = 1.238V, MODE = 3.6V, ILOAD = 0A
VOUT = 1.42V, MODE = 0V, ILOAD = 0A
VRUN = 0V, VIN = 4.2V
fOSC
Oscillator Frequency
VOUT = 1.375V
VOUT = 0V
RPFET
RDS(ON) of P-Channel FET
RNFET
●
●
0.5
●
%
5.5
V
300
20
0.1
400
35
1
µA
µA
µA
1.5
170
1.8
MHz
kHz
ISW = 100mA
0.7
0.85
Ω
RDS(ON) of N-Channel FET
ISW = –100mA
0.6
0.90
Ω
ILSW
SW Leakage
VRUN = 0V, VSW = 0V or 5V, VIN = 5V
±0.01
±1
µA
VRUN
RUN Threshold
●
1
1.5
V
IRUN
RUN Leakage Current
●
±0.01
±1
µA
VMODE
MODE Threshold
●
IMODE
MODE Leakage Current
●
Burst Mode is a registered trademark of Linear Technology Corporation.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3405A-1.375 is guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
●
2.5
1.2
0.3
0.3
1.5
2
V
±0.01
±1
µA
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
LTC3405A-1.375: TJ = TA + (PD)(250°C/W)
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
3405a1375f
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LTC3405A-1.375
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TYPICAL PERFOR A CE CHARACTERISTICS
TA = 25°C unless otherwise noted.
(From Figure1a)
Efficiency vs Input Voltage
100
100
Burst Mode OPERATION
90
80
90
80
IOUT = 0.1mA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 250mA
60
80
70
50
EFFICIENCY (%)
70
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Output Current
Efficiency vs Output Current
90
PULSE SKIPPING MODE
60
50
40
3.6V
4.2V
3.6V
4.2V
20
Burst Mode OPERATION
10
30
2.5
3.0
3.5
4.0
4.5
LOAD CURRENT (mA)
5.0
0
0.1
5.5
60
50
30
40
70
40
30
0.1
1000
1
100
10
OUTPUT CURRENT (mA)
VIN = 2.7V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
10
100
1
OUTPUT CURRENT (mA)
1000
3405A1375 G03
3405A1375 G01
3405A1375 G02
Oscillator Frequency vs
Supply Voltage
Oscillator Frequency vs
Temperature
1.70
Output Voltage vs Load Current
1.395
1.8
VIN = 3.6V
1.55
1.50
1.45
1.40
1.35
50
25
75
0
TEMPERATURE (°C)
100
125
1.7
1.385
1.6
1.5
1.4
1.2
Burst Mode
OPERATION
1.375
PULSE SKIPPING MODE
1.365
1.355
1.3
1.345
2
3
4
5
SUPPLY VOLTAGE (V)
6
0
100
400
200
300
CURRENT LOAD (mA)
500
3405A1375 G05
3405A1375 G04
3405A1375 G06
RDS(ON) vs Input Voltage
RDS(ON) vs Temperature
1.2
1.2
1.1
VIN = 4.2V
1.0
1.0 V = 2.7V
IN
0.9
MAIN SWITCH
0.8
0.7
0.6
SYNCHRONOUS
SWITCH
0.5
VIN = 3.6V
0.8
RDS(ON) (Ω)
1.30
–50 –25
RDS(0N) (Ω)
FREQUENCY (MHz)
1.60
OUTPUT VOLTAGE (V)
OSCILLATOR FREQUENCY (MHz)
1.65
0.4
0.6
0.4
0.3
0.2
0.2
SYNCHRONOUS SWITCH
MAIN SWITCH
0.1
0
0
1
3
2
5
4
INPUT VOLTAGE (V)
6
7
3405A1375 G07
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
3405A1375 G08
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LTC3405A-1.375
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TYPICAL PERFOR A CE CHARACTERISTICS
TA = 25°C unless otherwise noted.
(From Figure 1a)
Dynamic Supply Current
vs Supply Voltage
Dynamic Supply Current
vs Temperature
1600
VIN = 3.6V
300 ILOAD = 0A
1200
260
SUPPLY CURRENT (µA)
1000
800
600
400
PULSE SKIPPING MODE
VIN = 5.5V
140 RUN = 0V
PULSE SKIPPING MODE
220
180
140
100
SWITCH LEAKAGE (nA)
1400
ILOAD = 0A
SUPPLY CURRENT (µA)
Switch Leakage vs Temperature
160
340
60
200
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
20
0
–50 –25
5.5
SUPPLY VOLTAGE (V)
50
25
75
0
TEMPERATURE (°C)
3405A1375 G09
100
80
60
SYNCHRONOUS
SWITCH
40
MAIN SWITCH
20
Burst Mode OPERATION
Burst Mode OPERATION
120
100
0
–50 –25
125
50
25
75
0
TEMPERATURE (°C)
125
3405A1375 G11
3405A1375 G10
Switch Leakage vs Input Voltage
100
Pulse Skipping Mode Operation
Burst Mode Operation
60
RUN = 0V
SWITCH LEAKAGE (pA)
50
SW
5V/DIV
SW
5V/DIV
VOUT
100mV/DIV
AC COUPLED
VOUT
10mV/DIV
SYNCHRONOUS
SWITCH
40
30
20
IL
100mA/DIV
MAIN SWITCH
IL
100mA/DIV
10
0
0
1
5
2
3
4
INPUT VOLTAGE (V)
6
VIN = 3.6V
ILOAD = 20mA
VIN = 3.6V
ILOAD = 20mA
5µs/DIV
500ns/DIV
3405A1375 G14
3405A1375 G13
3405A1375 G12
Start-Up from Shutdown
Load Step
VOUT
100mV/DIV
AC
COUPLED
RUN
2V/DIV
VOUT
1V/DIV
IL
200mA/DIV
IL
200mA/DIV
ILOAD
200mA/DIV
VIN = 3.6V
ILOAD = 200mA
VIN = 3.6V
20µs/DIV
ILOAD = 0mA TO 250mA
PULSE SKIPPING MODE
40µs/DIV
3405A1375 G15
3405A1375 G16
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LTC3405A-1.375
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TYPICAL PERFOR A CE CHARACTERISTICS
TA = 25°C unless otherwise noted.
(From Figure 1a)
Load Step
Load Step
Load Step
VOUT
100mV/DIV
AC
COUPLED
VOUT
100mV/DIV
AC
COUPLED
IL
200mA/DIV
IL
200mA/DIV
IL
200mA/DIV
ILOAD
200mA/DIV
ILOAD
200mA/DIV
ILOAD
200mA/DIV
VOUT
100mV/DIV
AC
COUPLED
VIN = 3.6V
20µs/DIV
ILOAD = 20mA TO 250mA
PULSE SKIPPING MODE
VIN = 3.6V
20µs/DIV
ILOAD = 0mA TO 250mA
Burst Mode OPERATION
VIN = 3.6V
20µs/DIV
ILOAD = 20mA TO 250mA
Burst Mode OPERATION
3405A1375 G17
3405A1375 G18
3405A1375 G19
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PI FU CTIO S
RUN (Pin 1): Run Control Input. Forcing this pin above
1.5V enables the part. Forcing this pin below 0.3V shuts
down the device. In shutdown, all functions are disabled
drawing <1µA supply current. Do not leave RUN floating.
VIN (Pin 4): Main Supply Pin. Must be closely decoupled
to GND, Pin 2, with a 2.2µF or greater ceramic capacitor.
GND (Pin 2): Ground Pin.
VOUT (Pin 5): Output Voltage Feedback Pin. An internal
resistive divider divides the output voltage down for comparison to the internal 0.9V reference voltage.
SW (Pin 3): Switch Node Connection to Inductor. This pin
connects to the drains of the internal main and synchronous power MOSFET switches.
MODE (Pin 6): Mode Select Input. To select pulse skipping mode, tie to VIN. Grounding this pin selects Burst
Mode operation. Do not leave this pin floating.
3405a1375f
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LTC3405A-1.375
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FU CTIO AL DIAGRA
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MODE
6
SLOPE
COMP
0.65V
OSC
OSC
4 VIN
FREQ
SHIFT
VOUT
–
5
+
R1
95k
0.9V
0.4V
– EA
R2
180k
–
+
SLEEP
S
Q
R
Q
RS LATCH
RUN
–
OVDET
0.95V
ICOMP
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
ANTISHOOTTHRU
3 SW
OV
+
+
0.9V REF
5Ω
+
–
+
BURST
VFB
VIN
1
EN
SHUTDOWN
IRCMP
2 GND
–
3405A1375 BD
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OPERATIO (Refer to Functional Diagram)
Main Control Loop
The LTC3405A-1.375 uses a constant frequency, current
mode step-down architecture. The main (P-channel
MOSFET) and synchronous (N-channel MOSFET) switches
are internal. During normal operation, the internal top
power MOSFET is turned on each cycle when the oscillator
sets the RS latch, and turned off when the current comparator, ICOMP, resets the RS latch. The peak inductor
current at which ICOMP resets the RS latch, is controlled by
the output of error amplifier EA. When the load current
increases, the output voltage decreases which causes a
slight decrease in VFB relative to the 0.9V reference, which
in turn, causes the EA amplifier’s output voltage to increase until the average inductor current matches the new
load current. While the top MOSFET is off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse, as indicated by the current reversal
comparator IRCMP, or the beginning of the next clock cycle.
Comparator OVDET guards against transient overshoots
> 5.6% by turning the main switch off and keeping it off
until the fault is removed.
Burst Mode Operation
The LTC3405A-1.375 is capable of Burst Mode operation
in which the internal power MOSFETs operate intermittently based on load demand. To enable Burst Mode
operation, simply connect the MODE pin to GND. To
disable Burst Mode operation and enable PWM pulse
skipping mode, connect the MODE pin to VIN or drive it
with a logic high (VMODE > 1.5V). In this mode, the
efficiency is lower at light loads, but becomes comparable
to Burst Mode operation when the output load exceeds
25mA. The advantage of pulse skipping mode is lower
output ripple and less interference to audio circuitry.
3405a1375f
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LTC3405A-1.375
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OPERATIO (Refer to Functional Diagram)
When the converter is in Burst Mode operation, the peak
current of the inductor is set to approximately 100mA regardless of the output load. Each burst event can last from
a few cycles at light loads to almost continuously cycling
with short sleep intervals at moderate loads. In between
these burst events, the power MOSFETs and any unneeded
circuitry are turned off, reducing the quiescent current to
20µA. In this sleep state, the load current is being supplied
solely from the output capacitor. As the output voltage
droops, the EA amplifier’s output rises above the sleep
threshold signaling the BURST comparator to trip and turn
the top MOSFET on. This process repeats at a rate that is
dependent on the load demand.
Short-Circuit Protection
When the output is shorted to ground, the frequency of the
oscillator is reduced to about 210kHz, 1/7 the nominal
frequency. This frequency foldback ensures that the
inductor current has more time to decay, thereby preventing runaway. The oscillator’s frequency will progressively
increase to 1.5MHz when VOUT rises above 0V.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. Normally, this
results in a reduction of maximum inductor peak current
for duty cycles > 40%. However, the LTC3405A-1.375
uses a patented scheme that counteracts this compensating ramp, which allows the maximum inductor peak
current to remain unaffected throughout all duty cycles.
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APPLICATIO S I FOR ATIO
The basic LTC3405A-1.375 application circuit is shown in
Figure 1. External component selection is driven by the
load requirement and begins with the selection of L
followed by CIN and COUT.
Inductor Selection
For most applications, the inductor value will fall in the
range of 2.2µH to 10µH. Its value is determined by the
desired ripple current. Large value inductors lower ripple
current and small value inductors result in higher ripple
currents. Higher VIN or VOUT also increases the ripple
current as shown in equation 1. A reasonable starting point
for setting ripple current is ∆IL = 120mA (40% of 300mA).
∆IL =
⎛ V ⎞
VOUT ⎜ 1 − OUT ⎟
VIN ⎠
⎝
f L
1
( )( )
(1)
The DC current rating of the inductor should be at least
equal to the maximum load current plus half the ripple
current to prevent core saturation. Thus, a 360mA rated
inductor should be enough for most applications (300mA
+ 60mA). For better efficiency, choose a low DC-resistance
inductor.
The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the inductor current peaks fall to approximately
100mA. Lower inductor values (higher ∆IL) will cause this
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
Inductor Core Selection
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials
are small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
electrical characteristics. The choice of which style inductor to use often depends more on the price vs size
requirements and any radiated field/EMI requirements
than on what the LTC3405A-1.375 requires to operate.
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LTC3405A-1.375
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APPLICATIO S I FOR ATIO
Table 1 shows some typical surface mount inductors that
work well in LTC3405A-1.375 applications.
Table 1. Representative Surface Mount Inductors
MANUFACTURER PART NUMBER
MAX DC
VALUE CURRENT DCR HEIGHT
Taiyo Yuden
LB2016T2R2M
LB2012T2R2M
LB2016T3R3M
2.2µH
2.2µH
3.3µH
315mA
240mA
280mA
0.13Ω 1.6mm
0.23Ω 1.25mm
0.2Ω 1.6mm
Panasonic
ELT5KT4R7M
4.7µH
950mA
0.2Ω 1.2mm
Murata
LQH32CN2R2M33 4.7µH
450mA
0.2Ω
Taiyo Yuden
LB2016T4R7M
4.7µH
210mA
0.25Ω 1.6mm
Panasonic
ELT5KT6R8M
6.8µH
760mA
0.3Ω 1.2mm
Panasonic
ELT5KT100M
10µH
680mA
0.36Ω 1.2mm
Sumida
CMD4D116R8MC 6.8µH
620mA
0.23Ω 1.2mm
2mm
CIN and COUT Selection
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle VOUT/VIN. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
RMS capacitor current is given by:
CIN required IRMS ≅ IOMAX
[V (V
OUT
IN − VOUT
1/ 2
)]
VIN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that the capacitor
manufacturer’s ripple current ratings are often based on
2000 hours of life. This makes it advisable to further derate
the capacitor, or choose a capacitor rated at a higher
temperature than required. Always consult the manufacturer if there is any question.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating
generally far exceeds the IRIPPLE(P-P) requirement. The
output ripple ∆VOUT is determined by:
⎛
1 ⎞
∆VOUT ≅ ∆IL ⎜ ESR +
⎟
8 fCOUT ⎠
⎝
where f = operating frequency, COUT = output capacitance
and ∆IL = ripple current in the inductor. For a fixed output
voltage, the output ripple is highest at maximum input
voltage since ∆IL increases with input voltage.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount configurations. In the case
of tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. An excellent choice is
the AVX TPS series of surface mount tantalum. These are
specially constructed and tested for low ESR so they give
the lowest ESR for a given volume. Other capacitor types
include Sanyo POSCAP, Kemet T510 and T495 series, and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. Because the
LTC3405A-1.375’s control loop does not depend on the
output capacitor’s ESR for stable operation, ceramic capacitors can be used freely to achieve very low output
ripple and small circuit size.
Care must be taken when ceramic capacitors are used at
the input and the output. When a ceramic capacitor is used
at the input and the power is supplied by a wall adapter
through long wires, a load step at the output can induce
ringing at the input, VIN. At best, this ringing can couple to
the output and be mistaken as loop instability. At worst, a
sudden inrush of current through the long wires can
potentially cause a voltage spike at VIN, large enough to
damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.
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LTC3405A-1.375
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APPLICATIO S I FOR ATIO
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3405A-1.375 circuits: VIN quiescent current
and I2R losses. The VIN quiescent current loss dominates
the efficiency loss at very low load currents whereas the
I2R loss dominates the efficiency loss at medium to high
load currents. In a typical efficiency plot, the efficiency
curve at very low load currents can be misleading since the
actual power lost is of no consequence as illustrated in
Figure 2.
1
VIN = 3.6V
POWER LOST (W)
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I2R losses, simply add RSW to
RL and multiply the result by the square of the average
output current.
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
0.1
Thermal Considerations
0.01
0.001
0.0001
0.1
the DC bias current. In continuous mode, IGATECHG =
f(QT + QB) where QT and QB are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to VIN and thus
their effects will be more pronounced at higher supply
voltages.
1
100
10
LOAD CURRENT (mA)
1000
3405A1375 F02
Figure 2. Power Lost vs Load Current
1. The VIN quiescent current is due to two components:
the DC bias current as given in the electrical characteristics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from VIN to ground. The resulting
dQ/dt is the current out of VIN that is typically larger than
In most applications, the LTC3405A-1.375 does not
dissipate much heat due to its high efficiency. But, in
applications where they run at high ambient temperature
with low supply voltage, the heat dissipated may exceed
the maximum junction temperature of the part. If the
junction temperature reaches approximately 150°C, both
power switches will be turned off and the SW node will
become high impedance.
To keep the LTC3405A-1.375 from exceeding the maximum junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The temperature rise is given by:
TR = (PD)(θJA)
3405a1375f
9
LTC3405A-1.375
U
W
U U
APPLICATIO S I FOR ATIO
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, TJ, is given by:
TJ = TA + TR
where TA is the ambient temperature.
As an example, consider the LTC3405A-1.375 with an
input voltage of 2.7V, a load current of 300mA and an
ambient temperature of 70°C. From the typical performance graph of switch resistance, the RDS(ON) of the Pchannel switch at 70°C is approximately 0.94Ω and the
RDS(ON) of the N-channel synchronous switch is approximately 0.75Ω.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3405A-1.375. These items are also illustrated graphically in Figures 3 and 4. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the VIN trace should be kept short, direct and
wide.
2. Does the (+) plate of CIN connect to VIN as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
3. Keep the (–) plates of CIN and COUT as close as possible.
The series resistance looking into the SW pin is:
RSW = 0.95Ω (0.51) + 0.75Ω (0.49) = 0.85Ω
1
Therefore, power dissipated by the part is:
RUN
MODE
LTC3405A-1.375
2
PD = ILOAD2 • RSW = 76.5mW
–
GND
VOUT
3
+
L1
SW
VIN
VIN
3405A1375 F03
BOLD LINES INDICATE HIGH CURRENT PATHS
which is well below the maximum junction temperature of
125°C.
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD • ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT, which generates a feedback error signal.
The regulator loop then acts to return VOUT to its steadystate value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
4
CIN
TJ = 70°C + (0.0765)(250) = 89.1°C
Checking Transient Response
5
COUT
VOUT
For the SOT-23 package, the θJA is 250°C/ W. Thus, the
junction temperature of the regulator is:
Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)).
6
Figure 3. LTC3405A-1.375 Layout Diagram
Design Example
As a design example, assume the LTC3405A-1.375 is
used in a single lithium-ion battery-powered cellular phone
application. The VIN will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.15A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
and high load currents is important. Output voltage is
1.375V. With this information we can calculate L using
equation (1),
L=
⎛ V ⎞
VOUT ⎜ 1 − OUT ⎟
VIN ⎠
⎝
f ∆IL
1
( )( )
(3)
3405a1375f
10
LTC3405A-1.375
U
W
U U
APPLICATIO S I FOR ATIO
100
Substituting VOUT = 1.375V, VIN = 4.2V, ∆IL = 60mA and
f = 1.5MHz in equation (3) gives:
80
70
⎛ 1.375V ⎞
1.375V
⎜1 −
⎟ ≅ 10µH
1.5MHz(60mA) ⎝
4.2V ⎠
EFFICIENCY (%)
L=
90
60
50
40
30
20
VIA TO VIN
VIN = 2.7V
VIN = 3.6V
VIN = 4.2V
10
VIN
VOUT
PIN 1
0
0.1
1
10
100
LOAD CURRENT (mA)
LTC3405A-1.375
3405A1375 F05b
Figure 5b. LTC3405A-1.375 Small Footprint Efficiency
SW
L1
1000
COUT
CIN
GND
3405A1518 F04
Figure 4. LTC3405A-1.375 Suggested Layout
For best efficiency choose a 200mA or greater inductor
with less than 0.3Ω series resistance.
CIN will require an RMS current rating of at least 0.125A
≅ ILOAD(MAX)/2 at temperature and COUT will require an
ESR of less than 0.5Ω. In most cases, a ceramic capacitor
will satisfy this requirement.
Figure 5 shows the complete circuit along with its efficiency curve.
VIN
2.7V
TO 4.2V
4
CIN***
2.2µF
CER
VIN
SW
3
LTC3405A-1.375
1
6
RUN
VOUT
MODE
GND
2
5
10µH*
VOUT
100mV/DIV
AC
COUPLED
IL
200mA/DIV
ILOAD
200mA/DIV
VIN = 3.6V
20µs/DIV
ILOAD = 100mA TO 300mA
Burst Mode OPERATION
3405A1375 F05c
Figure 5c.
VOUT
1.375V
COUT**
10µF
CER
* MURATA LQHMCN10002
** MURATA 0603 GRM188R60G106ME47B
*** MURATA 0603 GRM188R61A225KE34B
3405A1375 F05a
Figure 5a. Small Footprint Application
3405a1375f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC3405A-1.375
U
PACKAGE DESCRIPTIO
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC
(NOTE 4)
0.754
0.854 ± 0.127
0.20 BSC
DATUM ‘A’
2.80 BSC
3.254
1.50 – 1.75
(NOTE 4)
0.30 – 0.50 REF
PIN ONE ID
0.09 – 0.20
(NOTE 3)
0.95 BSC
0.80 – 0.90
1.9 BSC
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
0.01 – 0.10
1.00 MAX
RECOMMENDED SOLDER PAD LAYOUT
0.95 BSC
0.30 – 0.45 TYP
6 PLCS (NOTE 3)
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
0.30 – 0.45 TYP
6 PLCS (NOTE 3)
1.90 BSC
S6 TSOT-23 0801
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3405a1375f
12
Linear Technology Corporation
LT/LT 0305 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2002
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