IDT IDT70V3399S166BF High-speed 3.3v 256/128k x 18 synchronous dual-port static ram with 3.3v or 2.5v interface Datasheet

HIGH-SPEED 3.3V
256/128K x 18
IDT70V3319/99S
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆
◆
◆
◆
◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
– Due to limited pin count PL/FT option is not supported
on the 128-pin TQFP package. Device is pipelined
outputs only on each port.
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (6Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output mode
LVTTL- compatible, single 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz.
Available in a 128-pin Thin Quad Flatpack, 208-pin fine
pitch Ball Grid Array, and 256-pin Ball
Grid Array
Supports JTAG features compliant to IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
128-pin TQFP package.
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◆
◆
◆
Functional Block Diagram
FT/PIPEL
UBL
UBR
LBL
LBR
1/0
0a 1a
0b 1b
1b 0b
1a 0a
a
b
b
a
FT/PIPER
1/0
R/WL
R/WR
CE0L
CE1L
CE0R
CE1R
1
1
B B
WW
0 1
L L
0
1/0
B B
WW
1 0
R R
Dout0-8_L
Dout9-17_L
OEL
0
1/0
Dout0-8_R
Dout9-17_R
OER
,
0a 1a 0b 1b
1b 0b 1a 0a
FT/PIPEL
FT/PIPE R
0/1
0/1
ab
ba
256K x 18
MEMORY
ARRAY
Din_L
I/O0L - I/O17L
I/O0R - I/O17R
Din_R
CLKR
CLKL
A0L
REPEATL
ADSL
CNTENL
Counter/
Address
Reg.
Counter/
Address
Reg.
ADDR_R
ADDR_L
TDI
NOTE:
1. A17 is a NC for IDT70V3399.
,
A17R(1)
A17L(1)
JTAG
TDO
TCK
TMS
TRST
A0R
REPEATR
ADSR
CNTENR
5623 tbl 01
MAY 2003
1
©2003 Integrated Device Technology, Inc.
DSC 5623/7
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Description:
The IDT70V3319/99 is a high-speed 256/128K x 18 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70V3319/99 has been optimized for applications having unidirectional
Industrial and Commercial Temperature Ranges
or bidirectional data flow in bursts. An automatic power down feature,
controlled by CE0 and CE1, permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70V3319/99 can support an operating voltage of either 3.3V or
2.5V on one or both ports, controllable by the OPT pins. The power supply
for the core of the device (VDD) remains at 3.3V.
Pin Configuration(1,2,3,4,5)
08/01/02
1
2
3
4
5
6
7
8
9
10 11
12
13 14
15
16 17
I/O9L
NC
VSS
TDO
NC
A16L
A12L
A8L
NC
VDD
CLKL
CNTENL
A4L
A0L
OPTL
NC
VSS
A
NC
VSS
NC
TDI
A17L(1)
A13L
A9L
NC
CE0L
VSS
ADSL
A5L
A1L
VSS
VDDQR
I/O8L
NC
B
VDDQL
I/O9R
VDDQR PIPE/FTL
NC
A14L
A10L
UBL
CE1L
VSS
R/WL
A6L
A2L
VDD
I/O8R
NC
VSS
C
NC
VSS
I/O10L
A15L
A11L
A7L
LBL
VDD
OEL
REPEATL
A3L
VDD
NC
VDDQL
I/O7L
I/O7R
D
I/O11L
NC
VDDQR I/O10R
I/O6L
NC
VSS
NC
E
VDDQL
I/O11R
NC
VSS
VSS
I/O6R
NC
VDDQR
F
NC
VSS
I/O12L
NC
NC
VDDQL
I/O5L
NC
G
VDD
NC
VDDQR I/O12R
VDD
NC
VSS
I/O5R
H
VDDQL
VDD
VSS
VSS
VSS
VDD
VSS
VDDQR
J
I/O14R
VSS
I/O13R
VSS
I/O3R
VDDQL
I/O4R
VSS
K
NC
I/O14L
VDDQR
I/O13L
NC
I/O3L
VSS
I/O4L
L
VDDQL
NC
I/O15R
VSS
VSS
NC
I/O2R
VDDQR
M
NC
VSS
NC
I/O15L
I/O1R
VDDQL
NC
I/O2L
N
I/O16R
I/O16L
VDDQR
NC
TRST
A16R
A12R
A8R
NC
VDD
CLKR
CNTEN R
A4R
NC
I/O1L
VSS
NC
P
VSS
NC
I/O17R
TCK
A17R(1)
A13R
A9R
NC
CE0R
VSS
ADSR
A5R
A1R
VSS
VDDQL
I/O0R
VDDQR
R
NC
I/O17L
VDDQL
TMS
NC
A14R
A10R
UBR
CE1R
VSS
R/WR
A6R
A2R
VSS
NC
VSS
NC
T
VSS
NC
PIPE/FTR
NC
A15R
A11R
A7R
LBR
VDD
A3R
A0R
VDD
OPTR
NC
I/O0L
U
NC
70V3319/99BF
BF-208(6)
208-Pin fpBGA
Top View(7)
OER REPEATR
5623 drw 02c
NOTES:
1. A17 is a NC for IDT70V3399.
2. All VDD pins must be connected to 3.3V power supply.
3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
4. All VSS pins must be connected to ground supply.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4,5) (con't.)
70V3319/99BC
BC-256(6)
256-Pin BGA
Top View(7)
08/01/02
A1
NC
B1
NC
C1
NC
D1
NC
E1
A2
TDI
B2
NC
C2
I/O9L
D2
I/O9R
E2
I/O10R I/O10L
F1
F2
I/O11L
G1
NC
H1
NC
J1
NC
G2
NC
H2
I/O12R
J2
A3
NC
B3
TDO
C3
VSS
D3
NC
E3
NC
F3
A4
B4
NC
C4
A16L
D4
E4
VDDQL
F4
G4
I/O12L VDDQR
H3
NC
J3
H4
NC
L1
I/O15L
M1
K2
NC
L2
NC
M2
I/O16R I/O16L
N1
NC
P1
NC
R1
NC
T1
NC
N2
I/O17R
P2
K3
J4
NC
T2
TCK
C5
A13L
D5
E5
VDD
F5
VDD
G5
VSS
H5
L4
J5
VSS
K5
VSS
L5
I/O15R VDDQR VDD
M3
NC
N3
NC
P3
I/O17L TMS
R2
K4
I/O14L VDDQL
L3
A15L
VDDQR VSS
I/O13L I/O14R I/O13R VDDQL
K1
B5
R3
TRST
T3
NC
A6
A11L
B6
A12L
C6
A10L
D6
A7
A8L
B7
A9L
C7
NC
CE1L
B9
B8
C8
C9
LBL
NC
D9
D8
A10
A11
OEL CNTENL
B10
B11
CE0L R/WL REPEATL
UBL
A7L
D7
A9
A8
C10
C11
CLKL ADSL
D10
D11
A12
A5L
B12
A4L
C12
A6L
D12
A13
A2L
B13
A1L
C13
A3L
D13
PIPE/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD
I/O11R VDDQL
G3
A5
A17L(1) A14L
M4
VDDQR
N4
M5
VDD
N5
E6
VDD
F6
VSS
G6
VSS
H6
VSS
J6
VSS
K6
VSS
L6
VSS
M6
VDD
N6
E7
VSS
F7
VSS
G7
VSS
H7
VSS
J7
VSS
K7
VSS
L7
VSS
M7
VSS
N7
E8
E9
VSS
VSS
F9
F8
VSS
VSS
G8
G9
VSS
H8
VSS
H9
VSS
J8
VSS
J9
VSS
K8
VSS
K9
VSS
L8
VSS
L9
VSS
VSS
M9
M8
VSS
N8
VSS
N9
E10
VSS
F10
VSS
G10
VSS
H10
VSS
J10
VSS
K10
VSS
L10
VSS
M10
VSS
N10
E11
VDD
F11
VSS
G11
VSS
H11
VSS
J11
VSS
K11
VSS
L11
VSS
M11
VDD
N11
E12
F12
A16R
R4
NC
T4
P5
A13R
R5
A15R
T5
A17R(1) A14R
P6
A10R
R6
A12R
T6
A11R
P7
A7R
R7
A9R
T7
A8R
P9
P8
LBR
NC
R8
R9
UBR
T8
P10
P11
CLKR ADSR
R10
R11
CE0R R/WR REPEATR
T9
NC
CE1R
T10
T11
OER CNTENR
F13
A0L
B14
VDD
C14
OPTL
D14
NC
E14
NC
F14
VDD VDDQR I/O6R
G12
VSS
H12
VSS
J12
VSS
K12
VSS
L12
VDD
M12
VDD
N12
PIPE/FT R VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL
P4
E13
VDD VDDQR
A14
P12
A6R
R12
A4R
T12
A5R
G13
G14
VDDQL I/O5L
H13
VDDQL
J13
H14
NC
J14
A15
A16
NC
B15
B16
NC
VDDQR
L13
K14
NC
L14
VDDQL I/O2L
M13
M14
VDDQL I/O1R
N13
VDD
P13
A3R
R13
A1R
T13
A2R
N14
NC
P14
NC
R14
OPTR
T14
A0R
NC
C16
C15
NC
D15
I/O8L
D16
NC
I/O8R
E16
E15
I/O7L
I/O7R
F16
F15
NC
G15
I/O6L
G16
NC
NC
H16
H15
NC
I/O5R
J16
J15
VDDQR I/O4R I/O3R
K13
NC
K15
I/O4L
K16
NC
I/O3L
L16
L15
NC
I/O2R
M16
M15
I/O1L
NC
N16
N15
I/O0R
P15
NC
P16
NC
I/O0L
R16
R15
NC
T15
NC
,
T16
NC
NC
5623 drw 02d
,
NOTES:
1. A17 is a NC for IDT70V3399.
2. All VDD pins must be connected to 3.3V power supply.
3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
4. All VSS pins must be connected to ground supply.
5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
6.42
3
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
A14L
A15L
A16L
70V3319/99PRF
PK-128(6)
128-Pin TQFP
Top View(7)
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
A13R
A12R
A11R
A10R
A9R
A8R
A7R
UBR
LBR
CE1R
CE0R
VDD
VDD
VSS
VSS
CLKR
OER
R/WR
ADSR
CNTENR
REPEATR
A6R
A5R
A4R
A3R
A2R
A17L(1)
IO9L
IO9R
VDDQL
VSS
IO10L
IO10R
VDDQR
VSS
IO11L
IO11R
IO12L
IO12R
VDD
VDD
VSS
VSS
IO13R
IO13L
IO14R
IO14L
IO15R
IO15L
VDDQL
VSS
IO16R
IO16L
VDDQR
VSS
IO17R
IO17L
A17R(1)
A16R
A15R
A14R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
08/06/02
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
A13L
A12L
A11L
A10L
A9L
A8L
A7L
UBL
LBL
CE1L
CE0L
VDD
VDD
VSS
VSS
CLKL
OEL
R/WL
ADSL
CNTENL
REPEATL
A6L
A5L
A4L
A3L
A2L
Pin Configuration(1,2,3,4,5,8,9) (con't.)
A1L
A0L
OPTL
VSS
IO8L
IO8R
VSS
VSS
VDDQL
IO7L
IO7R
VSS
VDDQR
IO6L
IO6R
IO5L
IO5R
VDD
VDD
VSS
VSS
IO4R
IO4L
IO3R
IO3L
IO2R
IO2L
VSS
VDDQL
IO1R
IO1L
VSS
VDDQR
IO0R
IO0L
OPTR
A0R
A1R
5623 drw 02a
.
NOTES:
1. A17 is a NC for IDT70V3399.
2. All VDD pins must be connected to 3.3V power supply.
3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V).
4. All VSS pins must be connected to ground supply.
5. Package body is approximately 14mm x 20mm x 1.4mm.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
8. PIPE/FT option in PK-128 is not supported due to limitation in pin count. Device is pipelined outputs only on each port.
9. Due to the limited pin count, JTAG is not supported in the PK-128 package.
6.42
4
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
(6)
CE0L, CE 1L
CE0R, CE1R
Chip Enables
R/WL
R/WR
Read/Write Enable
Output Enable
OER
OEL
(1)
(1)
A 0L - A17L
A0R - A17R
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
CLK L
CLKR
Clock
(5)
(5)
Address
PIPE/FTL
PIPE/FTR
Pipeline/Flow-Through
ADSL
ADSR
Address Strobe Enable
CNTENL
CNTENR
Counter Enable
REPEATL
REPEATR
Counter Repeat(4)
UBL
UBR
Upper Byte Enable (I/O9-I/O17)(6)
LBL
LBR
Lower Byte Enable (I/O0-I/O8)(6)
VDDQL
V DDQR
Power (I/O Bus) (3.3V or 2.5V)(2)
OPTL
OPTR
Option for selecting VDDQX(2,3)
V DD
Power (3.3V)(2)
V SS
Ground (0V)
TDI
Test Data Input
TDO
Test Data Output
TCK
Test Logic Clock (10MHz)
TMS
Test Mode Select
TRST
Reset (Initialize TAP Controller)
5623 tbl 01
NOTES:
1. A17 is a NC for IDT70V3399.
2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
3. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
4. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADS X.
5. PIPE/FT option in PK-128 package is not supported due to limitation in pin count.
Device is pipelined output mode only on each port.
6. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
6.42
5
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2,3)
OE
CLK
CE0
CE1
UB
LB
R/W
Upper Byte
I/O9-17
Lower Byte
I/O0-8
X
↑
H
X
X
X
X
High-Z
High-Z
Deselected–Power Down
X
↑
X
L
X
X
X
High-Z
High-Z
Deselected–Power Down
X
↑
L
H
H
H
X
High-Z
High-Z
Both Bytes Deselected
X
↑
L
H
H
L
L
High-Z
DIN
Write to Lower Byte Only
X
↑
L
H
L
H
L
DIN
High-Z
Write to Upper Byte Only
X
↑
L
H
L
L
L
DIN
DIN
L
↑
L
H
H
L
H
High-Z
DOUT
Read Lower Byte Only
L
↑
L
H
L
H
H
DOUT
High-Z
Read Upper Byte Only
L
↑
L
H
L
L
H
DOUT
DOUT
Read Both Bytes
H
↑
L
H
L
L
X
High-Z
High-Z
Outputs Disabled
MODE
Write to Both Bytes
5623 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = VIH.
3. OE is an asynchronous input signal.
Truth Table II—Address Counter Control(1,2)
External
Address
Previous
Internal
Address
Internal
Address
Used
CLK
ADS
CNTEN
REPEAT(6)
X
X
An
↑
X
X
L(4)
DI/O(0)
Counter Reset to last valid ADS load
An
X
An
↑
L(4)
X
H
DI/O (n)
External Address Used
An
Ap
Ap
↑
H
H
H
DI/O(p)
External Address Blocked—Counter disabled (Ap reused)
H
DI/O(p+1)
X
Ap
Ap + 1
↑
H
(5)
L
MODE
I/O(3)
Counter Enabled—Internal Address generation
5623 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, UB, LB and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the date out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and UB, LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, UB, LB.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
6.42
6
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Recommended Operating
Temperature and Supply Voltage(1)
Grade
Commercial
Industrial
Min.
Typ.
Max.
Unit
V DD
Core Supply Voltage
3.15
3.3
3.45
V
3.3V + 150mV
VDDQ
I/O Supply Voltage (3)
2.4
2.5
2.6
V
3.3V + 150mV
V SS
Ground
0
0
0
GND
VDD
0 C to +70 C
0V
-40 C to +85 C
0V
O
O
O
Recommended DC Operating
Conditions with VDDQ at 2.5V
Symbol
Ambient
Temperature
O
Industrial and Commercial Temperature Ranges
5623 tbl 04
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
Parameter
V
(2)
V
VIH
Input High Voltage
(Address & Control Inputs)
1.7
____
V DDQ + 100mV
VIH
Input High Voltage - I/O(3)
1.7
____
V DDQ + 100mV(2)
V
VIL
Input Low Voltage
-0.3(1)
____
0.7
V
5623 tbl 05a
NOTES:
1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed.
2. VTERM must not exceed VDDQ + 100mV.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIL (0V), and VDDQX for that port must be supplied
as indicated above.
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM(2)
Terminal Voltage
with Respect to GND
-0.5 to +4.6
V
TBIAS(3)
Temperature Under Bias
-55 to +125
o
C
TSTG
Storage Temperature
-65 to +150
o
C
Symbol
Min.
Typ.
Max.
Unit
TJN
Junction Temperature
+150
o
C
V DD
Core Supply Voltage
3.15
3.3
3.45
V
IOUT
DC Output Current
mA
VDDQ
I/O Supply Voltage (3)
3.15
3.3
3.45
V
V SS
Ground
0
0
0
50
Recommended DC Operating
Conditions with VDDQ at 3.3V
5623 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
Parameter
V
(2)
V
VIH
Input High Voltage
(Address & Control Inputs)(3)
2.0
____
VDDQ + 150mV
VIH
Input High Voltage - I/O(3)
2.0
____
VDDQ + 150mV(2)
V
VIL
Input Low Voltage
-0.3(1)
____
0.8
V
5623 tbl 05b
NOTES:
1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed.
2. VTERM must not exceed VDDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be
supplied as indicated above.
6.42
7
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Capacitance(1)(TA = +25°C, F = 1.0MHZ)
Symbol
CIN
Parameter
Input Capacitance
(3)
COUT
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 3dV
8
pF
VOUT = 3dV
10.5
pF
5623 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
70V3319/99S
Symbol
Min.
Max.
Unit
VDDQ = Max., VIN = 0V to V DDQ
___
10
µA
Output Leakage Currentt
CE0 = VIH or CE1 = VIL, VOUT = 0V to V DDQ
___
10
µA
VOL (3.3V)
Output Low Voltage(2)
IOL = +4mA, VDDQ = Min.
___
0.4
V
VOH (3.3V)
Output High Voltage (2)
IOH = -4mA, VDDQ = Min.
2.4
___
V
VOL (2.5V)
(2)
IOL = +2mA, VDDQ = Min.
___
0.4
V
(2)
IOH = -2mA, VDDQ = Min.
2.0
___
V
|ILI|
|ILO |
VOH (2.5V)
Parameter
(1)
Input Leakage Current
(1)
Output Low Voltage
Output High Voltage
Test Conditions
5623 tbl 08
NOTE:
1. At VDD < 2.0V leakages are undefined.
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.
6.42
8
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Test Condition
Version
70V3319/99S166
Com'l Only
70V3319/99S133
Com'l
& Ind
Typ.(4)
Max.
Typ. (4)
Max.
Unit
mA
Dynamic Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled,
f = fMAX(1)
COM'L
S
370
500
320
400
IND
S
____
____
320
480
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH,
Outputs Disabled,
f = fMAX(1)
COM'L
S
125
200
115
160
IND
S
____
____
115
195
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(1)
COM'L
S
250
350
220
290
IND
S
____
____
220
350
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports Outputs Disabled
CEL and CER > VDD - 0.2V,
VIN > VDD - 0.2V
or VIN < 0.2V, f = 0(2)
COM'L
S
15
30
15
30
IND
S
____
____
15
40
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and CE"B" > VDD - 0.2V(5)
VIN > VDD - 0.2V or VIN < 0.2V
Active Port, Outp uts Disabled , f = f MAX(1)
COM'L
S
250
350
220
290
IND
S
____
____
220
350
mA
mA
mA
mA
5623 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).
5. CEX = V IL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6.42
9
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels (Address & Controls)
GND to 3.0V/GND to 2.4V
Input Pulse Levels (I/Os)
GND to 3.0V/GND to 2.4V
Input Rise/Fall Times
2.5V
833Ω
2ns
Input Timing Reference Levels
1.5V/1.25V
Output Reference Levels
1.5V/1.25V
Output Load
DATAOUT
5pF*
770Ω
Figures 1 and 2
5623 tbl 10
,
3.3V
590Ω
50Ω
50Ω
DATAOUT
1.5V/1.25
10pF
(Tester)
,
DATAOUT
435Ω
5pF*
5623 drw 03
Figure 1. AC Output Test load.
5623 drw 04
Figure 2. Output Test Load
(For tCKLZ , tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.
7
6
5
4
∆tCD
(Typical, ns) 3
2
•
1
•
20.5
•
30
•
50
80
100
200
-1
Capacitance (pF)
5623 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
10
,
,
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(2,3) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
70V3319/99S166
Com'l Only
Symbol
tCYC1
tCYC2
tCH1
tCL1
Parameter
Clock Cycle Time (Flow-Through)(1)
(1)
Clock Cycle Time (Pipelined)
70V3319/99S133
Com'l
& Ind
Min.
Max.
Min.
Max.
Unit
20
____
25
____
ns
ns
6
____
7.5
____
(1)
6
____
7
____
ns
(1)
ns
Clock High Time (Flow-Through)
6
____
7
____
tCH2
Clock High Time (Pipelined)
(2)
2.1
____
2.6
____
ns
tCL2
Clock Low Time (Pipelined)(1)
2.1
____
2.6
____
ns
tSA
Address Setup Time
1.7
____
1.8
____
ns
tHA
Address Hold Time
0.5
____
0.5
____
ns
tSC
Chip Enable Setup Time
1.7
____
1.8
____
ns
tHC
Chip Enable Hold Time
0.5
____
0.5
____
ns
tSB
Byte Enable Setup Time
1.7
____
1.8
____
ns
tHB
Byte Enable Hold Time
0.5
____
0.5
____
ns
tSW
R/W Setup Time
1.7
____
1.8
____
ns
tHW
R/W Hold Time
0.5
____
0.5
____
ns
tSD
Input Data Setup Time
1.7
____
1.8
____
ns
tHD
Input Data Hold Time
0.5
____
0.5
____
ns
tSAD
ADS Setup Time
1.7
____
1.8
____
ns
ADS Hold Time
0.5
____
0.5
____
ns
CNTEN Setup Time
1.7
____
1.8
____
ns
tHCN
CNTEN Hold Time
0.5
____
0.5
____
ns
tSRPT
REPEAT Setup Time
1.7
____
1.8
____
ns
tHRPT
REPEAT Hold Time
0.5
____
0.5
____
ns
tOE
Output Enable to Data Valid
____
4.0
____
4.2
ns
tOLZ
Output Enable to Output Low-Z
1
____
1
____
ns
tOHZ
Output Enable to Output High-Z
tHAD
tSCN
tCD1
Clock Low Time (Flow-Through)
Clock to Data Valid (Flow-Through)
(1)
(1)
1
3.6
1
4.2
ns
____
12
____
15
ns
____
3.6
____
4.2
ns
ns
tCD2
Clock to Data Valid (Pipelined)
tDC
Data Output Hold After Clock High
1
____
1
____
tCKHZ
Clock High to Output High-Z
1
3
1
3
ns
tCKLZ
Clock High to Output Low-Z
1
____
1
____
ns
5
____
6
____
Port-to-Port Delay
tCO
Clock-to-Clock Offset
ns
5623 tbl 11
NOTES:
1. The Pipelined output parameters (t CYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
3. These values are valid for either level of V DDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.
6.42
11
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(2)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tSC
tHC
tHC
(3)
CE1
tSB
tSB
tHB
UB, LB
R/W
ADDRESS
(4)
tSW
tHW
tSA
tHA
An
An + 1
(1 Latency)
An + 2
An + 3
tDC
tCD2
DATAOUT
Qn
tCKLZ
OE
tHB
(5)
Qn + 1
Qn + 2
(5)
(1)
tOHZ
tOLZ
(1)
tOE
5623 drw 06
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(2,6)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tSC
tHC
tHC
(3)
CE1
tSB
tHB
UB, LB
tSB
R/W
tHB
tSW tHW
tSA
(4)
ADDRESS
tHA
An
An + 1
tCD1
DATAOUT
An + 2
tCKHZ
Qn
Qn + 2 (5)
Qn + 1
tCKLZ
OE
An + 3
tDC
tOHZ
tOLZ
tDC
(1)
tOE
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If UB, LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
6.42
12
5623 drw 07
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Multi-Device Pipelined Read(1,2)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
A0
ADDRESS(B1)
tSC
tHC
CE0(B1)
tSC
tHC
tCD2
tCD2
tCKHZ
Q0
DATAOUT(B1)
tSA
A0
tSC
Q3
tCKLZ
tDC
tCKHZ
tHA
A6
A5
A4
A3
A2
A1
tSC
CE0(B2)
tCD2
Q1
tDC
ADDRESS(B2)
A6
A5
A4
A3
A2
A1
tHC
tHC
tCD2
DATAOUT(B2)
tCKHZ
tCD2
Q4
Q2
tCKLZ
tCKLZ
5623 drw 08
Timing Waveform of a Multi-Device Flow-Through Read(1,2)
tCH1
tCYC1
tCL1
CLK
tSA
A0
ADDRESS(B1)
CE0(B1)
tHA
tSC
A6
A5
A4
A3
A2
A1
tHC
tSC tHC
tCD1
tCD1
D0
DATAOUT(B1)
tCKHZ
tCD1
D3
tCKLZ
tDC
(1)
D5
tCKHZ (1)
tCKLZ
(1)
tHA
A0
ADDRESS(B2)
tCD1
D1
tDC
tSA
(1)
A1
A6
A5
A4
A3
A2
tSC tHC
CE0(B2)
tSC
tHC
tCD1
DATAOUT(B2)
tCKLZ
(1)
tCKHZ
(1)
tCD1
D2
tCKLZ
(1)
tCKHZ
(1)
D4
5623 drw 09
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3319/99 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE 1(B2), R/W, CNTEN, and REPEAT = VIH.
6.42
13
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4)
CLK"A"
tSW
tHW
tSA
tHA
R/W"A"
ADDRESS"A"
tSD
DATAIN"A"
NO
MATCH
MATCH
tHD
VALID
tCO(3)
CLK"B"
tCD2
R/W"B"
ADDRESS"B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
DATAOUT"B"
VALID
tDC
5623 drw 10
NOTES:
1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = V IH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2 ). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + t CYC2 + t CD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)
CLK "A"
tSW
tHW
tSA
tHA
R/W "A"
ADDRESS "A"
tSD
DATAIN "A"
NO
MATCH
MATCH
tHD
VALID
tCO
(3)
CLK "B"
tCD1
R/W "B"
ADDRESS "B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
tCD1
DATAOUT "B"
VALID
VALID
tDC
tDC
5623 drw 11
NOTES:
1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = V IH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + t CYC + tCD1 ). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be tCO + t CD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42
14
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read
tCYC2
(OE = VIL)(2)
tCH2
tCL2
CLK
CE0
tSC
tHC
tSB
tHB
CE1
UB, LB
tSW tHW
R/W
(3)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
An + 3
An + 2
An + 4
tSD tHD
DATAIN
Dn + 2
tCD2
(1)
tCKHZ
tCKLZ
tCD2
Qn + 3
Qn
DATAOUT
READ
NOP
(4)
WRITE
READ
5623 drw 12
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = V IL; CE1, CNTEN, and REPEAT = V IH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)(2)
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
tSB
tHB
CE1
UB, LB
tSW tHW
R/W
tSW tHW
(3)
ADDRESS
An
tSA tHA
An +1
An + 2
tSD
DATAIN
Dn + 2
tCD2
(1)
Qn
DATAOUT
An + 3
An + 4
An + 5
tHD
Dn + 3
tCKLZ
tCD2
Qn + 4
(4)
tOHZ
OE
READ
WRITE
READ
5623 drw 13
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE 0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH .
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
15
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2)
tCH1
tCYC1
tCL1
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
tSW tHW
R/W
tSW tHW
(3)
ADDRESS
tSA
An
tHA
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD1
(1)
tCD1
Qn
DATAOUT
tCD1
tCD1
Qn + 1
tDC
tCKHZ
(5)
NOP
READ
tCKLZ
WRITE
Qn + 3
tDC
READ
6523 drw 14
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
tSW tHW
tSW tHW
R/W
(3)
An
tSA tHA
ADDRESS
An +1
DATAIN
(1)
DATAOUT
An + 2
tSD tHD
An + 3
Dn + 2
Dn + 3
tDC
tCD1
An + 4
tOE
tCD1
Qn
tCKLZ
tOHZ
An + 5
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
5623 drw 15
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = V IH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
16
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT
Qx - 1(2)
Qn + 2(2)
Qn + 1
Qn
Qx
Qn + 3
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
5623 drw 16
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
tCH1
tCYC1
tCL1
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD1
DATAOUT
Qx(2)
Qn
Qn + 1
Qn + 2
Qn + 3(2)
Qn + 4
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
5623 drw 17
NOTES:
1. CE 0, OE, UB, LB = VIL; CE1, R/W, and REPEAT = VIH.
2. If there is no address change via ADS = V IL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.42
17
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)(1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 2
An + 1
An + 4
An + 3
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tSD tHD
Dn + 1
Dn
DATAIN
WRITE
EXTERNAL
ADDRESS
Dn + 1
Dn + 4
Dn + 3
Dn + 2
WRITE
WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
5623 drw 18
Timing Waveform of Counter Repeat(2)
tCH2
tCYC2
tCL2
CLK
tSA tHA
(4)
An
ADDRESS
INTERNAL(3)
ADDRESS
LAST ADS LOAD
Ax
An + 2
An + 1
LAST ADS +1
An
An + 1
tSW tHW
R/W
ADS
t SAD tHAD
CNTEN
tSCN tHCN
tSRPT tHRPT
REPEAT
tSD
tHD
D0
DATAIN
(5)
QLAST
DATAOUT
(6)
EXECUTE
REPEAT
WRITE
LAST ADS
ADDRESS
READ
LAST ADS
ADDRESS
READ
LAST ADS
ADDRESS + 1
QLAST+1
READ
ADDRESS n
Qn
READ
ADDRESS n+1
5623 drw 19
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and REPEAT = VIH.
2. CE0, UB, LB = V IL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6.42
18
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Functional Description
Depth and Width Expansion
The IDT70V3319/99 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse is independent of the LOW to HIGH transition of the clock
signal.
An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V3319/99s for depth
expansion configurations. Two cycles are required with CE0 LOW and
CE1 HIGH to re-activate the outputs.
The IDT70V3319/99 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70V3319/99 can also be used in applications requiring
expanded width, as indicated in Figure 4. Through combining the control
signals, the devices can be grouped as necessary to accommodate
applications needing 36-bits or wider.
A18/A17(1)
IDT70V3319/99
CE0
CE1
IDT70V3319/99
CE1
VDD
VDD
Control Inputs
Control Inputs
IDT70V3319/99
CE0
IDT70V3319/99
CE1
CE1
CE0
CE0
Control Inputs
Control Inputs
5623 drw 20
Figure 4. Depth and Width Expansion with IDT70V3319/99
NOTE:
1. A17 is for IDT70V3319, A16 is for IDT70V3399.
6.42
19
UB, LB,
R/W,
OE,
CLK,
ADS,
REPEAT,
CNTEN
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
JTAG Timing Specifications
tJF
tJCL
tJCYC
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
TRST
,
5623 drw 21
tJRST
Figure 5. Standard JTAG Timing
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4)
70V3319/99
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
(1)
tJR
JTAG Clock Rise Time
____
3
ns
tJF
JTAG Clock Fall Time
____
3(1)
ns
tJRST
JTAG Reset
50
____
ns
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
25
ns
tJDC
JTAG Data Output Hold
0
____
ns
tJS
JTAG Setup
15
____
ns
tJH
JTAG Hold
15
____
ns
5623 tbl 12
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
6.42
20
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Revision Number (31:28)
IDT Device ID (27:12)
Description
0x0
Reserved for version number
(1)
0x0314
IDT JEDEC ID (11:1)
0x33
ID Register Indicator Bit (Bit 0)
Defines IDT part number
Allows unique identification of device vendor as IDT
1
Indicates the presenc e of an ID register
5623 tbl 13
NOTE:
1. Device ID for IDT70V3399 is 0x0315.
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
Identification (IDR)
Boundary Scan (BSR)
32
Note (3)
5623 tbl 14
System Interface Parameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan registe r (BSR) between TDI and TDO.
BYPASS
1111
Places the by pass register (BYR) between TDI and TDO.
IDCODE
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0011
Places the bypass register (BYR) be tween TDI and TDO. Forces all
device output drivers to a High-Z state.
0001
Places the boundary scan registe r (BSR) between TDI and TDO.
SAMPLE allows data from device inputs (2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the b oundary scan cells via the TDI.
All other codes
Several combinations are reserved. Do not use codes other than those
identified above.
HIGHZ
SAMPLE/PRELOAD
RESERVED
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
6.42
21
5623 tbl 15
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT
XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BF
PRF
BC
208-pin fpBGA (BF-208)
128-pin TQFP (PK-128)
256-pin BGA (BC-256)
166
133
Commercial Only
Commercial & Industrial
S
Standard Power
Speed in Megahertz
70V3319 4Mbit (256K x 18-Bit) Synchronous Dual-Port RAM
70V3399 2Mbit (128K x 18-Bit) Synchronous Dual-Port RAM
5623 drw 22
IDT Clock Solution for IDT70V3319/99 Dual-Port
Dual-Port I/O Specitications
IDT Dual-Port
Part Number
Voltage
70V3319/99
3.3/2.5
Clock Specifications
I/O
Input
Capacitance
Input Duty
Cycle
Requirement
Maximum
Frequency
Jitter
Tolerance
IDT
PLL
Clock Device
LVTTL
8pF
40%
166
75ps
IDT5V2528
5623 tbl 16a
6.42
22
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Datasheet Document History:
06/02/00:
07/12/00:
06/20/01:
07/30/01:
11/20/01:
08/06/02:
05/19/03:
Initial Public Offering
Page 1 Added mux to functional block diagram
Page 1 Added JTAG information for TQFP package
Page 4 Corrected TQFP package size
Page 1 Added PL/FToption
Page 20 Changed maximum value for JTAG AC Electrical Characteristics for tJCD from 20ns to 25ns
Page 9 Added Industrial Temperature DC Parameters
Page 2, 3 & 4 Added date revision for pin configurations
Page 11 Changed tOE value in AC Electrical Characteristics, please refer to Errata #SMEN-01-05
Page 1 & 22 Replaced TM logo with ® logo
Page 10 Changed AC Test Conditions Input Rise/Fall Times
Consolidated multiple devices into one datasheet
Page 1 & 5 Added DCD capability for Pipelined Outputs
Page 7 Clarified TBIAS and added TJN
Page 9 Changed DC Electrical Parameters
Page 11 Removed Clock Rise & Fall Time from AC Electrical Characteristics Table
Removed Preliminary status
Page 11 Added Byte Enable SetupTime & Byte Enable Hold Time to AC Elecctrical Characteristics Table
Page 22 Added IDT Clock Solution Table
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-5166
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
23
for Tech Support:
831-754-4613
[email protected]
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