NSC ADC08061 500 ns a/d converter with s/h function and input multiplexer Datasheet

July 15, 2009
ADC08061/ADC08062
500 ns A/D Converter with S/H Function and Input
Multiplexer
General Description
Key Specifications
NOTE: These products are obsolete. This data sheet is
provided for reference only.
Using a patented multi-step A/D conversion technique, the 8bit ADC08061 and ADC08062 CMOS ADCs offer 500 ns (typ)
conversion time, internal sample-and-hold (S/H), and dissipate only 125 mW of power. The ADC08062 has a twochannel multiplexer. The ADC08061/2 performs 8-bit conversions using a multistep flash approach.
Input track-and-hold circuitry eliminates the need for an external sample-and-hold. The ADC08061/2 performs accurate
conversions of full-scale input signals that have a frequency
range of DC to 300 kHz (full-power bandwidth) without need
of an external S/H.
The digital interface has been designed to ease connection
to microprocessors and allows the parts to be I/O or memory
mapped.
■
■
■
■
■
■
Resolution
Conversion Time
Full Power Bandwidth
Throughput rate
Power Consumption
Total Unadjusted Error
8 bits
560 ns max (WR-RD Mode)
300 kHz
1.5 MHz
100 mW max
±½ LSB and ±1 LSB
Features
■
■
■
■
■
1 or 2 input channels
No external clock required
Analog input voltage range from GND to V+
Overflow output for cascading (ADC08061)
ADC08061 pin-compatible with the ADC0820
Applications
■
■
■
■
Mobile telecommunications
Hard disk drives
Instrumentation
High-speed data acquisition systems
Block Diagram
1108601
* ADC08061
** ADC08062
Ordering Information
Industrial (−40°C ≤ TA ≤ 85°C)
Package
ADC08061BIN, ADC08062BIN
N20A
ADC08061CIWM, ADC08062CIWM
M20B
© 2009 National Semiconductor Corporation
11086
11086 Version 6 Revision 2
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Print Date/Time: 2009/07/15 15:48:35
ADC08061/ADC08062 500 ns A/D Converter with S/H Function and Input Multiplexer
OBSOLETE
ADC08061/ADC08062
Connection Diagrams
1108614
1108615
Dual-In-Line and Wide-Body
Small-Outline
Packages N20A or M20B
Dual-In-Line and Wide-Body
Small-Outline
Packages N20A or M20B
Pin Descriptions
VIN,VIN1–8
DB0–DB7
WR /RDY
:
MODE
RD
INT
These are analog inputs. The input range is
GND–50 mV ≤ VINPUT ≤ V+ + 50 mV. The
ADC08061 has a single input (VIN) and the
ADC08062 has a two-channel multiplexer
(VIN1–2).
TRI-STATE data outputs—bit 0 (LSB) through
bit 7 (MSB).
WR-RD Mode (Logic high applied to MODE
pin)
WR: With CS low, the conversion is started on
the falling edge of WR. The digital result will be
strobed into the output latch at the end of conversion (see Figures 2, 3, 4).
RD Mode (Logic low applied to MODE pin)
RDY: This is an open drain output (no internal
pull-up device). RDY will go low after the falling
edge of CS and return high at the end of conversion.
Mode: Mode (RD or WR-RD) selection input—
This pin is pulled to a logic low through an internal 50 µA current sink when left unconnected.
RD Mode is selected if the MODE pin is left unconnected or externally forced low. A complete
conversion is accomplished by pulling RD low
until output data appears.
WR-RD Mode is selected when a high is applied to the MODE pin. A conversion starts with
the WR signal's rising edge and then using
RD to access the data.
WR-RD Mode (logic high on the MODE pin)
This is the active low Read input. With a logic
low applied to the CS pin, the TRI-STATE data
outputs (DB0–DB7) will be activated when RD
goes low (Figures 2, 3, 4).
RD Mode (logic low on the MODE pin)
With CS low, a conversion starts on the falling
edge of RD. Output data appears on DB0–DB7
at the end of conversion (see Figures 1, 5).
This is an active low output that indicates that a
conversion is complete and the data is in the
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GND
VREF−,VREF+
CS
OFL
NC
A0
output latch. INT is reset by the rising edge of
RD.
This is the power supply ground pin. The
ground pin should be connected to a “clean”
ground reference point.
These are the reference voltage inputs. They
may be placed at any voltage between GND −
50 mV and V+ + 50 mV, but VREF+ must be
greater than VREF−. Ideally, an input voltage
equal to VREF− produces an output code of 0,
and an input voltage greater than VREF+ − 1.5
LSB produces an output code of 255.
For the ADC08062, an input voltage on any unselected input that exceeds V+ by more than
100 mV or is below GND by more than 100 mV
will create errors in a selected channel that is
operating within proper operating conditions.
This is the active low Chip Select input. A logic
low signal applied to this input pin enables the
RD and WR inputs. Internally, the CS signal is
ORed with RD and WR signals.
Overflow Output. If the analog input is higher
than VREF+ − ½ LSB, OFL will be low at the end
of conversion. It can be used when cascading
two ADC08061s to achieve higher resolution (9
bits). This output is always active and does not
go into TRI-STATE as DB0–DB7 do. When
OFL is set, all data outputs remain high when
the ADC08061's output data is read.
No connection.
This logic input is used to select one of the
ADC08062's input multiplexer channels. A
channel is selected as shown in the table below.
ADC08062
A0
Channel
0
VIN1
1
VIN2
V+ Positive power supply voltage input. Nominal operating
supply voltage is +5V. The supply pin should be bypassed
with a 10 µF bead tantalum in parallel with a 0.1 ceramic
capacitor. Lead length should be as short as possible.
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TMIN ≤ TA ≤ TMAX =
−40°C ≤ TA ≤ 85°C
Temperature Range
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V+)
Logic Control Inputs
Voltage at Other Inputs and Outputs
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (Note 4)
All Packages
Storage Temperature
Lead Temperature (Note 5)
J Package (Soldering, 10 sec.)
N Package (Soldering, 10 sec.)
WM Package
(Vapor Phase, 60 sec.)
WM Package (Infrared, 15 sec.)
ESD Susceptibility (Note 6)
Supply Voltage, (V+)
Pos. Reference Voltage, VREF+
Neg. Reference Voltage, VREF−
Input Voltage Range
6V
−0.3V to V+ + 0.3V
−0.3V to V+ + 0.3V
5 mA
20 mA
(Notes 1, 2)
+4.5V to +5.5V
(VREF− + 1V) to V+
GND to (VREF+ − 1V)
VREF− to VREF+
875 mW
−65°C to +150°C
+300°C
+260°C
+215°C
+220°C
2 kV
Converter Characteristics
The following specifications apply for RD Mode, V+ = 5V, VREF+ = 5V, and VREF− = GND unless otherwise specified. Boldface
limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
Symbol
INL
TUE
Limits
(Note 8)
Units
(Limit)
ADC08061/2BIN
±½
LSB (max)
ADC08061/2CIWM
±1
LSB (max)
ADC08061/2BIN
±½
LSB (max)
ADC08061/2CIWM
±1
LSB (max)
0
Bits (max)
Parameter
Conditions
Integral Non Linearity
Total Unadjusted Error
Typical
(Note 7)
Missing Codes
Reference Input Resistance
VREF+
Positive Reference Input Voltage
VREF−
Negative Reference Input
Voltage
VIN
Analog Input Voltage
500
Ω(min)
700
1250
Ω (max)
VREF−
V (min)
V+
V (max)
GND
VREF+
V (min)
V (max)
GND − 0.1
V+ + 0.1
V (min)
V (max)
(Note 10)
On Channel Input Current
PSS
700
Power Supply Sensitivity
On Channel Input = 5V, Off Channel
Input = 0V (Note 11)
−0.4
−20
µA (max)
On Channel Input = 0V, Off Channel
Input = 5V (Note 11)
−0.4
−20
µA (max)
V+ = 5V ±5%, VREF = 4.75V
All Codes Tested
±1/16
±½
LSB (max)
Effective Bits
7.8
Bits
Full-Power Bandwidth
300
kHz
THD
Total Harmonic Distortion
0.5
%
S/N
Signal-to-Noise Ratio
50
dB
IMD
Intermodulation Distortion
50
dB
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ADC08061/ADC08062
Operating Ratings
Absolute Maximum Ratings
ADC08061/ADC08062
AC Electrical Characteristics
The following specifications apply for V+ = 5V, tr = tf = 10 ns, VREF+ = 5V, VREF− = 0V unless otherwise specified. Boldface limits
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
Symbol
Parameter
tWR
Write Time
Condition
Mode Pin to V+;
(Figures 2, 3, 4)
Typical
(Note 7)
Limits
(Note 8)
Units
(Limit)
100
100
ns (min)
tRD
Read Time (Time from Falling Edge of
Mode Pin to V+; (Figure 2)
WR to Falling Edge of RD )
350
350
ns (min)
tRDW
RD Width
200
400
250
400
ns (min)
ns (max)
tCONV
WR -RD Mode Conversion Time (tWR
Mode Pin to V+; (Figure 2)
+ tRD + tACC1)
500
560
ns (max)
tCRD
RD Mode Conversion Time
655
900
ns (max)
tACCO
Access Time (Delay from Falling Edge CL ≤ 100 pF Mode Pin to GND;
of RD to Output Valid)
(Figure 1)
640
900
ns (max)
45
110
ns (max)
tACC1
Mode Pin to GND; (Figure 5)
Mode Pin to GND; (Figure 1)
Mode Pin to V+, tRD ≤ tINTL
Access Time (Delay from Falling Edge (Figure 2)
CL = 10 pF
of RD to Output Valid)
CL ≤ 100 pF
50
ns
tRD > tINTL; (Figures 3, 4)
tACC2
Access Time (Delay from Falling Edge
of RD to Output Valid)
t0H
TRI-STATE Control (Delay from
Rising Edge of RD to HI-Z State)
RL = 3 kΩ, CL = 10 pF
t1H
TRI-STATE Control (Delay from
Rising Edge of RD to HI-Z State)
tINTL
CL ≤ 10 pF
25
CL = 100 pF
30
55
ns (max)
30
60
ns (max)
RL = 3 kΩ, CL = 10 pF
30
60
ns (max)
Delay from Rising Edge of
WR to Falling Edge of INT
(Figures 3, 4)
Mode Pin = V+, CL = 50 pF
520
690
ns (max)
tINTH
Delay from Rising Edge of RD to
Rising Edge of INT
CL = 50 pF; (Figures 1, 2, 3, 4)2b,
and 4 )
50
95
ns (max)
tINTH
Delay from Rising Edge of WR to
Rising Edge of INT
CL = 50 pF; (Figure 4)
45
95
ns (max)
tRDY
Delay from CS to RDY
25
45
ns (max)
tID
Delay from INT to Output Valid
RL = 3 kΩ, CL = 100 pF; (Figure
4)
0
15
ns (max)
tRI
Delay from RD to INT
Mode Pin = V+, tRD ≤ tINTL; (Figure
3)
60
115
ns (max)
tN
Time between End of RD and Start of
(Figures 1, 2, 3, 4, 5)
New Conversion
50
50
ns (min)
tAH
Channel Address Hold Time
(Figures 1, 2, 3, 4, 5)
10
60
ns (min)
tAS
Channel Address Setup Time
(Figures 1, 2, 3, 4, 5)
0
0
ns (max)
tCSS
CS Setup Time
(Figures 1, 2, 3, 4, 5)
0
0
ns (max)
tCSH
CS Hold Time
(Figures 1, 2, 3, 4, 5)
0
0
ns (min)
CVIN
Analog Input Capacitance
25
pF
COUT
Logic Output Capacitance
5
pF
CIN
Logic Input Capacitance
5
pF
Mode Pin = 0V, CL = 50 pF, RL =
3 kΩ (Figure 1)
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The following specifications apply for V+ = 5V unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all
other limits TA = TJ = 25°C.
Symbol
Limits (Note
8)
Units
(Limit)
Mode Pin
3.5
V (min)
ADC08062 CS, WR, RD, A0 Pins
2.2
V (min)
ADC08061 CS, WR, RD Pins
2.0
V (min)
Mode Pin
1.5
V (max)
ADC08062 CS, WR, RD, A0 Pins
0.7
V (max)
ADC08061 CS, WR, RD Pins
0.8
V (max)
1
3
200
µA (max)
µA (max)
µA (max)
Parameter
Conditions
Typical (Note
7)
V+ = 5.5V
VIH
Logic “1” Input Voltage
V+ = 4.5V
VIL
Logic “0” Input Voltage
VIH = 5V
IIH
CS, RD, A0 Pins
WR Pin
Mode Pin
Logic “1” Input Current
0.005
0.1
50
VIL = 0V
IIL
Logic “0” Input Current
CS, RD, WR, A0 Pins
Mode Pin
−0.005
µA (max)
−2
V+ = 4.75V
IOUT = −360 µA
VOH
VOL
Logic “1” Output Voltage
Logic “0” Output Voltage
DB0–DB7, OFL, INT
IOUT = −10 µA
2.4
V (min)
DB0–DB7, OFL, INT
4.5
V (min)
0.4
V (max)
0.1
3
µA (max)
−0.1
−3
µA (max)
V+ = 4.75V, IOUT = 1.6 mA
DB0–DB7, OFL, INT, RDY
VOUT = 5.0V
IO
TRI-STATE Output Current
DB0–DB7, RDY
VOUT = 0V
DB0–DB7, RDY
ISOURCE
Output Source Current
VOUT = 0V
DB0–DB7, OFL, INT
−26
−6
mA (min)
ISINK
Output Sink Current
VOUT = 5V
DB0–DB7, OFL, INT, RDY
24
7
mA (min)
IC
Supply Current
CS = WR = RD = 0
11.5
20
mA (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee performance limits.
For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some
performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply voltage (VIN < GND or VIN > V+), the absolute value of the current at that pin should
be limited to 5 mA or less. The 20 mA package input current specification limits the number of pins that can exceed the power supply boundaries with a 5 mA
current limit to four.
Note 4: The power dissipation of this device under normal operation should never exceed 875 mW (Quiescent Power Dissipation + the loads on the digital
outputs). Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (e.g., when any input
or output exceeds the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX (maximum junction
temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature
is PDmax = (TJMAX − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. The table below details TJMAX and θJA for the various
packages and versions of the ADC08061/2.
Part Number
ADC08061/2BIN
ADC08061/2CIWM
TJMAX
θJA
105
105
51
85
Note 5: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices.
Note 6: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
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ADC08061/ADC08062
DC Electrical Characteristics
ADC08061/ADC08062
Note 7: Typical figures are at 25°C and represent most likely parametric norm.
Note 8: Limits are guaranteed to National's AOQL (Average Output Quality Level).
Note 9: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 10: Two on-chip diodes are tied to each analog input and are reversed biased during normal operation. One is connected to V+ and the other is connected
to GND. They will become forward biased and conduct when an analog input voltage is equal to or greater than one diode drop above V+ or below GND. Therefore,
caution should be exercised when testing with V+ = 4.5V. Analog inputs with magnitudes equal to 5V can cause an input diode to conduct, especially at elevated
temperatures. This can create conversion errors for analog signals near full-scale. The specification allows 50 mV forward bias on either diode; e.g., the output
code will be correct as long as the analog input signal does not exceed the supply voltage by more than 50 mV. Exceeding this range on an unselected channel
will corrupt the reading of a selected channel. An absolute analog input signal voltage range of 0V ≤ VIN ≤ 5V can be achieved by ensuring that the minimum
supply voltage applied to V+ is 4.950V over temperature variations, initial tolerance, and loading.
Note 11: Off-channel leakage current is measured after the on-channel selection.
TRI-STATE Test Circuits and Waveforms
t1H
t0H, CL = 10 pF
1108605
1108602
tr = 10 ns
t1H, CL = 10 pF
1108604
tr = 10 ns
t0H
1108603
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ADC08061/ADC08062
Timing Diagrams
1108606
FIGURE 1. RD Mode (Mode Pin is Low)
1108607
FIGURE 2. WR-RD Mode (Mode Pin is High and tRD ≤ tINTL)
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ADC08061/ADC08062
1108608
FIGURE 3. WR-RD Mode (Mode Pin is High and tRD > tINTL)
1108609
FIGURE 4. WR-RD Mode (Mode Pin is High) Reduced Interface System Connection (CS = RD = 0)
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ADC08061/ADC08062
1108610
FIGURE 5. RD Mode (Pipeline Operation) (Mode Pin is Low and tRDW must be between 200 ns and 400 ns)
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ADC08061/ADC08062
Typical Performance Characteristics
tCRD vs. Temperature
Linearity Error vs.
Reference Voltage
1108625
1108626
Offset Error vs.
Reference Voltage
Supply Current
vs. Temperature
1108627
1108628
Logic Threshold
vs. Temperature
Output Current
vs. Temperature
1108629
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1108630
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1.0 FUNCTIONAL DESCRIPTION
The ADC08061 and ADC08062 perform 8-bit analog-to-digital conversions using a multi-step flash technique. The first
flash generates the five most significant bits (MSBs) and the
second flash generates the three least significant bits (LSBs).
Figure 6 shows the major functional blocks of the
ADC08061/2's multi-step flash converter. It consists of an
over-encoded 2½-bit Voltage Estimator, an internal DAC with
two different voltage spans, a 3-bit half-flash converter and a
comparator multiplexer.
The resistor string near the center of the block diagram in
Figure 6 forms the internal main DAC. Each of the eight resistors at the bottom of the string is equal to 1/256 of the total
string resistance. These resistors form the LSB Ladder and
have a voltage drop of 1/256 of the total reference voltage
(VREF+ − VREF−) across them. The remaining resistors make
up the MSB Ladder. They are made up of eight groups of four
resistors connected in series. Each MSB Ladder section has
⅛ of the total reference voltage across it. Within a given MSB
1108618
FIGURE 6. Block Diagram of the ADC08061/2 Multi-Step Flash Architecture
A conversion begins with the Voltage Estimator comparing
the analog input signal against the six tap voltages on the
estimator DAC. The estimator decoder then selects one of the
groups of tap points along the MSB Ladder. These eight tap
points are then connected to the eight flash comparators. For
example, if the analog input signal applied to VIN is between
0 and 3/16 of VREF (VREF = VREF+ − VREF−), the estimator decoder instructs the comparator multiplexer to select the eight
tap points between 8/256 and 2/8 of VREF and connects them
to the eight flash comparators. The first flash conversion is
now performed, producing the five MSBs of data.
The remaining three LSBs are generated next using the same
eight comparators that were used for the first flash conversion. As determined by the results of the MSB flash, a voltage
from the MSB Ladder equivalent to the magnitude of the five
MSBs is subtracted from the analog input voltage as the upper
switch is moved from position one to position two. The resulting remainder voltage is applied to the eight flash compara-
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ADC08061/ADC08062
Ladder section, each of the MSB resistors has 8/256, or 1/32
of the total reference voltage across it. Tap points are found
between all of the resistors in both the MSB and LSB Ladders.
Through the Comparator Multiplexer these tap points can be
connected, in groups of eight, to the eight comparators shown
at the right of Figure 6. This function provides the necessary
reference voltages to the comparators during each flash conversion.
The six comparators, seven-resistor string (estimator DAC),
and Estimator Decoder at the left of Figure 6 form the Voltage
Estimator. The estimator DAC connected between VREF+ and
VREF− generates the reference voltages for the six Voltage
Estimator comparators. These comparators perform a very
low resolution A/D conversion to obtain an “estimate” of the
input voltage. This estimate is then used to control the Comparator Multiplexer, connecting the appropriate MSB Ladder
section to the eight flash comparators. Only 14 comparators,
six in the Voltage Estimator and eight in the flash converter,
are needed to achieve the full eight-bit resolution, instead of
32 comparators that would be needed by traditional half-flash
methods.
Application Information
ADC08061/ADC08062
tors and, with the lower switch in position two, compared with
the eight tap points from the LSB Ladder.
By using the same eight comparators for both flash conversions, the number of comparators needed by the multi-step
converter is significantly reduced when compared to standard
half-flash techniques.
Voltage Estimator errors as large as 1/16 of VREF (16 LSBs)
will be corrected since the flash comparators are connected
to ladder voltages that extend beyond the range specified by
the Voltage Estimator. For example, if 7/16 VREF < VIN < 9/16
VREF the Voltage Estimator's comparators tied to the tap
points below 9/16 VREF will output “1”s (000111). This is decoded by the estimator decoder to “10”. The eight flash comparators will be placed at the MSB Ladder tap points between
⅛ VREF and ⅛ VREF. The overlap of 1/16 VREF on each side of
the Voltage Estimator's span will automatically correct an error of up to 16 LSBs (16 LSBs = 312.5 mV for VREF = 5V). If
the first flash conversion determines that the input voltage is
between ⅛ VREF and 4/8 VREF − LSB/2, the Voltage Estimator's
output code will be corrected by subtracting “1”. This results
in a corrected value of “01”. If the first flash conversion determines that the input voltage is between 8/16 VREF − LSB/2
and ⅛ VREF, the Voltage Estimator's output code remains unchanged.
After correction, the 2-bit data from both the Voltage Estimator
and the first flash conversion are decoded to produce the five
MSBs. Decoding is similar to that of a 5-bit flash converter
since there are 32 tap points on the MSB Ladder. However,
31 comparators are not needed since the Voltage Estimator
places the eight comparators along the MSB Ladder where
reference tap voltages are present that fall above and below
the magnitude of VIN. Comparators are not needed outside
this selected range. If a comparator's output is a “0”, all comparators above it will also have outputs of “0” and if a
comparator's output is a “1”, all comparators below it will also
have outputs of “1”.
When RD goes low, a conversion is initiated and the data from
the previous conversion is available on the DB0–DB7 outputs.
Reading D0–D7 for the first two times after power-up produces random data. The data will be valid during the third
RD pulse that occurs after the first conversion.
2.3 WR-RD (WR then RD) Mode
The ADC08061/2 is in the WR-RD mode with the MODE pin
tied high. A conversion starts on the falling edge of the WR
signal. There are two options for reading the output data
which relate to interface timing. If an interrupt-driven scheme
is desired, the user can wait for the INT output to go low before
reading the conversion result (see Figure 3). Typically, INT
will go low 520 ns, maximum, after WR 's rising edge. However, if a shorter conversion time is desired, the processor
need not wait for INT and can exercise a read after only 350
ns (see Figure 2). If RD is pulled low before INT goes low,
INT will immediately go low and data will appear at the outputs. This is the fastest operating mode (tRD ≤ tINTL) with a
conversion time, including data access time, of 560 ns. Allowing 100 ns for reading the conversion data and the delay
between conversions gives a total throughput time of 660 ns
(throughput rate of 1.5 MHz).
2.4 WR-RD Mode with Reduced Interface
System Connection
CS and RD can be tied low, using only WR to control the start
of conversion for applications that require reduced digital interface while operating in the WR-RD mode (Figure 4). Data
will be valid approximately 705 ns following WR 's rising edge.
2.5 Multiplexer Addressing
The ADC08062 has 2 multiplexer inputs. These are selected
using the A0 multiplexer channel selection input. Table 1
shows the input code needed to select a given channel. The
multiplexer address is latched when received but the multiplexer channel is updated after the completion of the current
conversion.
2.0 DIGITAL INTERFACE
The ADC08061/2 has two basic interface modes which are
selected by connecting the MODE pin to a logic high or low.
TABLE 1. Multiplexer Addressing
2.1 RD Mode
With a logic low applied to the MODE pin, the converter is set
to Read mode. In this configuration (see Figure 1), a complete version is done by pulling RD low, and holding low, until
the conversion is complete and output data appears. This
typically takes 655 ns. The INT (interrupt) line goes low at the
end of conversion. A typical delay of 50 ns is needed between
the rising edge of RD (after the end of a conversion) and the
start of the next conversion (by pulling RD low). The RDY
output goes low after the falling edge of CS and goes high at
the end-of-conversion. It can be used to signal a processor
that the converter is busy or serve as a system Transfer Acknowledge signal. For the ADC08062 the data generated by
the first conversion cycle after power-up is from an unknown
channel.
Channel
0
VIN1
1
VIN2
The multiplexer address data must be valid at the time of
RD's falling edge, remain valid during the conversion, and can
go high after RD goes high when operating in the Read
Mode.
The multiplexer address data should be valid at or before the
time of WR's falling edge, remain valid while WR is low, and
go invalid after WR goes high when operating in the WR-RD
Mode.
3.0 REFERENCE INPUTS
The two VREF inputs of the ADC08061/2 are fully differential
and define the zero to full-scale input range of the A to D converter. This allows the designer to vary the span of the analog
input since this range will be equivalent to the voltage difference between VREF+ and VREF−. Transducers with minimum
output voltages above GND can also be compensated by
connecting VREF− to a voltage that is equal to this minimum
voltage. By reducing VREF (VREF = VREF+ − VREF−) to less than
5V, the sensitivity of the converter can be increased (i.e., if
VREF = 2.5V, then 1 LSB = 9.8 mV). The ADC08061/2's reference arrangement also facilitates ratiometric operation and
in many cases the ADC08061/2's power supply can be used
2.2 RD Mode Pipelined Operation
Applications that require shorter RD pulse widths than those
used in the Read mode as described above can be achieved
by setting RD's width between 200 ns–400 ns (Figure 5).
RD pulse widths outside this range will create conversion linearity errors. These errors are caused by exercising internal
interface logic circuitry using CS and/or RD during a conversion.
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ADC08062
A0
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with an operational amplifier. Any ringing or voltage shifts at
the op amp's output during the sampling period can result in
conversion errors.
Correct conversion results will be obtained for input voltages
greater than GND − 100 mV and less than V+ + 100 mV. Do
not allow the signal source to drive the analog input pin more
than 300 mV higher than V+, or more than 300 mV lower than
GND. The current flowing through any analog input pin should
be limited to 5 mA or less to avoid permanent damage to the
IC if an analog input pin is forced beyond these voltages. The
sum of all the overdrive currents into all pins must be less than
20 mA. Some sort of protection scheme should be used when
the input signal is expected to extend more than 300 mV beyond the power supply limits. A simple protection network
using resistors and diodes is shown in Figure 9.
4.0 ANALOG INPUT AND SOURCE IMPEDANCE
The ADC08061/2's analog input circuitry includes an analog
switch with an “on” resistance of 70Ω and capacitance of
1.4 pF and 12 pF (see Figure 7). The switch is closed during
the A/D's input signal acquisition time (while WR is low when
using the WR -RD Mode). A small transient current flows into
the input pin each time the switch closes. A transient voltage,
whose magnitude can increase as the source impedance increases, may be present at the input. So long as the source
impedance is less than 500Ω, the input voltage transient will
not cause errors and need not be filtered.
Large source impedances can slow the charging of the sampling capacitors and degrade conversion accuracy. Therefore, only signal sources with output impedances less than
500Ω should be used if rated accuracy is to be achieved at
the minimum sample time (100 ns maximum). A signal source
with a high output impedance should have its output buffered
6.0 INHERENT SAMPLE-AND-HOLD
An important benefit of the ADC08061/2's input architecture
is the inherent sample-and-hold (S/H) and its ability to measure relatively high speed signals without the help of an
external S/H. In a non-sampling converter, regardless of its
speed, the input must remain stable to at least ½ LSB throughout the conversion process if full accuracy is to be maintained.
Consequently, for many high speed signals, this signal must
be externally sampled and held stationary during the conversion.
The ADC08061 and ADC08062 are suitable for DSP-based
systems because of the direct control of the S/H through the
WR signal. The WR input signal allows the A/D to be synchronized to a DSP system's sampling rate or to other
ADC08061 and ADC08062s.
1108619
*Represents a multiplexer channel in the ADC08062.
FIGURE 7. ADC08061 and ADC08062 Equivalent Input Circuit Model
External Reference 2.5V Full-Scale
(Standard Application)
Power Supply as Reference
1108621
1108620
Note : Bypass capacitors consist of a 0.1 µF ceramic in parallel with a 10
µF bead tantalum.
13
11086 Version 6 Revision 2
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www.national.com
ADC08061/ADC08062
for transducer power as well as the VREF source. Ratiometric
operation is achieved by connecting VREF− to GND and connecting VREF+ and a transducer's power supply input to V+.
The ADC08061/2's linearity degrades when VREF+ − |VREF−|
is less than 2.0V.
The voltage at VREF− sets the input level that produces a digital output of all zeros. Though VIN is not itself differential, the
reference design affords nearly differential-input capability for
some measurement applications. Figure 7 shows one possible differential configuration.
It should be noted that, while the two VREF inputs are fully
differential, the digital output will be zero for any analog input
voltage if VREF− ≥ VREF+.
ADC08061/ADC08062
Input Not Referred to GND
* Signal source driving VIN(−) must be capable of sinking 5 mA.
1108622
FIGURE 8. Analog Input Options
1108623
Note the multiple bypass capacitors on the reference and power supply pins. VREF− should be bypass to analog ground using multiple capacitors if it is not grounded
(see Section 7.0 “Layout, Grounds, and Bypassing”). VIN1 is shown with an optional input protection network.
FIGURE 9. Typical Connection
The analog inputs should be isolated from noisy signal traces
to avoid having spurious signals couple to the input. Any external component (e.g., an input filter capacitor) connected
across the inputs should be returned to a very clean ground
point. Incorrectly grounding the ADC08061/2 will result in reduced conversion accuracy.
The V+ supply pin, VREF+, and VREF− (if not grounded) should
be bypassed with a parallel combination of a 0.1 µF ceramic
capacitor and a 10 µF tantalum capacitor placed as close as
possible to the supply pin using short circuit board traces. See
Figures 8, 9.
The ADC08061 can perform accurate conversions of fullscale input signals at frequencies from DC to more than
300 kHz (full power bandwidth) without the need of an external sample-and-hold (S/H).
7.0 LAYOUT, GROUNDS, AND BYPASSING
In order to ensure fast, accurate conversions from the
ADC08061/2, it is necessary to use appropriate circuit board
layout techniques. Ideally, the analog-to-digital converter's
ground reference should be low impedance and free of noise
from other parts of the system. Digital circuits can produce a
great deal of noise on their ground returns and, therefore,
should have their own separate ground lines. Best performance is obtained using separate ground planes for the
digital and analog parts of the system.
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14
11086 Version 6 Revision 2
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ADC08061/ADC08062
Physical Dimensions inches (millimeters) unless otherwise noted
Wide-Body Small-Outline Package (M)
Order Number ADC08061CIWM, or ADC08062CIWM
NS Package Number M20B
Dual-In-Line Package (N)
Order Number ADC08061BIN or ADC08062BIN
NS Package Number N20A
15
11086 Version 6 Revision 2
Print Date/Time: 2009/07/15 15:48:35
www.national.com
ADC08061/ADC08062 500 ns A/D Converter with S/H Function and Input Multiplexer
Notes
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