QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS The MC74AC258/74ACT258 is a quad 2-input multiplexer with 3-state outputs. Four bits of data from two sources can be selected using a common data select input. The four outputs present the selected data in the complement (inverted) form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with bus-oriented systems. • • • • Multiplexer Expansion by Tying Outputs Together Inverting 3-State Outputs Outputs Source/Sink 24 mA ′ACT258 Has TTL Compatible Inputs OE VCC 16 15 I0c 14 I1c 13 Zc 12 I0d 11 I1d 10 N SUFFIX CASE 648-08 PLASTIC Zd 9 PIN NAMES 1 2 3 4 5 6 7 8 S I0a I1a Za I0b I1b Zb GND S OE I0a–I0d I1a–I1d Za–Zd D SUFFIX CASE 751B-05 PLASTIC Common Data Select Input 3-State Output Enable Input Data Inputs from Source 0 Data Inputs from Source 1 3-State Multiplexer Outputs LOGIC SYMBOL TRUTH TABLE Output Enable Select Input OE S H L L L L X H H L L Data Inputs I0 X X X L H I1 X L H X X Outputs OE I0a I1a I0b I1b I0c I1c I0d I1d Z S Z H L H L Za H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance FACT DATA 5-1 Zb Zc Zd MC74AC258 MC74ACT258 FUNCTIONAL DESCRIPTION When the Output Enable input (OE) is HIGH, the outputs are forced to a high impedance state. If the outputs of the 3-state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure the Output Enable signals to 3-state devices whose outputs are tied together are designed so there is no overlap. The MC74AC258/74ACT258 is a quad 2-input multiplexer with 3-state outputs. It selects four bits of data from two sources under control of a common Select input (S). When the Select input is LOW, the I0x inputs are selected and when Select is HIGH, the I1x inputs are selected. The data on the selected inputs appears at the outputs in inverted form. The MC74AC258/74ACT258 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are shown below: Za = OE•(I1a•S+I0a•S) Zb = OE•(I1b•S+I0b•S) Zc = OE•(I1c•S+I0c•S) Zd = OE•(I1d•S+I0d•S) LOGIC DIAGRAM OE I0a I1a Za I0b I1b I0c Zb I1c Zc I0d I1d Zd Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. FACT DATA 5-2 S MC74AC258 MC74ACT258 MAXIMUM RATINGS* Symbol Parameter Value Unit –0.5 to +7.0 V V VCC DC Supply Voltage (Referenced to GND) Vin DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 Vout DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V Iin DC Input Current, per Pin ±20 mA Iout DC Output Sink/Source Current, per Pin ±50 mA ICC DC VCC or GND Current per Output Pin ±50 mA Tstg Storage Temperature –65 to +150 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage Vin, Vout DC Input Voltage, Output Voltage (Ref. to GND) tr, tf Input Rise and Fall Time (Note 1) ′AC Devices except Schmitt Inputs tr, tf Input Rise and Fall Time (Note 2) ′ACT Devices except Schmitt Inputs TJ Junction Temperature (PDIP) TA Operating Ambient Temperature Range IOH IOL Min Typ Max ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 VCC VCC @ 3.0 V 150 VCC @ 4.5 V 40 VCC @ 5.5 V 25 VCC @ 4.5 V 10 VCC @ 5.5 V 8.0 Unit V V ns/V ns/V 140 °C 85 °C Output Current — High –24 mA Output Current — Low 24 mA –40 1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. FACT DATA 5-3 25 MC74AC258 MC74ACT258 DC CHARACTERISTICS Symbol Parameter VCC (V) 74AC 74AC TA = +25°C TA = –40°C to +85°C Typ VIH VIL VOH Conditions Guaranteed Limits Minimum High Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC – 0.1 V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC – 0.1 V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 2.56 3.86 4.86 2.46 3.76 4.76 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 5.5 0.36 0.36 0.36 0.44 0.44 0.44 3.0 4.5 5.5 VOL Unit Maximum Low Level Output Voltage 3.0 4.5 5.5 0.002 0.001 0.001 IOUT = –50 µA V *VIN = VIL or VIH –12 mA IOH –24 mA –24 mA IOUT = 50 µA V V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA IIN Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µA VI = VCC, GND IOZ Maximum 3-State Current 5.5 ±0.5 ±5.0 µA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 5.5 75 mA VOLD = 1.65 V Max 5.5 –75 mA VOHD = 3.85 V Min 80 µA VIN = VCC or GND IOLD IOHD ICC †Minimum Dynamic Output Current Maximum Quiescent Supply Current 5.5 8.0 * All outputs loaded; thresholds on input associated with output under test. † Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. FACT DATA 5-4 MC74AC258 MC74ACT258 AC CHARACTERISTICS (For Figures and Waveforms — See Section 3) Symbol Parameter VCC* (V) 74AC 74AC TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. tPLH Propagation Delay In to Zn 3.3 5.0 2.0 1.5 6.0 4.5 9.5 7.5 1.5 1.0 11.0 8.5 ns 3-5 tPHL Propagation Delay In to Zn 3.3 5.0 2.0 1.5 5.0 4.0 8.5 6.5 1.5 1.0 9.5 7.0 ns 3-5 tPLH Propagation Delay S to Zn 3.3 5.0 3.0 2.0 7.5 6.0 12.0 9.5 2.5 1.5 14.0 10.5 ns 3-6 tPHL Propagation Delay S to Zn 3.3 5.0 2.5 1.5 7.5 5.5 11.5 9.0 2.0 1.5 13.0 10.0 ns 3-6 tPZH Output Enable Time 3.3 5.0 2.5 1.5 6.0 4.5 9.5 7.5 2.0 1.5 10.5 8.5 ns 3-7 tPZL Output Enable Time 3.3 5.0 2.0 1.5 5.5 5.5 9.0 7.0 1.5 1.0 10.0 8.0 ns 3-8 tPHZ Output Disable Time 3.3 5.0 2.5 2.0 5.5 5.5 10.0 8.5 2.0 1.5 11.0 9.0 ns 3-7 tPLZ Output Disable Time 3.3 5.0 2.0 1.5 5.5 5.0 9.0 7.0 2.0 1.5 10.0 8.0 ns 3-8 * Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. FACT DATA 5-5 MC74AC258 MC74ACT258 DC CHARACTERISTICS Symbol Parameter VCC (V) 74ACT 74ACT TA = +25°C TA = –40°C to +85°C Typ Guaranteed Limits Unit Conditions VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1 V or VCC – 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1 V or VCC – 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V 3.86 4.86 3.76 4.76 0.1 0.1 0.1 0.1 4.5 5.5 0.36 0.36 0.44 0.44 V *VIN = VIL or VIH 24 mA IOL 24 mA ±0.1 ±1.0 µA VI = VCC, GND 1.5 mA VI = VCC – 2.1 V ±5.0 µA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 5.5 75 mA VOLD = 1.65 V Max 5.5 –75 mA VOHD = 3.85 V Min 80 µA VIN = VCC or GND 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 IIN Maximum Input Leakage Current 5.5 ∆ICCT Additional Max. ICC/Input 5.5 IOZ Maximum 3-State Current 5.5 IOLD IOHD ICC †Minimum Dynamic Output Current Maximum Quiescent Supply Current 0.001 0.001 0.6 ±0.5 5.5 8.0 * All outputs loaded; thresholds on input associated with output under test. † Maximum test duration 2.0 ms, one output loaded at a time. FACT DATA 5-6 V V IOUT = –50 µA *VIN = VIL or VIH –24 mA IOH –24 mA IOUT = 50 µA MC74AC258 MC74ACT258 AC CHARACTERISTICS (For Figures and Waveforms — See Section 3) Symbol Parameter VCC* (V) 74ACT 74ACT TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. tPLH Propagation Delay In to Zn 5.0 2.0 6.5 8.5 1.5 9.5 ns 3-5 tPHL Propagation Delay In to Zn 5.0 2.0 5.5 7.5 1.5 8.0 ns 3-5 tPLH Propagation Delay S to Zn 5.0 3.0 7.5 10.5 2.0 11.5 ns 3-6 tPHL Propagation Delay S to Zn 5.0 1.5 7.0 9.5 1.5 11.0 ns 3-6 tPZH Output Enable Time 5.0 2.0 6.5 8.5 1.5 9.5 ns 3-7 tPZL Output Enable Time 5.0 2.0 6.5 8.5 1.5 9.5 ns 3-8 tPHZ Output Disable Time 5.0 1.5 7.0 9.0 1.0 10.0 ns 3-7 tPLZ Output Disable Time 5.0 2.0 6.0 8.0 1.5 9.0 ns 3-8 * Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 55 pF VCC = 5.0 V FACT DATA 5-7 MC74AC258 MC74ACT258 OUTLINE DIMENSIONS N SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B F C DIM A B C D F G H J K L M S L S SEATING PLANE –T– K H G D M J 16 PL 0.25 (0.010) T A M M D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] –TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ FACT DATA 5-8 *MC74AC258/D* MC74AC258/D