Cypress CY7C139-25JXC 4k x 8/9 dual-port static ram with sem, int, busy Datasheet

CY7C138 CY7C1394K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
CY7C138
CY7C139
4K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
Features
• True Dual-Ported memory cells that allow simultaneous
reads of the same memory location
• 4K x 8 organization (CY7C138)
• 4K x 9 organization (CY7C139)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 160 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Available in 68-pin PLCC
• Pb-Free packages available
Functional Description
are included on the CY7C138/9 to handle situations when
multiple processors access the same piece of data. Two ports
are provided permitting independent, asynchronous access
for reads and writes to any location in memory. The
CY7C138/9 can be utilized as a standalone 8/9-bit dual-port
static RAM or multiple devices can be combined in order to
function as a 16/18-bit or wider master/slave dual-port static
RAM. An M/S pin is provided for implementing 16/18-bit or
wider memory applications without the need for separate
master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs,
communications
status
buffering,
and
dual-port
video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags
are provided on each port (BUSY and INT). BUSY signals that
the port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from
one port to the other to indicate that a shared resource is in
use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared
resource is in use. An automatic power-down feature is
controlled independently on each port by a chip enable (CE)
pin or SEM pin.
The CY7C138 and CY7C139 are available in a 68-pin PLCC.
The CY7C138 and CY7C139 are high-speed CMOS 4K x 8
and 4K x 9 dual-port static RAMs. Various arbitration schemes
Logic Block Diagram
R/WL
R/WR
CEL
OE L
CER
OER
(7C139)I/O8L
I/O7L
I/O
CONTROL
I/O0L
I/O8R (7C139)
I/O7R
I/O
CONTROL
I/O0R
[1, 2]
BUSYR
BUSY L[1, 2]
A11L
ADDRESS
DECODER
A0L
CEL
OEL
INTERRUPT
SEMAPHORE
ARBITRATION
A0R
CE R
OER
R/WR
R/WL
SEML
INTL[2]
A11R
ADDRESS
DECODER
MEMORY
ARRAY
SEMR
INTR[2]
M/S
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
Document #: 38-06037 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 6, 2005
CY7C138
CY7C139
Pin Configurations
\
9 8 7 6
A6L
A8L
A7L
5 4 3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
CY7C138/9
52
51
50
49
48
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A5R
47
46
45
44
A5L
A4L
A3L
A7R
A6R
A
9R
A8R
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
R/W
R
SEM
R
CER
NC
NC
GND
NC
A
11R
A10R
21
22
23
24
25
26
I/O7R
I/O3R
I/O4R
I/O5R
I/O6R
10
11
12
13
14
15
16
17
18
19
20
NC [3]
OER
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
NC
NC
VCC
NC
A
11L
A
10L
A9L
NC [4]
OE L
R/W L
SEM
L
CEL
I/O 1L
I/O 0L
68-Pin PLCC
Top View
Pin Definitions
Left Port
Right Port
Description
I/O0L–7L(8L)
I/O0R–7R(8R)
Data Bus Input/Output
A0L–11L
A0R–11R
Address Lines
CEL
CER
Chip Enable
OEL
OER
Output Enable
R/WL
R/WR
Read/Write Enable
SEML
SEMR
Semaphore Enable. When asserted LOW, allows access to eight
semaphores. The three least significant bits of the address lines will
determine which semaphore to write or read. The I/O0 pin is used when
writing to a semaphore. Semaphores are requested by writing a 0 into the
respective location.
INTL
INTR
Interrupt Flag. INTL is set when right port writes location FFE and is cleared
when left port reads location FFE. INTR is set when left port writes location
FFF and is cleared when right port reads location FFF.
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
Selection Guide
7C138-15
7C139-15
Maximum Access Time (ns)
7C138-25
7C139-25
7C138-35
7C139-35
7C138-55
7C139-55
Unit
15
25
35
55
ns
Maximum Operating Current
Commercial
220
180
160
160
mA
Maximum Standby Current for ISB1
Commercial
60
40
30
30
mA
Notes:
3. I/O8R on the CY7C139.
4. I/O8L on the CY7C139.
Document #: 38-06037 Rev. *B
Page 2 of 16
CY7C138
CY7C139
Maximum Ratings[5]
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Range
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
Commercial
DC Input Voltage[6] ......................................... –0.5V to +7.0V
Industrial
Ambient
Temperature
VCC
0°C to +70°C
5V ± 10%
–40°C to +85°C
5V ± 10%
Electrical Characteristics Over the Operating Range
7C138-15
7C139-15
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 4.0 mA
Min.
Max.
2.4
7C138-25
7C139-25
Min.
2.4
0.4
VIH
Max.
2.2
V
0.4
2.2
0.8
Unit
V
V
VIL
Input LOW Voltage
0.8
V
IIX
Input Leakage Current
GND < VI < VCC
–10
+10
–10
+10
µA
IOZ
Output Leakage Current
Output Disabled, GND < VO < VCC
–10
+10
–10
+10
µA
ICC
Operating Current
VCC = Max.,
IOUT = 0 mA,
Outputs Disabled
Com’l
180
mA
ISB1
Standby Current
(Both Ports TTL Levels)
CEL and CER > VIH,
f = fMAX[7]
Com’l
ISB2
Standby Current
(One Port TTL Level)
CEL and CER > VIH,
f = fMAX[7]
Com’l
Standby Current
(Both Ports CMOS Levels)
Both Ports
CE and CER > VCC – 0.2V,
VIN > VCC – 0.2V
or VIN < 0.2V, f = 0[7]
Com’l
Standby Current
(One Port CMOS Level)
One Port
CEL or CER > VCC – 0.2V,
VIN > VCC – 0.2V or
VIN < 0.2V, Active
Port Outputs, f = fMAX[7]
Com’l
ISB3
ISB4
220
Ind
190
60
40
130
110
Ind
50
Ind
mA
120
15
Ind
Ind
mA
15
mA
30
125
100
mA
115
Notes:
5. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
6. Pulse width < 20 ns.
7. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
standby ISB3.
Document #: 38-06037 Rev. *B
Page 3 of 16
CY7C138
CY7C139
Electrical Characteristics Over the Operating Range (continued)
]
7C138-35
7C139-35
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 4.0 mA
Min.
7C138-55
7C139-55
Max.
2.4
Input LOW Voltage
IIX
Input Leakage Current
GND < VI < VCC
–10
+10
IOZ
Output Leakage Current
Output Disabled, GND < VO < VCC
–10
+10
ICC
Operating Current
VCC = Max.,
IOUT = 0 mA,
Outputs Disabled
Com’l
Ind
Standby Current
(Both Ports TTL Levels)
CEL and CER > VIH,
f = fMAX[7]
Standby Current
(One Port TTL Level)
ISB3
ISB4
V
2.2
VIL
0.8
Unit
V
0.4
2.2
ISB2
Max.
2.4
0.4
VIH
ISB1
Min.
V
0.8
V
–10
+10
µA
–10
+10
µA
160
160
mA
180
180
Com’l
30
30
Ind
40
40
CEL and CER > VIH,
f = fMAX[7]
Com’l
100
100
Ind
110
110
Standby Current
(Both Ports CMOS Levels)
Both Ports
CE and CER > VCC – 0.2V,
VIN > VCC – 0.2V
or VIN < 0.2V, f = 0[7]
Com’l
15
15
Ind
30
30
Standby Current
(One Port CMOS Level)
One Port
CEL or CER > VCC – 0.2V,
VIN > VCC – 0.2V or
VIN < 0.2V, Active
Port Outputs, f = fMAX[7]
Com’l
90
90
Ind
100
100
mA
mA
mA
mA
Capacitance[8]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
10
pF
15
pF
AC Test Loads and Waveforms
5V
5V
R1 = 893Ω
OUTPUT
OUTPUT
C = 30 pF
R1 = 893Ω
RTH = 250Ω
OUTPUT
C = 5 pF
C = 30pF
R2 = 347Ω
R2 = 347Ω
VTH = 1.4V
(b) Thévenin Equivalent(Load 1)
(a) Normal Load (Load 1)
(c) Three-State Delay (Load 3)
ALL INPUT PULSES
OUTPUT
3.0V
C = 30 pF
GND
10%
90%
< 3 ns
90%
10%
< 3 ns
Load (Load 2)
Note:
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06037 Rev. *B
Page 4 of 16
CY7C138
CY7C139
Switching Characteristics Over the Operating Range[9]
7C138-15
7C139-15
Parameter
Description
Min.
Max.
7C138-25
7C139-25
Min.
Max.
7C138-35
7C139-35
Min.
Max.
7C138-55
7C139-55
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
tAA
Address to Data Valid
tOHA
Output Hold From Address Change
tACE
CE LOW to Data Valid
15
25
tDOE
OE LOW to Data Valid
10
15
tLZOE[10,11,12]
tHZOE[10,11,12]
tLZCE[10,11,12]
tHZCE[10,11,12]
tPU[12]
tPD[12]
OE Low to Low Z
15
3
CE LOW to Power-Up
25
10
0
CE HIGH to Power-Down
35
15
0
15
ns
35
55
ns
20
25
ns
3
20
ns
25
3
20
0
25
ns
3
3
15
ns
55
3
3
10
55
3
3
3
CE HIGH to High Z
35
3
3
OE HIGH to High Z
CE LOW to Low Z
25
ns
25
0
35
ns
ns
ns
55
ns
WRITE CYCLE
tWC
Write Cycle Time
15
25
35
55
ns
tSCE
CE LOW to Write End
12
20
30
40
ns
tAW
Address Set-Up to Write End
12
20
30
40
ns
tHA
Address Hold From Write End
2
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tPWE
Write Pulse Width
12
20
25
30
ns
tSD
Data Set-Up to Write End
10
15
15
20
ns
tHD
Data Hold From Write End
0
0
0
0
ns
tHZWE[11,12]
tLZWE[11,12]
tWDD[13]
tDDD[13]
R/W LOW to High Z
R/W HIGH to Low Z
10
3
15
3
20
3
25
3
ns
ns
Write Pulse to Data Delay
30
50
60
70
ns
Write Data Valid to Read Data Valid
25
30
35
40
ns
15
20
20
45
ns
[14]
BUSY TIMING
tBLA
BUSY LOW from Address Match
tBHA
BUSY HIGH from Address Mismatch
15
20
20
40
ns
tBLC
BUSY LOW from CE LOW
15
20
20
40
ns
tBHC
BUSY HIGH from CE HIGH
15
20
20
35
ns
tPS
Port Set-Up for Priority
tWB
R/W LOW after BUSY LOW
0
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH
13
20
30
40
ns
tBDD[15]
BUSY HIGH to Data Valid
5
5
Note 15
5
Note 15
5
Note 15
ns
Note 15
ns
Notes:
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
10. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
11. Test conditions used are Load 3.
12. This parameter is guaranteed but not tested.
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.
15. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual).
Document #: 38-06037 Rev. *B
Page 5 of 16
CY7C138
CY7C139
Switching Characteristics Over the Operating Range[9] (continued)
7C138-15
7C139-15
Parameter
Description
Min.
Max.
7C138-25
7C139-25
Min.
Max.
7C138-35
7C139-35
Min.
Max.
7C138-55
7C139-55
Min.
Max.
Unit
[14]
INTERRUPT TIMING
tINS
INT Set Time
15
25
25
30
ns
tINR
INT Reset Time
15
25
25
30
ns
SEMAPHORE TIMING
tSOP
SEM Flag Update Pulse (OE or SEM)
10
10
15
20
ns
tSWRD
SEM Flag Write to Read Time
5
5
5
5
ns
tSPS
SEM Flag Contention Window
5
5
5
5
ns
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[16, 17]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (Either Port CE/OE Access)[16, 18, 19]
SEM or CE
tHZCE
tACE
OE
tLZOE
tHZOE
tDOE
tLZCE
DATA VALID
DATA OUT
tPU
ICC
tPD
ISB
Notes:
16. R/W is HIGH for read cycle.
17. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.
18. Address valid prior to or coincident with CE transition LOW.
19. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.
Document #: 38-06037 Rev. *B
Page 6 of 16
CY7C138
CY7C139
Switching Waveforms (continued)
Read Timing with Port-to-Port Delay (M/S = L)[20, 21]
tWC
ADDRESS R
MATCH
t
R/W R
PWE
t
DATA INR
t
SD
HD
VALID
ADDRESS L
MATCH
tDDD
DATAOUTL
VALID
tWDD
Write Cycle No. 1: OE Three-States Data I/Os (Either Port)[22, 23, 24]
tWC
ADDRESS
tSCE
SEM OR CE
tAW
tHA
tPWE
R/W
tSA
tSD
DATA IN
tHD
DATA VALID
OE
t
tHZOE
DATA OUT
LZOE
HIGH IMPEDANCE
Notes:
20. BUSY = HIGH for the writing port.
21. CEL = CER = LOW.
22. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to
be placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write
pulse can be as short as the specified tPWE.
24. R/W must be HIGH during all address transitions.
Document #: 38-06037 Rev. *B
Page 7 of 16
CY7C138
CY7C139
Switching Waveforms (continued)
Write Cycle No. 2: R/W Three-States Data I/Os (Either Port)[22, 24, 25]
tWC
ADDRESS
tSCE
tHA
SEM OR CE
tAW
tSA
R/W
tPWE
tSD
tHD
DATA VALID
DATA IN
tLZWE
HIGH IMPEDANCE
tHZWE
DATA OUT
Semaphore Read After Write Timing, Either Side[26]
tOHA
tAA
A0–A 2
VALID ADDRESS
VALID ADDRESS
tAW
tACE
tHA
SEM
tSCE
tSOP
tSD
I/O0
DATAIN VALID
tSA
tPWE
DATAOUT VALID
tHD
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
Notes:
25. Data I/O pins enter high impedance when OE is held LOW during write.
26. CE = HIGH for the duration of the above timing (both write and read cycle).
Document #: 38-06037 Rev. *B
Page 8 of 16
CY7C138
CY7C139
Switching Waveforms (continued)
Timing Diagram of Semaphore Contention[27, 28, 29]
A0L–A2L
MATCH
R/WL
SEML
tSPS
A0R–A2R
MATCH
R/WR
SEMR
Timing Diagram of Read with BUSY (M/S = HIGH)[21]
tWC
ADDRESS R
MATCH
tPWE
R/WR
tSD
DATA INR
tHD
VALID
tPS
ADDRESS L
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATAOUTL
VALID
tWDD
Write Timing with Busy Input (M/S=LOW)
tPWE
R/W
BUSY
tWB
tWH
Notes:
27. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH
28. Semaphores are reset (available to both ports) at cycle start.
29. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
Document #: 38-06037 Rev. *B
Page 9 of 16
CY7C138
CY7C139
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)[30]
CEL Valid First:
ADDRESS L,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESS L,R
ADDRESS MATCH
CER
tPS
CEL
tBLC
tBHC
BUSY L
Busy Timing Diagram No. 2 (Address Arbitration)[30]
Left Address Valid First:
tRC or tWC
ADDRESS L
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESS R
tBLA
tBHA
BUSYR
Right Address Valid First:
tRC or tWC
ADDRESS R
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESS L
tBLA
tBHA
BUSY L
Note:
30. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
Document #: 38-06037 Rev. *B
Page 10 of 16
CY7C138
CY7C139
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR:
tWC
ADDRESS L
WRITE FFF
tHA[31]
CE L
R/W L
INTR
tINS[32]
Right Side Clears INTR:
tRC
ADDRESSR
READ FFF
CE R
tINR[32]
R/W R
OE R
INT R
Right Side Sets INTL:
tWC
ADDRESSR
WRITE FFE
tHA[31]
CER
R/W R
INT L
tINS[32]
Left Side Clears INTL:
tRC
ADDRESSR
READ FFE
CE L
tINR [32]
R/W L
OE L
INT L
Notes:
31. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
32. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document #: 38-06037 Rev. *B
Page 11 of 16
CY7C138
CY7C139
Architecture
The CY7C138/9 consists of an array of 4K words of 8/9 bits
each of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be utilized
for port–to–port communication. Two semaphore (SEM)
control pins are used for allocating shared resources. With the
M/S pin, the CY7C138/9 can function as a master (BUSY pins
are outputs) or as a slave (BUSY pins are inputs). The
CY7C138/9 has an automatic power-down feature controlled
by CE. Each port is provided with its own output enable control
(OE), which allows data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the OE pin (see Write Cycle No. 1
waveform) or the R/W pin (see Write Cycle No. 2 waveform).
Data can be written to the device tHZOE after the OE is
deasserted or tHZWE after the falling edge of R/W. Required
inputs for non-contention operations are summarized in
Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must be met before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE is asserted. If the user of the CY7C138/9 wishes to access
a semaphore flag, then the SEM pin must be asserted instead
of the CE pin.
Interrupts
The interrupt flag (INT) permits communications between
ports.When the left port writes to location FFF, the right port’s
interrupt flag (INTR) is set. This flag is cleared when the right
port reads that same location. Setting the left port’s interrupt
flag (INTL) is accomplished when the right port writes to
location FFE. This flag is cleared when the left port reads
location FFE. The message at FFF or FFE is user-defined.
See Table 2 for input requirements for INT. INTR and INTL are
push-pull outputs and do not require pull-up resistors to
operate. BUSYL and BUSYR in master mode are push-pull
outputs and do not require pull-up resistors to operate.
Busy
The CY7C138/9 provides on-chip arbitration to alleviate simultaneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within tPS of
each other the Busy logic will determine which port has
access. If tPS is violated, one port will definitely gain
permission to the location, but it is not guaranteed which one.
BUSY will be asserted tBLA after an address match or tBLC
after CE is taken LOW.
Document #: 38-06037 Rev. *B
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components.Writing of slave devices must be
delayed until after the BUSY input has settled. Otherwise, the
slave chip may begin a write cycle during a contention
situation.When presented as a HIGH input, the M/S pin allows
the device to be used as a master and therefore the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.
Semaphore Operation
The CY7C138/9 provides eight semaphore latches, which are
separate from the dual-port memory locations. Semaphores
are used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is
in use. For example, if the left port wants to request a given
resource, it sets a latch by writing a zero to a semaphore
location. The left port then verifies its success in setting the
latch by reading it. After writing to the semaphore, SEM or OE
must be deasserted for tSOP before attempting to read the
semaphore. The semaphore value will be available tSWRD +
tDOE after the rising edge of the semaphore write. If the left port
was successful (reads a zero), it assumes control over the
shared resource, otherwise (reads a one) it assumes the right
port has control and continues to poll the semaphore.When
the right side has relinquished control of the semaphore (by
writing a one), the left side will succeed in gaining control of
the a semaphore.If the left side no longer requires the
semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access.When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an unused semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows
sample semaphore operations.
When reading a semaphore, all eight/nine data lines output the
semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will
definitely be obtained by one side or the other, but there is no
guarantee which side will control the semaphore.
Initialization of the semaphore is not automatic and must be
reset during initialization program at power-up. All
semaphores on both sides should have a one written into them
at initialization from both sides to assure that they will be free
when needed.
Page 12 of 16
CY7C138
CY7C139
Table 1. Non-Contending Read/Write
Inputs
CE
Outputs
R/W
OE
SEM
H
X
X
H
High Z
Power-Down
H
H
L
L
Data Out
Read Data in Semaphore
X
X
H
X
High Z
I/O Lines Disabled
X
L
Data In
Write to Semaphore
H
I/O0-7/8
Operation
L
H
L
H
Data Out
Read
L
L
X
H
Data In
Write
L
X
X
L
Illegal Condition
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)
Left Port
Function
Right Port
R/W
CE
OE
A0-11
INT
Set Left INT
X
X
X
X
L
Reset Left INT
X
L
L
FFE
H
Set Right INT
L
L
X
FFF
X
Reset Right INT
X
X
X
X
X
R/W
CE
OE
A0-11
INT
L
L
X
FFE
X
X
X
X
X
X
X
X
X
X
L
X
L
L
FFF
H
Table 3. Semaphore Operation Example
Function
I/O0-7/8 Left
I/O0-7/8 Right
No action
1
1
Semaphore free
Left port writes semaphore
0
1
Left port obtains semaphore
Right port writes 0 to semaphore
0
1
Right side is denied access
Left port writes 1 to semaphore
1
0
Right port is granted access to semaphore
Left port writes 0 to semaphore
1
0
No change. Left port is denied access
Right port writes 1 to semaphore
0
1
Left port obtains semaphore
Left port writes 1 to semaphore
1
1
No port accessing semaphore address
Right port writes 0 to semaphore
1
0
Right port obtains semaphore
Right port writes 1 to semaphore
1
1
No port accessing semaphore
Left port writes 0 to semaphore
0
1
Left port obtains semaphore
Left port writes 1 to semaphore
1
1
No port accessing semaphore
Document #: 38-06037 Rev. *B
Status
Page 13 of 16
CY7C138
CY7C139
ICC
1.0
ISB3
0.8
0.6
0.4
0.2
0.0
4.0
4.5
5.0
5.5
ICC
1.0
ISB3
0.8
0.6
VCC = 5.0V
VIN = 5.0V
0.4
0.2
0.6
–55
6.0
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.4
1.6
1.3
1.4
NORMALIZED tAA
NORMALIZED tAA
125
1.2
1.1
TA = 25°C
1.2
1.0
VCC = 5.0V
0.8
0.9
0.8
4.0
4.5
5.0
5.5
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
200
160
120
VCC = 5.0V
TA = 25°C
80
40
0
0
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
1.0
25
0.6
–55
6.0
25
2.0
3.0
4.0
5.0
140
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
120
100
80
60
40
VCC = 5.0V
TA = 25°C
20
0
0.0
125
1.0
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
1.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT (mA)
1.2
1.2
NORMALIZED I,CC ISB
NORMALIZED ICC, ISB
1.4
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
2.0
3.0
4.0
5.0
OUTPUT VOLTAGE (V)
VIN = 5.0V
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
1.00
NORMALIZED ICC
DELTA tAA (ns)
NORMALIZED tPC
25.0
0.75
20.0
15.0
0.50
0.0
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
Document #: 38-06037 Rev. *B
5.0
0
VCC = 5.0V
TA = 25°C
VIN = 5.0V
1.0
VCC = 4.5V
TA = 25°C
5.0
0
NORMALIZED ICC vs. CYCLE TIME
0.75
10.0
0.25
1.25
0
200
400
600
800 1000
CAPACITANCE (pF)
0.50
10
28
40
66
CYCLE FREQUENCY (MHz)
Page 14 of 16
CY7C138
CY7C139
Ordering Information
4K x8 Dual-Port SRAM
Speed
(ns)
15
25
35
55
Ordering Code
CY7C138-15JC
Package
Name
J81
Package Type
Operating
Range
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C138-15JXC
J81
68-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C138-25JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C138-25JXC
J81
68-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C138-25JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7C138-35JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C138-35JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7C138-55JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C138-55JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
4K x9 Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Type
Package Type
Operating
Range
15
CY7C139-15JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
25
CY7C139-25JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
35
55
CY7C139-25JXC
J81
68-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C139-25JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7C139-35JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C139-35JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7C139-55JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C139-55JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
Package Diagram
68-Lead Plastic Leaded Chip Carrier J81
68-Lead Pb-Free Plastic Leaded Chip Carrier J81
51-85005-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06037 Rev. *B
Page 15 of 16
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C138
CY7C139
Document History Page
Document Title: CY7C138/CY7C139 4K x 8/9 Dual-Port Static RAM
Document Number: 38-06037
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110180
09/29/01
SZV
Change from Spec number: 38-00536 to 38-06037
*A
122287
12/27/02
RBI
Power up requirements added to Maximum Ratings Information
*B
393403
See ECN
YIM
Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C138-15JXC, CY7C138-25JXC, CY7C139-25JXC
Document #: 38-06037 Rev. *B
Page 16 of 16
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