MOTOROLA MC74HC58D

SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC74HC58 is identical to the MC74HC51 except that the outputs are
inverted. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
14
1
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 42 FETs or 10.5 Equivalent Gates
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
ORDERING INFORMATION
MC74HCXXN
MC74HCXXD
Plastic
SOIC
PIN ASSIGNMENT
LOGIC DIAGRAM
A1
B1
C1
D1
E1
F1
A2
B2
A1
1
14
VCC
A2
2
13
C1
12
B2
3
12
B1
13
C2
4
11
F1
D2
5
10
E1
Y2
6
9
D1
GND
7
8
Y1
1
8
9
10
11
2
3
6
C2
D2
Y1
Y1 = (A1•B1•C1) + (D1•E1•F1)
4
FUNCTION TABLES
Y2
Y2 = (A2•B2) + (C2•D2)
Inputs
5
A1 B1 C1 D1 E1
PIN 14 = VCC
PIN 7 = GND
Y1
H
H
H
X
X
X
X
X
X
H
H
H
Any other combinations
H
H
L
Inputs
Output
A2
10/95
 Motorola, Inc. 1995
1
REV 6
Output
F1
B2
C2
D2
Y2
H
H
X
X
X
X
H
H
Any other combinations
H
H
L
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MC74HC58
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
VOH
Vin = VIH or VIL |Iout|
|Iout|
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL |Iout|
|Iout|
Iin
ICC
4.0 mA
5.2 mA
4.0 mA
5.2 mA
V
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
2
20
40
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC74HC58
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
PLH,
tPHL
Maximum Propagation Delay, Any Input to Output Y
(Figures 1 and 2)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Symbol
Cin
Parameter
Unit
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Section)*
pF
22
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
tr
tf
90%
ANY
INPUT
50%
10%
VCC
TEST POINT
OUTPUT
GND
tPLH
DEVICE
UNDER
TEST
tPHL
CL*
90%
50%
10%
OUTPUT Y
tTLH
* Includes all probe and jig capacitance
tTHL
Figure 1. Switching Waveforms
Figure 2. Test Circuit
EXPANDED LOGIC DIAGRAM
A1
B1
C1
D1
E1
F1
A2
B2
C2
D2
1
12
13
8
9
Y1
10
11
2
3
6
4
Y2
5
PIN 14 = VCC
PIN 7 = GND
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
MC74HC58
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
14
8
1
7
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
B
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
C
J
N
H
G
D
SEATING
PLANE
K
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
–A–
14
1
P 7 PL
0.25 (0.010)
7
G
D
0.25 (0.010)
M
T
F
J
M
K
14 PL
B
S
M
R X 45°
C
SEATING
PLANE
B
M
A
S
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
8
–B–
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.039
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0°
7°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7°
0°
0.228 0.244
0.010 0.019
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◊
CODELINE
4
*MC74HC58/D*
MC74HC58/D
High–Speed CMOS Logic Data
DL129 — Rev 6