OKI MSM514800DSL-XXJS 524,288-word x 8-bit dynamic ram : fast page mode type Datasheet

FEDD514800DSL-01
This version : Dec. 2000
1Semiconductor
MSM514800D/DSL
524,288-Word x 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MSM514800D/DSL is a 524,288-word × 8-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS
technology. The MSM514800D/DSL achieves high integration, high-speed operation, and low-power
consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS
process. The MSM514800D/DSL is available in a 28-pin plastic SOJ. The MSM514800DSL (the self-refresh and
lower-power version) is specially designed for lower-power applications.
FEATURES
•
524,288-word × 8-bit configuration
•
Single 5V power supply, ±10% tolerance
•
Input
: TTL compatible, low input capacitance
•
Output
: TTL compatible, 3-state
•
Refresh
: 1,024 cycles/16 ms, 1,024 cycles/128 ms (SL Version)
•
Fast page mode, read modify write capability
•
CAS before RAS refresh, hidden refresh, RAS-only refresh capability
•
CAS before RAS self-refresh capability (SL version)
•
Package options:
28-pin 400mil plastic SOJ
(SOJ28-P-400-1.27)
(Product : MSM514800D/DSL-xxJS)
xx : indicates speed rank.
PRODUCT FAMILY
Family
MSM514800D/DSL
Access Time (Max.)
Cycle Time
Power Dissipation
tRAC
tAA
tCAC
tOEA
(Min.)
Operating (Max.)
Standby (Max.)
60ns
30ns
20ns
20ns
110ns
660mW
70ns
35ns
20ns
20ns
130ns
605mW
5.5mW/
1.1mW (SL Version)
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FEDD514800DSL-01
1Semiconductor
This Version: Dec.2000
MSM514800D/DSL
PIN CONFIGRATION (TOP VIEW)
VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
NC 6
WE 7
RAS 8
A9R 9
A0 10
A1 11
A2 12
A3 13
VCC 14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
DQ8
DQ7
DQ6
DQ5
CAS
OE
NC
A8
A7
A6
A5
A4
VSS
28-Pin Plastic SOJ
Pin Name
Function
A0 - A8, A9R
Address Input
RAS
Row Address Strobe
CAS
Column Address Strobe
DQ1 – DQ8
Data Input/Data Output
OE
Output Enable
WE
Write Enable
VCC
Power Supply (5V)
VSS
Ground (0V)
NC
No Connection
Note : The same power supply voltage must be provided to every VCC pin, and the same
GND voltage level must be provided to every VSS pin.
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FEDD514800DSL-01
1Semiconductor
MSM514800D/DSL
This Version: Dec.2000
BLOCK DIAGRAM
Timing
Generator
RAS
Timing
Generator
CAS
9
9
Internal
Address
Counter
A0 – A8
9
A9R
Column
Address
Buffers
1
Row
Address
Buffers
Refresh
Control Clock
10
Row
Decoders
Word
Drivers
Column Decoders
Sense Amplifiers
WE
Write
Clock
Generator
8
I/O
Selector
OE
8
Output
Buffers
8
Input
Buffers
8
8
8
DQ1 – DQ8
8
Memory
Cells
VCC
On Chip
VBB Generator
VSS
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FEDD514800DSL-01
1Semiconductor
MSM514800D/DSL
This Version: Dec.2000
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to VSS
VT
−1.0 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
−55 to 150
°C
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
Min.
Typ.
Max.
Unit
VCC
VSS
VIH
VIL
4.5
5.0
5.5
V
0
0
0
V
2.4

6.5 *1
V
−1.0 *2

0.8
V
Notes: *1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with
respect to the point at which VCC is applied).
*2. The input voltage is VSS − 2.0V when the pulse width is less than 20ns (the pulse width is with
respect to the point at which VSS is applied).
Capacitance
(VCC = 5V ± 10%, Ta = 25°C, f=1MHz)
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance (A0 – A8, A9R)
CIN1

7
pF
Input Capacitance (RAS, CAS, WE, OE)
CIN2

7
pF
Output Capacitance (DQ1 – DQ8)
CI/O

8
pF
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FEDD514800DSL-01
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MSM514800D/DSL
This Version: Dec.2000
DC Characteristics
(VCC = 5V ± 10%, Ta = 0°C to 70°C)
Parameter
Symbol
Condition
Output High Voltage
VOH
IOH = −5.0mA
Output Low Voltage
VOL
IOL = 4.2mA
MSM514800
D/DSL-60
MSM514800
D/DSL-70
Min.
Max.
Min.
Max.
2.4
VCC
2.4
VCC
V
0
0.4
0
0.4
V
Unit
Note
Input Leakage Current
ILI
0V ≤ VI ≤ 6.5V ;
All other pins not
under test = 0V
−10
10
−10
10
µA
Output Leakage Current
ILO
DQ disable
0V ≤ VO ≤ 5.5V
−10
10
−10
10
µA
Average Power Supply
Current (Operating)
ICC1
RAS, CAS cycling,
tRC = Min.

120

110
mA
1,2
RAS, CAS = VIH

2

2
1
1

mA
RAS, CAS ≥
VCC – 0.2V

1

200

200
µA
1,5
Power Supply Current
(Standby)
ICC2
Average Power Supply
Current
(RAS-only Refresh)
ICC3
RAS cycling,
CAS = VIH,
tRC = Min.

120

110
mA
1,2
Power Supply Current
(Standby)
ICC5
RAS = VIH,
CAS = VIL,
DQ = enable

5

5
mA
1
Average Power Supply
Current
(CAS before RAS Refresh)
ICC6
RAS = cycling,
CAS before RAS

120

110
mA
1,2
Average Power Supply
Current (Fast Page Mode)
ICC7
RAS = VIL,
CAS cycling,
tPC = Min.

110

100
mA
1,3
Average Power Supply
Current (Battery Backup)
tRC = 125µs,
ICC10 CAS before RAS,
tRAS ≤ 1µs

300

300
µA
1,4,5
Average Power Supply
Current (CAS before RAS
Self-Refresh)
ICCS

300

300
µA
1,5
Notes: 1.
2.
3.
4.
5.
RAS ≤ 0.2V,
CAS ≤ 0.2V
ICC Max. is specified as ICC for output open condition.
The address can be changed once or less while RAS = VIL.
The address can be changed once or less while CAS = VIH.
VCC − 0.2V ≤ VIH ≤ 6.5V, − 1.0V ≤ VIL ≤ 0.2V.
SL version.
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FEDD514800DSL-01
1Semiconductor
MSM514800D/DSL
This Version: Dec.2000
AC Characteristic (1/2)
(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3
Parameter
Symbol
MSM514800
D/DSL-60
MSM514800
D/DSL-70
Unit
Note
Min.
Max.
Min.
Max.
tRC
110

130

ns
tRWC
155

185

ns
tPC
40

45

ns
tPRWC
85

100

ns
Access Time from RAS
tRAC

60

70
ns
4,5,6
Access Time from CAS
tCAC

20

20
ns
4,5
Access Time from Column Address
tAA

30

35
ns
4,6
Access Time from CAS Precharge
tCPA

35

40
ns
4
Access Time from OE
tOEA

20

20
ns
4
Output Low Impedance Time from CAS
tCLZ
0

0

ns
4
CAS to Data Output Buffer Turn-off Delay
Time
tOFF
0
15
0
20
ns
7
OE to Data Output Buffer Turn-off Delay
Time
tOEZ
0
15
0
20
ns
7
Transition Time
tT
3
50
3
50
ns
3
Refresh Period
tREF

16

16
ms
Refresh Period
tREF

128

128
ms
RAS Precharge Time
tRP
40

50

ns
RAS Pulse Width
tRAS
60
10,000
70
10,000
ns
RAS Pulse Width (Fast Page Mode)
tRASP
60
100,000
70
100,000
ns
RAS Hold Time
tRSH
15

20

ns
RAS Hold Time referenced to OE
tROH
15

20

ns
CAS Precharge Time (Fast Page Mode)
tCP
10

10

ns
CAS Pulse Width
tCAS
20
10,000
20
10,000
ns
CAS Hold Time
tCSH
60

70

ns
CAS to RAS Precharge Time
tCRP
10

10

ns
RAS Hold Time from CAS Precharge
tRHCP
35

40

ns
RAS to CAS Delay Time
tRCD
20
40
20
50
ns
5
RAS to Column Address Delay Time
tRAD
15
30
15
35
ns
6
Row Address Set-up Time
tASR
0

0

ns
Row Address Hold Time
tRAH
10

10

ns
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write Cycle
Time
11
6/14
FEDD514800DSL-01
1Semiconductor
MSM514800D/DSL
This Version: Dec.2000
AC Characteristic (2/2)
(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3
Parameter
Symbol
MSM514800
D/DSL-60
MSM514800
D/DSL-70
Min.
Max.
Min.
Max.
Unit
Note
Column Address Set-up Time
tASC
0

0

ns
Column Address Hold Time
tCAH
10

15

ns
Column Address Hold Time from RAS
tAR
50

55

ns
Column Address to RAS Lead Time
tRAL
30

35

ns
Read Command Set-up Time
tRCS
0

0

ns
Read Command Hold Time
tRCH
0

0

ns
8
Read Command Hold Time referenced to
RAS
tRRH
0

0

ns
8
Write Command Set-up Time
tWCS
0

0

ns
9
Write Command Hold Time
tWCH
15

15

ns
Write Command Hold Time from RAS
tWCR
50

55

Write Command Pulse Width
tWP
15

15

ns
OE Command Hold Time
tOEH
15

20

ns
Write Command to RAS Lead Time
tRWL
15

20

ns
Write Command to CAS Lead Time
tCWL
15

20

ns
Data-in Set-up Time
tDS
0

0

ns
10
Data-in Hold Time
tDH
15

15

ns
10
Data-in Hold Time from RAS
tDHR
50

55

OE to Data-in Delay Time
tOED
15

20

ns
CAS to WE Delay Time
tCWD
40

50

ns
9
Column Address to WE Delay Time
tAWD
60

65

ns
9
RAS to WE Delay Time
tRWD
90

100

ns
9
CAS Precharge WE Delay Time
tCPWD
65

70

ns
9
CAS Active Delay Time from RAS
Precharge
tRPC
10

10

ns
RAS to CAS Set-up Time
(CAS before RAS)
tCSR
10

10

ns
RAS to CAS Hold Time (CAS before RAS)
tCHR
15

15

ns
RAS Pulse Width
(CAS before RAS Self-Refresh)
tRASS
100

100

µs
11
RAS Precharge Time
(CAS before RAS Self-Refresh)
tRPS
110

130

ns
11
CAS Hold Time
(CAS before RAS Self-Refresh)
tCHS
−40

−50

ns
11
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FEDD514800DSL-01
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Notes:
This Version: Dec.2000
MSM514800D/DSL
1.
A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2.
The AC characteristics assume tT = 5ns.
3.
VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times
(tT) are measured between VIH and VIL.
4.
This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF.
5.
Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.)
limit, then the access time is controlled by tCAC.
6.
Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.)
limit, then the access time is controlled by tAA.
7.
tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit
condition and are not referenced to output voltage levels.
8.
tRCH or tRRH must be satisfied for a read cycle.
9.
tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early
write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle.
If tCWD ≥ tCWD (Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then
the cycle is a read modify write cycle and data out will contain data read from the selected cell; if
neither of the above sets of conditions is satisfied, then the condition of the data out (at access time)
is indeterminate.
10. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE
leading edge in an OE control write cycle, or a read modify write cycle.
11. SL version only.
8/14
FEDD514800DSL-01
1Semiconductor
MSM514800D/DSL
Timing Chart
•
Read Cycle
RAS
tRC
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRAD
VIL
WE
OE
VIH
VIL
tCRP
tRSH
tCAS
VIH
tRAL
tASR
Address
tRCD
tRAH
tASC
Row
tCAH
Column
tRCS
tRRH
VIH
tAA
VIL
tRCH
tROH
tOEA
VIH
VIL
tCAC
tRAC
DQ
tOFF
tOEZ
tCLZ
VOH
Valid Data-out
Open
VOL
“H” or “L”
•
Write Cycle (Early Write)
RAS
tRC
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRCD
VIH
tRAD
VIL
tRAL
tASR
Address
WE
OE
DQ
VIH
VIL
VIH
tCRP
tRSH
tCAS
tRAH
tASC
Row
tCAH
Column
tCWL
tWCS
tWP
tWCH
VIL
tRWL
VIH
VIL
VIH
VIL
tDS
Valid Data-in
tDH
Open
“H” or “L”
9/14
FEDD514800DSL-01
1Semiconductor
•
MSM514800D/DSL
Read Modify Write Cycle
tRWC
RAS
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRSH
tCAS
VIH
VIH
VIL
tCRP
tRAD
VIL
tASR
Address
tRCD
tRAH
Row
tASC
tCWL
tRWL
tCAH
Column
tRCS
tCWD
tWP
tRWD
WE
OE
VIH
VIL
tAWD
tAA
tOEH
tOEA
VIH
tOED
VIL
tCAC
tRAC
DQ
VI/OH
VI/OL
tOEZ
tCLZ
Valid
Data-out
tDS
tD
Valid
Data-in
“H” or “L”
10/14
FEDD514800DSL-01
1Semiconductor
•
MSM514800D/DSL
Fast Page Mode Read Cycle
tRASP
RAS
VIH
VIL
tRCD
tCRP
CAS
tCP
VIH
VIL
VIH
VIL
tRAD
tCSH
tRAH tASC
tCP
Row
tASC
Column
tCAH
Column
tRCH
tRCS
tRCH
VIH
VIL
tAA
tAA
VIH
VIL
tRAC
tCPA
tOFF
tOEZ
tCLZ
VOH
tAA
tOEA
tCAC
DQ
tASC
tRCS
tRCH
tCRP
tRAL
tCAH
Column
tOEA
OE
tRSH
tCAS
tCAS
tCAH
tRCS
WE
tRHCP
tCAS
tASR
Address
tRP
tPC
tCPA
tOFF
tCAC
VOL
tOFF
tCAC
tOEZ
tCLZ
Valid
Data-out
tRRH
tOEA
tOEZ
tCLZ
Valid
Data-out
Valid
Data-out
“H” or “L”
•
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
RAS
CAS
tPC
VIH
VIL
tCRP
tCP
VIH
VIL
tRAH
tASC
Row
tCSH
tCAH
tASC
Column
tWCS
VIH
tWCH
tWP
tCRP
tASC
Column
tRWL
tCWL
tCWL
tWCS
tRAL
tCAH
tWCH
tWP
tWCS
tWP
tWCH
VIL
tDS
DQ
tCAH
Column
tCWL
WE
tRSH
tCAS
tCAS
tRAD
VIL
VIH
tCP
tCAS
tASR
Address
tRCD
tRHPC
VIH
VIL
tD
Valid
Data-in
tDS
tD
Valid
Data-in
tDS
tD
Valid
Data-in
Note: OE = “H” or “L”
“H” or “L”
11/14
FEDD514800DSL-01
1Semiconductor
•
MSM514800D/DSL
Fast Page Mode Read Modify Write Cycle
tRASP
RAS
CAS
tCSH
VIH
VIL
tRCD
VIL
tCAH
tCWL
tASC
Row
tASC
tRAL
tCWL
Column
tCWD
tRCS
tCPWD
tCWD
tAWD
tAWD
tRCS
tPWD
tCWD
tCPWD
tCWL
tRWL
VIH
tAWD
VIL
tWP
tCPA
tDH
VIH
tWP
tD
tCAC
VI/OH
tOEZ
Out
VI/OL
tCLZ
tCPA
tAA
tOEA
tOED
VIL
In
tD
tDS
tOEA
tOED
tOEZ
tCAC
tWP
tROH
tDS
tAA
tDS
tOEA
Out
tOED
tOEZ
tCAC
In
Out
In
tCLZ
tCLZ
Note: Out = Valid Data-out, In = Valid Data-in
•
tCRP
tCAH
Column
tAA
DQ
tCAS
tASC
Column
tRAC
OE
tCP
tCAS
tRAD
VIL
VIH
tRP
tRSH
tCAH
tRCS
WE
tCP
tCAS
VIH
tRAH
tASR
Address
tPRWC
“H” or “L”
RAS-only Refresh Cycle
tRC
RAS
tRAS
VIH
tRP
VIL
tCRP
CAS
Address
DQ
tRPC
VIH
VIL
VIH
VIL
VOH
VOL
tASR
tRAH
Row
tOFF
Open
Note: WE, OE = “H” or “L”
“H” or “L”
12/14
FEDD514800DSL-01
1Semiconductor
•
MSM514800D/DSL
CAS before RAS Refresh Cycle
tRP
RAS
CAS
tRC
tRAS
VIH
VIL
tRPC
tCP
tRP
tCSR
tRPC
tCHR
VIH
VIL
tOFF
DQ
VOH
Open
VOL
“H” or “L”
Note: WE, OE, Address = “H” or “L”
•
Hidden Refresh Read Cycle
tRC
RAS
CAS
VIH
VIL
tCRP
tRCD
tRSH
tCHR
tRAD
VIL
VIH
VIL
tRAH
tASC
tCAH
Column
Row
tRCS
WE
tRP
tRP
VIH
tASR
Address
tRC
tRAS
tRAS
tCAC
tRRH
VIH
tRAL
VIL
tAA
tROH
OE
DQ
VIH
VIL
VOH
VOL
tOFF
tOEA
tRAC
tOEZ
tCLZ
Open
Valid Data-out
“H” or “L”
13/14
FEDD514800DSL-01
1Semiconductor
MSM514800D/DSL
Hidden Refresh Write Cycle
tRC
RAS
CAS
VIH
VIL
tCRP
tRAS
tRCD
tRSH
VIH
OE
DQ
tRP
tRAD
VIL
tRAL
tRAH
VIH
tASC
Row
VIL
tCAH
Column
tWCS
WE
tRP
tCHR
tASR
Address
tRC
tRAS
tWCH
VIH
VIL
tWP
VIH
VIL
tDS
VIH
tD
Valid Data-in
VIL
“H” or “L”
CAS before RAS Self-Refresh Cycle
tRP
RAS
tRPS
VIH
VIL
tRPC
tCP
CAS
tRASS
tRPC
tCSR
tCHS
VIH
VIL
tOFF
DQ
VOH
VOL
Open
Note: WE, OE, Address = “H” or
“L”
O
S
“H” or “L”
14/14
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