Order this document from Logic Marketing SEMICONDUCTOR TECHNICAL DATA The MC88914 is a high–speed, low power, hex divide–by–two D–type flip–flop with matched propagation delays, an internal power–on–reset, and external synchronous reset. With TTL compatible buffered clock and external reset inputs that are common to all flip–flops, the MC88914 is ideal for use in high–frequency systems as a clock driver, providing multiple outputs that are synchronous. • • • • • • LOW SKEW CMOS CLOCK DRIVER WITH RESET Power–on–Reset and External Synchronous Reset TTL Compatible Positive Edge–Triggered Clock Matched Outputs for Synchronous Applications Outputs Source/Sink 24mA Part–to–Part Skew of Less Than 3.0ns Guaranteed Rise and Fall Times for a Given Capacitive Load 14 1 Pinout: 14–Lead Plastic (Top View) VCC GND Q5 Q4 Q3 SR GND 14 13 12 11 10 9 8 N SUFFIX PLASTIC PACKAGE CASE 646–06 14 1 1 2 3 4 5 6 7 VCC GND Q0 Q1 Q2 CLK GND D SUFFIX PLASTIC PACKAGE CASE 751A–03 LOGIC DIAGRAM SR POWER–ON RESET CLK CLK D RST Q CLK Q0 D RST Q Q1 CLK D RST Q Q2 CLK D RST Q Q3 CLK D RST Q CLK Q4 NOTE: This diagram is provided only for understanding of logic operation and should not be used to estimate propagation delays 8/95 Motorola, Inc. 1995 1 REV 4 D RST Q Q5 MC88914 DC CHARACTERISTICS (unless otherwise specified) Parameter Symbol Unit Condition ICC Maximum Quiescent Supply Current 80 µA VIN = VCC or GND VCC = 5.5V, TA = Worst Case ICC Maximum Quiescent Supply Current 8.0 µA VIN = VCC or GND VCC = 5.5V, TA = 25°C ICCT Maximum Additional ICC/Input 1.5 mA VIN = VCC –2.1V VCC = 5.5V, TA = Worst Case DC CHARACTERISTICS TA = +25°C Symbol Parameter VCC Typ TA = –40 to +85°C Guaranteed Max Unit Conditions VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1V or VCC – 0.1V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1V or VCC – 0.1V VOH Minimum High Level 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V IOUT = –50µA V 3.86 4.86 3.76 4.76 *VIN = VIL or VIH IOH = –24mA –24mA 0.1 0.1 0.1 0.1 V IOUT = 50µA V 4.5 5.5 0.36 0.36 0.44 0.44 *VIN = VIL or VIH IOH = 24mA 24mA ±0.1 ±0.1 µA VI = VCC, GND 1.5 mA VI = VCC –2.1V 75 mA VOLD = 1.65V –75 mA VOHD = 3.85V 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 IIN Maximum Input 5.5 ICCT Maximum ICC/Input 5.5 IOLD Minimum Dynamic Output Current** 5.5 0.001 0.001 0.6 IOHD 5.5 * All outputs loaded; thresholds on inputs associated with output under test. ** Maximum test duration 20ms, one output at a time. MOTOROLA 2 TIMING SOLUTIONS BR1333 — REV 5 MC88914 AC CHARACTERISTICS (VCC = 5.0V ±10%) TA = 25°C CL = 50 pF Symbol Parameter VCC (V) Min fMAX Maximum Clock Frequency (50% Duty Cycle) 5.0 110 tPLH, tPHL Propagation Delay CLK to Qn, Qn 5.0 4.0 tPV Propagation Delay Variation CLK to Qn, Qn (see Note 1) 5.0 tPS Propagation Delay Skew (Qn, Qn) |tPHL Actual – tPLH Actual| tOS Output–to–Output Skew (Qn, Qn) |tp Qn – tp Qm| (see Note 2) Max TA = –40 to +85°C CL = 50 pF Min Max 110 9.0 4.0 Unit MHz 11 ns 3.0 3.0 ns 5.0 1.0 1.0 ns 5.0 1.0 1.0 ns trise Rise/Fall Time for Qn, Qn 5.0 3.0 4.0 ns (0.2 x VCC to 0.8 x VCC) tfall 1. For a given set of conditions (i.e., capacitive load, temperature and VCC) the variation from device to device is guaranteed to be less than or equal to the maximum. 2. Where tp Qn and tp Qm are the actual propagation delays (any combination of HIGH or LOW) for any two separate outputs from a given high transition of CLK. AC OPERATING REQUIREMENTS TA = 25°C CL = 50 pF Symbol Parameter Max TA = –40 to +85°C CL = 50 pF VCC (V) Min tW CLK Pulse Width (HIGH to LOW) 5.0 3.0 Min 3.0 Max Unit ns tSU Minimum Setup Time, HIGH or LOW SRB to Clock 5.0 3.5 3.5 ns tHD Minimum Hold Time, HIGH or LOW SRB to Clock 5.0 1.0 1.0 ns CAPACITANCE Symbol Parameter Typ Unit Condition CIN Input Capacitance 4.5 pF VCC = 5.0V CPD Power Dissipation Capacitance 30 pF VCC = 5.0V TIMING SOLUTIONS BR1333 — REV 5 3 MOTOROLA MC88914 OUTLINE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 646–06 ISSUE L 14 8 1 7 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. B A F DIM A B C D F G H J K L M N L C J N H G D K SEATING PLANE M D SUFFIX PLASTIC SOIC PACKAGE CASE 751A–03 ISSUE F –A – 14 1 P7 PL 0.25 (0.010) 7 G D 0.25 (0.010) M T F J M K 14 PL B S M R X 45° C SEATING PLANE B M A S MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0° 10° 1.01 0.39 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 –B – INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0° 10° 0.015 0.039 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7° 0° 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7° 0° 0.228 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] –TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA ◊ CODELINE 4 *MC88914/D* MC88914/D TIMING SOLUTIONS BR1333 — REV 5