MOTOROLA Current [email protected]/ADC SEMICONDUCTOR TECHNICAL DATA MC92300 Product Preview VITERBI Decoder for Digital TV DTVVIT This product preview describes a high performance device, a Viterbi Decoder, for Digital-TV applications according to the EBU defined DVB transmission standard for satellite and cable Set-Top systems. RESET_N VDCLK SYMCLK VTSTI[1:0] Viterbi Decoder - Capability Specification • • • • • • • VO VLCK VFF VEF SR[2:0] Operates at max. 50MBits/s output rate to work with all present DVB channels Implements K=7, (1718,1338) Viterbi decoder for rates 1/2, 2/3, 3/4, 5/6 and 7/8 with a survivor depth of 96 Code rate and synchronization control programmable via I2C standard serial bus Automatic rate selection and signal quality output (qval) Full/empty flag generation of input FIFO for system monitoring of VDCLK/BITCLK ratio Simplified system design with internal PLL for the generation of output BITCLK from the incoming VDCLK for all depuncturing modes Available in a 128QFP package SDA DSA[6:0] SCL Ordering Information Device Package MC92300CG 128QFP VEF VFF VC1[2:0] VC2[2:0] VDCLK BITCLK VC0,VC1[2:0] Synchronizer Viterbi Core Depuncturing FIFO VO APLL SYMCLK RESET_N VLCK SR QVAL I2C 2 VTSTI[1:0] BITCLK Interface 7 SCL DSA SDA Figure 1. Viterbi Decoder Block Diagram This document contains information on a new product. Specifications and information herein are subject to change without notice. MOTOROLA, INC. 1997 5/28/97 Product Description The Viterbi Decoder contains the Viterbi core logic, which operates the K=7 convolutional code and generates a lock indication after successful acquisition. The core works with the main clock BITCLK, which provides the output data VO (output of the Viterbi). This clock is generated by the integrated bit clock generator circuit and is adjusted according to the programmed depuncturing rate. The input to the chip are 3 bit soft decision data VC0/1 from the QPSK demodulator together with the associated demodulator clock VDCLK. Rate adjustment in accordance with the several depuncturing rates is achieved with the input FIFO. The data is read into the depuncturing logic with the internally generated BITCLK. The Viterbi block employs a method known as Syndrom Based Node Synchronization to achieve both I & Q symbol and punctured rate synchronization. The theory of the Syndrom Based Node Synchronization is based on the observation that the product of the incoming data and a syndrom is zero if there are no errors If errors are present in the data, the probability of 0’s and 1’s in the product increases. The possible states that the synchronizer has to deal with are a combination of the following factors: 1.The phasing of the received symbols. I & Q input streams can either be processed as-is or can be rotated 90o to account for constellation rotation in the receiver. 2. Determination of the framing of the I and Q bit streams so as to extract the correct symbol. There are four possible ways to frame the two bit stream and the synchronizer must determine the correct one. Generator Polynomials The Viterbi decoder is designed to decode bit streams encoded using the DVB standard generator polynomials (1718, 1338). Punctured Codes The Viterbi Decoder is able to decode a basic rate 1/2 convolutional code and the “standard” punctured codes for a k=7 constraint length. The punctured codes are shown in the table below. Specific bits of the original rate 1/2 code sequence are periodically deleted prior to transmission according to the entries in the table, where a 0 means that the bit is deleted and a 1 means that the bit is transmitted. Table 1 Deletion Map For Punctured Rate 1/2 Codes Coding Rate Puncture Map 1/2 1 1 2/3 11 10 3/4 110 101 5/6 11010 10101 7/8 1111010 1000101 I2C Interface The internal registers of the VITERBI are accessible via the I2C interface. After reset, default values are preprogrammed, so that no more configuration is necessary. APLL In order to allow a simple system design, a Analogue PLL is integrated for generation of the output Bit Clock. The following output frequencies Ro are generated for a given DVB transponder Bandwidth TBW respectively for a given input symbol rate Rs . TBW[MHz] 36 33 30 27 26 Rs[MHz] Ro[MHz] for rates 1/2 2/3 3/4 5/6 7/8 38.3 28.3 37.7 42.4 47.2 49.5 20.5 20.5 27.3 30.7 34.2 35.9 Rs/Ro 1 4/3 3/2 5/3 7/4 Application Synchronization Prior to outputting valid data the Viterbi decoder block must synchronize to the input data stream, i.e. remove any phase ambiguity in the received symbols and determine the punctured code rate transmitted MOTOROLA 2 The MC92300 is used in satellite receiver implementation for DVB. Packaging The MC92300 is available in a 128-pin Plastic Quad Flat Pack (128QFP) package. MC92300 Rev.1.3 Viterbi Decoder Pin Description R E S VV E T T RT S SE_ PV T T SA OE T I I E S V V NS [ [ T Y SSI T 1 0 _ N S S DO ] ] NC VDD OVDD VC1[2] OVSS VC1[1] OVSS VC1[0] OVSS SYMCLK OVSS VSS VDD OVDD VC0[2] OVSS VC0[1] OVSS VC0[0] OVSS OVSS VSS VDD OVDD VDCLK OVSS VDCLK_DIV2 O O VV VV DDSS DDSS O O V V VV D DSS D DSS T E ST TE _ S MT O_ DS EE O VV DD DD VSS OVSS OVDD VDD VSS OVSS BITCLK OVDD OVSS VLCK OVSS VO OVDD VDD VSS OVSS VFF OVDD VEF OVSS SR[2] SR[1] SR[0] OVDD VDD 128QFP OVSS VSS TESTSEL FREF TESTOUT V V O S S D D O V V OD D D DD C D V D CS S V S DV S S S S S O D D A L A A S S DD A A A A A D[ [ [ [ [ C D [ [ S T 0 1 234 56 L ] ] ] ] ] ] ] SYMCLK BITCLK VDCLK VDCLK_DIV2 RESET_N VLCK VFF VEF SR[2:0] VO VC0,VC1[2:0] SDA DSA[6:0] SCL TESTSEL, FREF, TESTOUT, VCOCTL MC92300 Rev.1.3 - System Clock (input clock) - System Clock (output clock) - Input Clock - VDCLK/2 - Asynchronous Reset - Viterbi Decoder in Lock - FIFO Full Flag - FIFO Empty Flag - Selected Rate - Viterbi Decoder Output - Soft Decision Input - Data Bus of I2C-interface - Slave Address of I2C-interface - Clock Line of I2C-interface OVVO V SDV S SDD S D OV VS SS S VTSTI[1:0] VTSTO RESET_ASYNC TEST_SE TEST_MODE - Test pins - Test output - Teset for Scan Test - Test pin for Scan Mode - Test pin for Scan Mode MOTOROLA Device Test Pins: 51, 56-62, 105, 110-115, 120 (don’t connect these pins) NOT CONNECTED Pins: 27, 33, 34, 88-94, 99-102 - APLL pins MOTOROLA 3 Motorola reserves the right to make changes without further notice to any products herein. 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